HexagonInstrInfo.h Source File (original) (raw)

13#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H

14#define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H

23#include

24#include

28#define GET_INSTRINFO_HEADER

29#include "HexagonGenInstrInfo.inc"

31namespace llvm {

33class HexagonSubtarget;

34class MachineBranchProbabilityInfo;

35class MachineFunction;

36class MachineInstr;

37class MachineOperand;

38class TargetRegisterInfo;

44 enum BundleAttribute {

45 memShufDisabledMask = 0x4

46 };

48 virtual void anchor();

50public:

63 int &FrameIndex) const override;

71 int &FrameIndex) const override;

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114 bool AllowModify) const override;

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139 std::unique_ptr

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148 unsigned ExtraPredCycles,

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158 unsigned NumTCycles, unsigned ExtraTCycles,

160 unsigned NumFCycles, unsigned ExtraFCycles,

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182 bool KillSrc, bool RenamableDest = false,

183 bool RenamableSrc = false) const override;

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247 bool SkipDead) const override;

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263 const char *Str,

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278 Register &SrcReg2, int64_t &Mask,

279 int64_t &Value) const override;

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286 unsigned *PredCost = nullptr) const override;

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303 unsigned &OffsetPos) const override;

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319 unsigned DefIdx,

321 unsigned UseIdx) const override;

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325 std::pair<unsigned, unsigned>

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373 bool isEndLoopN(unsigned Opcode) const;

374 bool isExpr(unsigned OpType) const;

388 bool isNewValue(unsigned Opcode) const;

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463 const;

474 unsigned &PredRegPos, unsigned &PredRegFlags) const;

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503 bool ToBigInstrs) const;

505 bool ToBigInstrs = true) const;

507 bool ToBigInstrs) const;

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540};

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543inline TargetInstrInfo::RegSubRegPair

546 return TargetInstrInfo::RegSubRegPair(O.getReg(), O.getSubReg());

547}

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549}

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551#endif

MachineInstrBuilder & UseMI

MachineInstrBuilder MachineInstrBuilder & DefMI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

MachineBasicBlock MachineBasicBlock::iterator MBBI

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

DXIL Forward Handle Accesses

uint64_t IntrinsicInst * II

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

This file defines the SmallVector class.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

short getEquivalentHWInstr(const MachineInstr &MI) const

int getDuplexOpcode(const MachineInstr &MI, bool ForBigCore=true) const

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

Remove the branching code at the end of the specific MBB.

bool isPredicated(const MachineInstr &MI) const override

Returns true if the instruction is already predicated.

bool isHVXMemWithAIndirect(const MachineInstr &I, const MachineInstr &J) const

short changeAddrMode_abs_io(short Opc) const

bool isRestrictNoSlot1Store(const MachineInstr &MI) const

short getRegForm(const MachineInstr &MI) const

bool isVecALU(const MachineInstr &MI) const

bool isCompoundBranchInstr(const MachineInstr &MI) const

bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const

Symmetrical. See if these two instructions are fit for duplex pair.

bool isJumpR(const MachineInstr &MI) const

ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override

Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...

std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override

Decompose the machine operand's target flags into two values - the direct target flag value and any o...

bool producesStall(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const

bool invertAndChangeJumpTarget(MachineInstr &MI, MachineBasicBlock *NewTarget) const

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

Store the specified register of the given register class to the specified stack frame index.

bool isPredictedTaken(unsigned Opcode) const

bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const

TargetInstrInfo overrides.

unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const

int getDotNewPredOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const

bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override

If the specified instruction defines any predicate or condition code register(s) used for predication...

unsigned getInvertedPredicatedOpcode(const int Opc) const

bool isPureSlot0(const MachineInstr &MI) const

bool doesNotReturn(const MachineInstr &CallMI) const

HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI) const

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override

Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....

bool getPredReg(ArrayRef< MachineOperand > Cond, Register &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const

bool isPredicatedNew(const MachineInstr &MI) const

bool isSignExtendingLoad(const MachineInstr &MI) const

bool isVecAcc(const MachineInstr &MI) const

bool reversePredSense(MachineInstr &MI) const

bool isQFPMul(const MachineInstr *MF) const

unsigned getAddrMode(const MachineInstr &MI) const

MCInst getNop() const override

bool isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const

bool mayBeNewStore(const MachineInstr &MI) const

short changeAddrMode_rr_ur(const MachineInstr &MI) const

Definition HexagonInstrInfo.h:531

bool isOperandExtended(const MachineInstr &MI, unsigned OperandNum) const

bool canExecuteInBundle(const MachineInstr &First, const MachineInstr &Second) const

Can these instructions execute at the same time in a bundle.

std::optional< unsigned > getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override

getOperandLatency - Compute and return the use operand latency of a given pair of def and use.

bool isAddrModeWithOffset(const MachineInstr &MI) const

bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override

Get the base register and byte offset of a load/store instr.

bool isValidOffset(unsigned Opcode, int Offset, const TargetRegisterInfo *TRI, bool Extend=true) const

bool isBaseImmOffset(const MachineInstr &MI) const

bool isAbsoluteSet(const MachineInstr &MI) const

short changeAddrMode_io_pi(short Opc) const

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

Emit instructions to copy a pair of physical registers.

const HexagonRegisterInfo & getRegisterInfo() const

Definition HexagonInstrInfo.h:53

short changeAddrMode_pi_io(short Opc) const

bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const override

For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...

bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override

Reverses the branch condition of the specified condition list, returning false on success and true if...

std::unique_ptr< PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override

Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...

bool isLoopN(const MachineInstr &MI) const

bool isSpillPredRegOp(const MachineInstr &MI) const

bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override

Check if the instruction or the bundle of instructions has store to stack slots.

ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override

Return an array that contains the direct target flag values and their names.

bool isIndirectCall(const MachineInstr &MI) const

short changeAddrMode_ur_rr(short Opc) const

bool isValidAutoIncImm(const EVT VT, const int Offset) const

bool hasNonExtEquivalent(const MachineInstr &MI) const

bool isConstExtended(const MachineInstr &MI) const

bool getIncrementValue(const MachineInstr &MI, int &Value) const override

If the instruction is an increment of a constant value, return the amount.

int getCondOpcode(int Opc, bool sense) const

MachineInstr * findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp, MachineBasicBlock *TargetBB, SmallPtrSet< MachineBasicBlock *, 8 > &Visited) const

Find the hardware loop instruction used to set-up the specified loop.

unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData, const MachineInstr &MI) const

bool isAccumulator(const MachineInstr &MI) const

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

Insert branch code into the end of the specified MachineBasicBlock.

unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override

Compute the instruction latency of a given instruction.

bool PredOpcodeHasJMP_c(unsigned Opcode) const

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

Load the specified register of the given register class from the specified stack frame index.

bool isNewValue(const MachineInstr &MI) const

HexagonInstrInfo specifics.

bool isDotCurInst(const MachineInstr &MI) const

bool validateBranchCond(const ArrayRef< MachineOperand > &Cond) const

bool isExtended(const MachineInstr &MI) const

bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override

Return true if it's profitable to predicate instructions with accumulated instruction latency of "Num...

bool isAsCheapAsAMove(const MachineInstr &MI) const override

int getMaxValue(const MachineInstr &MI) const

bool isPredicateLate(unsigned Opcode) const

short changeAddrMode_rr_ur(short Opc) const

bool hasPseudoInstrPair(const MachineInstr &MI) const

bool isNewValueInst(const MachineInstr &MI) const

unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI, const TargetSubtargetInfo *STI=nullptr) const override

Measure the specified inline asm to determine an approximation of its length.

bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override

int getNonDotCurOp(const MachineInstr &MI) const

bool isIndirectL4Return(const MachineInstr &MI) const

unsigned reversePrediction(unsigned Opcode) const

ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const override

Return an array that contains the bitmask target flag values and their names.

short changeAddrMode_rr_io(const MachineInstr &MI) const

Definition HexagonInstrInfo.h:528

InstrStage::FuncUnits getUnits(const MachineInstr &MI) const

short changeAddrMode_ur_rr(const MachineInstr &MI) const

Definition HexagonInstrInfo.h:534

unsigned getMemAccessSize(const MachineInstr &MI) const

bool predOpcodeHasNot(ArrayRef< MachineOperand > Cond) const

bool isComplex(const MachineInstr &MI) const

bool isPostIncrement(const MachineInstr &MI) const override

Return true for post-incremented instructions.

void setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const

short changeAddrMode_io_abs(const MachineInstr &MI) const

Definition HexagonInstrInfo.h:522

MachineBasicBlock::instr_iterator expandVGatherPseudo(MachineInstr &MI) const

int getDotNewOp(const MachineInstr &MI) const

void changeDuplexOpcode(MachineBasicBlock::instr_iterator MII, bool ToBigInstrs) const

bool isMemOp(const MachineInstr &MI) const

int getDotOldOp(const MachineInstr &MI) const

short getPseudoInstrPair(const MachineInstr &MI) const

bool hasUncondBranch(const MachineBasicBlock *B) const

short getNonExtOpcode(const MachineInstr &MI) const

bool isTailCall(const MachineInstr &MI) const override

void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override

Insert a noop into the instruction stream at the specified point.

bool isDeallocRet(const MachineInstr &MI) const

HexagonInstrInfo(const HexagonSubtarget &ST)

unsigned getCExtOpNum(const MachineInstr &MI) const

bool isSolo(const MachineInstr &MI) const

DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override

Create machine specific model for scheduling.

bool isLateSourceInstr(const MachineInstr &MI) const

bool isDotNewInst(const MachineInstr &MI) const

void translateInstrsForDup(MachineFunction &MF, bool ToBigInstrs=true) const

bool isTC1(const MachineInstr &MI) const

bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override

Test if the given instruction should be considered a scheduling boundary.

bool predCanBeUsedAsDotNew(const MachineInstr &MI, Register PredReg) const

unsigned getSize(const MachineInstr &MI) const

bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override

Return true if it's profitable for if-converter to duplicate instructions of specified accumulated in...

short changeAddrMode_io_abs(short Opc) const

int getDotCurOp(const MachineInstr &MI) const

bool expandPostRAPseudo(MachineInstr &MI) const override

This function is called for all pseudo instructions that remain after register allocation.

bool isExpr(unsigned OpType) const

void genAllInsnTimingClasses(MachineFunction &MF) const

bool isTC2Early(const MachineInstr &MI) const

bool hasEHLabel(const MachineBasicBlock *B) const

bool shouldSink(const MachineInstr &MI) const override

bool isZeroExtendingLoad(const MachineInstr &MI) const

short changeAddrMode_rr_io(short Opc) const

bool isHVXVec(const MachineInstr &MI) const

bool isDependent(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const

short changeAddrMode_io_rr(short Opc) const

bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const override

Returns true if the first specified predicate subsumes the second, e.g.

bool mayBeCurLoad(const MachineInstr &MI) const

bool getBundleNoShuf(const MachineInstr &MIB) const

bool isNewValueJump(const MachineInstr &MI) const

bool isTC4x(const MachineInstr &MI) const

bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Cond) const override

Convert the instruction into a predicated instruction.

bool isFloat(const MachineInstr &MI) const

bool isToBeScheduledASAP(const MachineInstr &MI1, const MachineInstr &MI2) const

MachineOperand * getBaseAndOffset(const MachineInstr &MI, int64_t &Offset, LocationSize &AccessSize) const

bool getInvertedPredSense(SmallVectorImpl< MachineOperand > &Cond) const

unsigned nonDbgBBSize(const MachineBasicBlock *BB) const

getInstrTimingClassLatency - Compute the instruction latency of a given instruction using Timing Clas...

uint64_t getType(const MachineInstr &MI) const

bool isEndLoopN(unsigned Opcode) const

bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const override

For instructions with a base and offset, return the position of the base register and offset operands...

bool isPredicable(const MachineInstr &MI) const override

Return true if the specified instruction can be predicated.

bool isExtendable(const MachineInstr &MI) const

short changeAddrMode_abs_io(const MachineInstr &MI) const

Definition HexagonInstrInfo.h:519

void immediateExtend(MachineInstr &MI) const

immediateExtend - Changes the instruction in place to one using an immediate extender.

short changeAddrMode_io_rr(const MachineInstr &MI) const

Definition HexagonInstrInfo.h:525

HexagonII::CompoundGroup getCompoundCandidateGroup(const MachineInstr &MI) const

bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override

Check if the instruction or the bundle of instructions has load from stack slots.

SmallVector< MachineInstr *, 2 > getBranchingInstrs(MachineBasicBlock &MBB) const

bool isPredicatedTrue(const MachineInstr &MI) const

bool isNewValueStore(const MachineInstr &MI) const

int getMinValue(const MachineInstr &MI) const

bool isVecUsableNextPacket(const MachineInstr &ProdMI, const MachineInstr &ConsMI) const

unsigned getCompoundOpcode(const MachineInstr &GA, const MachineInstr &GB) const

bool addLatencyToSchedule(const MachineInstr &MI1, const MachineInstr &MI2) const

If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...

int getDotNewPredJumpOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const

bool isTC2(const MachineInstr &MI) const

Itinerary data supplied by a subtarget to be used by a target.

This class is intended to be used as a base class for asm properties and features specific to the tar...

Instances of this class represent a single low-level machine instruction.

MachineInstrBundleIterator< const MachineInstr > const_iterator

Instructions::iterator instr_iterator

Instructions::const_iterator const_instr_iterator

MachineInstrBundleIterator< MachineInstr > iterator

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

Wrapper class representing virtual and physical registers.

HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...

SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

TargetSubtargetInfo - Generic base class for all target subtargets.

LLVM Value Representation.

This is an optimization pass for GlobalISel generic memory operations.

TargetInstrInfo::RegSubRegPair getRegSubRegPair(const MachineOperand &O)

Create RegSubRegPair from a register MachineOperand.

@ First

Helpers to iterate all locations in the MemoryEffectsBase class.

uint64_t FuncUnits

Bitmask representing a set of functional units.