HexagonMCDuplexInfo.cpp Source File (original) (raw)

35static const std::pair<unsigned, unsigned> opcodeData[] = {

36 std::make_pair((unsigned)SA1_addi, 0),

37 std::make_pair((unsigned)SA1_addrx, 6144),

38 std::make_pair((unsigned)SA1_addsp, 3072),

39 std::make_pair((unsigned)SA1_and1, 4608),

40 std::make_pair((unsigned)SA1_clrf, 6768),

41 std::make_pair((unsigned)SA1_clrfnew, 6736),

42 std::make_pair((unsigned)SA1_clrt, 6752),

43 std::make_pair((unsigned)SA1_clrtnew, 6720),

44 std::make_pair((unsigned)SA1_cmpeqi, 6400),

45 std::make_pair((unsigned)SA1_combine0i, 7168),

46 std::make_pair((unsigned)SA1_combine1i, 7176),

47 std::make_pair((unsigned)SA1_combine2i, 7184),

48 std::make_pair((unsigned)SA1_combine3i, 7192),

49 std::make_pair((unsigned)SA1_combinerz, 7432),

50 std::make_pair((unsigned)SA1_combinezr, 7424),

51 std::make_pair((unsigned)SA1_dec, 4864),

52 std::make_pair((unsigned)SA1_inc, 4352),

53 std::make_pair((unsigned)SA1_seti, 2048),

54 std::make_pair((unsigned)SA1_setin1, 6656),

55 std::make_pair((unsigned)SA1_sxtb, 5376),

56 std::make_pair((unsigned)SA1_sxth, 5120),

57 std::make_pair((unsigned)SA1_tfr, 4096),

58 std::make_pair((unsigned)SA1_zxtb, 5888),

59 std::make_pair((unsigned)SA1_zxth, 5632),

60 std::make_pair((unsigned)SL1_loadri_io, 0),

61 std::make_pair((unsigned)SL1_loadrub_io, 4096),

62 std::make_pair((unsigned)SL2_deallocframe, 7936),

63 std::make_pair((unsigned)SL2_jumpr31, 8128),

64 std::make_pair((unsigned)SL2_jumpr31_f, 8133),

65 std::make_pair((unsigned)SL2_jumpr31_fnew, 8135),

66 std::make_pair((unsigned)SL2_jumpr31_t, 8132),

67 std::make_pair((unsigned)SL2_jumpr31_tnew, 8134),

68 std::make_pair((unsigned)SL2_loadrb_io, 4096),

69 std::make_pair((unsigned)SL2_loadrd_sp, 7680),

70 std::make_pair((unsigned)SL2_loadrh_io, 0),

71 std::make_pair((unsigned)SL2_loadri_sp, 7168),

72 std::make_pair((unsigned)SL2_loadruh_io, 2048),

73 std::make_pair((unsigned)SL2_return, 8000),

74 std::make_pair((unsigned)SL2_return_f, 8005),

75 std::make_pair((unsigned)SL2_return_fnew, 8007),

76 std::make_pair((unsigned)SL2_return_t, 8004),

77 std::make_pair((unsigned)SL2_return_tnew, 8006),

78 std::make_pair((unsigned)SS1_storeb_io, 4096),

79 std::make_pair((unsigned)SS1_storew_io, 0),

80 std::make_pair((unsigned)SS2_allocframe, 7168),

81 std::make_pair((unsigned)SS2_storebi0, 4608),

82 std::make_pair((unsigned)SS2_storebi1, 4864),

83 std::make_pair((unsigned)SS2_stored_sp, 2560),

84 std::make_pair((unsigned)SS2_storeh_io, 0),

85 std::make_pair((unsigned)SS2_storew_sp, 2048),

86 std::make_pair((unsigned)SS2_storewi0, 4096),

87 std::make_pair((unsigned)SS2_storewi1, 4352)};

90 switch (Ga) {

92 default:

93 return false;

110 }

111 return false;

112}

115 switch (Ga) {

117 default:

118 break;

120 switch (Gb) {

121 default:

122 break;

124 return 0;

126 return 0x4;

127 }

128 break;

130 switch (Gb) {

131 default:

132 break;

134 return 0x1;

136 return 0x2;

138 return 0x5;

139 }

140 break;

142 switch (Gb) {

143 default:

144 break;

146 return 0x8;

148 return 0x9;

150 return 0xA;

152 return 0x6;

153 }

154 break;

156 switch (Gb) {

157 default:

158 break;

160 return 0xC;

162 return 0xD;

164 return 0xB;

166 return 0xE;

168 return 0x7;

169 }

170 break;

172 switch (Gb) {

173 default:

174 break;

176 return 0x3;

177 }

178 break;

180 switch (Gb) {

182 return 0xFFFFFFFF;

183 }

184 break;

185 }

186 return 0xFFFFFFFF;

187}

190 MCRegister DstReg, PredReg, SrcReg, Src1Reg, Src2Reg;

191

193 default:

195

196

197

198

199

200 case Hexagon::L2_loadri_io:

203

204

207 Hexagon::R29 == SrcReg && inRange<5, 2>(MCI, 2)) {

209 }

210

214 }

215 }

216 break;

217 case Hexagon::L2_loadrub_io:

218

225 }

226 break;

227

228

229

230

231

232

233

234

235

236

237 case Hexagon::L2_loadrh_io:

238 case Hexagon::L2_loadruh_io:

239

246 }

247 break;

248 case Hexagon::L2_loadrb_io:

249

256 }

257 break;

258 case Hexagon::L2_loadrd_io:

259

266 }

267 break;

268

269 case Hexagon::L4_return:

270 case Hexagon::L2_deallocframe:

272

273 case Hexagon::EH_RETURN_JMPR:

274 case Hexagon::J2_jumpr:

275 case Hexagon::PS_jmpret:

276

277

279 if (Hexagon::R31 == DstReg)

281 break;

282

283 case Hexagon::J2_jumprt:

284 case Hexagon::J2_jumprf:

285 case Hexagon::J2_jumprtnew:

286 case Hexagon::J2_jumprfnew:

287 case Hexagon::PS_jmprett:

288 case Hexagon::PS_jmpretf:

289 case Hexagon::PS_jmprettnew:

290 case Hexagon::PS_jmpretfnew:

291 case Hexagon::PS_jmprettnewpt:

292 case Hexagon::PS_jmpretfnewpt:

295

296 if ((Hexagon::P0 == SrcReg) && (Hexagon::R31 == DstReg)) {

298 }

299 break;

300 case Hexagon::L4_return_t:

301 case Hexagon::L4_return_f:

302 case Hexagon::L4_return_tnew_pnt:

303 case Hexagon::L4_return_fnew_pnt:

304

306 if (Hexagon::P0 == SrcReg) {

308 }

309 break;

310

311

312

313

314

315 case Hexagon::S2_storeri_io:

316

317

322 Hexagon::R29 == Src1Reg && inRange<5, 2>(MCI, 1)) {

324 }

325

330 }

331 break;

332 case Hexagon::S2_storerb_io:

333

340 }

341 break;

342

343

344

345

346

347

348

349

350

351 case Hexagon::S2_storerh_io:

352

359 }

360 break;

361 case Hexagon::S2_storerd_io:

362

369 }

370 break;

371 case Hexagon::S4_storeiri_io:

372

377 }

378 break;

379 case Hexagon::S4_storeirb_io:

380

385 }

386 break;

387 case Hexagon::S2_allocframe:

390 break;

391

392

393

394

395

396

397

398

399

400

401

402

403

404

405

406

407

408

409 case Hexagon::A2_addi:

413

417 }

418

419 if (DstReg == SrcReg) {

421 }

422

423

427 }

428 }

429 break;

430 case Hexagon::A2_add:

431

438 }

439 break;

440 case Hexagon::A2_andir:

447 }

448 break;

449 case Hexagon::A2_tfr:

450

456 }

457 break;

458 case Hexagon::A2_tfrsi:

460

463 }

464 break;

465 case Hexagon::C2_cmoveit:

466 case Hexagon::C2_cmovenewit:

467 case Hexagon::C2_cmoveif:

468 case Hexagon::C2_cmovenewif:

469

470

471

475 Hexagon::P0 == PredReg && minConstant(MCI, 2) == 0) {

477 }

478 break;

479 case Hexagon::C2_cmpeqi:

480

483 if (Hexagon::P0 == DstReg &&

487 }

488 break;

489 case Hexagon::A2_combineii:

490 case Hexagon::A4_combineii:

491

496 }

497 break;

498 case Hexagon::A4_combineri:

499

506 }

507 break;

508 case Hexagon::A4_combineir:

509

516 }

517 break;

518 case Hexagon::A2_sxtb:

519 case Hexagon::A2_sxth:

520 case Hexagon::A2_zxtb:

521 case Hexagon::A2_zxth:

522

528 }

529 break;

530 }

531

533}

537 switch (potentialDuplex.getOpcode()) {

538 case Hexagon::A2_addi:

539

545 return true;

547 return true;

548 }

549 break;

550 case Hexagon::A2_tfrsi:

552

556 return true;

557

559 return false;

560

562 return true;

563 }

564 break;

565 default:

566 break;

567 }

568 return false;

569}

573 MCInst const &MIa, bool ExtendedA,

574 MCInst const &MIb, bool ExtendedB,

575 bool bisReversable,

577

578 if (ExtendedA)

579 return false;

580

581 if (ExtendedB) {

582 unsigned Opcode = MIb.getOpcode();

583 if ((Opcode != Hexagon::A2_addi) && (Opcode != Hexagon::A2_tfrsi))

584 return false;

585 }

588

589 static std::map<unsigned, unsigned> subinstOpcodeMap(std::begin(opcodeData),

591

592

593

597

598 unsigned zeroedSubInstS0 =

599 subinstOpcodeMap.find(SubInst0.getOpcode())->second;

600 unsigned zeroedSubInstS1 =

601 subinstOpcodeMap.find(SubInst1.getOpcode())->second;

602

603 if (zeroedSubInstS0 < zeroedSubInstS1)

604

605

606 return false;

607 }

608

609

610 if (MIb.getOpcode() == Hexagon::S2_allocframe)

611 return false;

612

614

615

616

618 return false;

619

620

621

623 return false;

624 }

625

626

630 return false;

633 return false;

634 }

635

639

640

643 return false;

644 }

645 }

646

648}

658 unsigned opNum) {

661 default:

663 break;

664 case Hexagon::R0:

665 case Hexagon::R1:

666 case Hexagon::R2:

667 case Hexagon::R3:

668 case Hexagon::R4:

669 case Hexagon::R5:

670 case Hexagon::R6:

671 case Hexagon::R7:

672 case Hexagon::D0:

673 case Hexagon::D1:

674 case Hexagon::D2:

675 case Hexagon::D3:

676 case Hexagon::R16:

677 case Hexagon::R17:

678 case Hexagon::R18:

679 case Hexagon::R19:

680 case Hexagon::R20:

681 case Hexagon::R21:

682 case Hexagon::R22:

683 case Hexagon::R23:

684 case Hexagon::D8:

685 case Hexagon::D9:

686 case Hexagon::D10:

687 case Hexagon::D11:

688 case Hexagon::P0:

690 break;

691 }

692 } else

694}

698 Result.setLoc(Inst.getLoc());

699 bool Absolute;

702 default:

703

705 break;

706 case Hexagon::A2_addi:

708 if (Absolute) {

709 if (Value == 1) {

710 Result.setOpcode(Hexagon::SA1_inc);

711 addOps(Result, Inst, 0);

712 addOps(Result, Inst, 1);

713 break;

714 }

715 if (Value == -1) {

716 Result.setOpcode(Hexagon::SA1_dec);

717 addOps(Result, Inst, 0);

718 addOps(Result, Inst, 1);

719 addOps(Result, Inst, 2);

720 break;

721 }

723 Result.setOpcode(Hexagon::SA1_addsp);

724 addOps(Result, Inst, 0);

725 addOps(Result, Inst, 2);

726 break;

727 }

728 }

729 Result.setOpcode(Hexagon::SA1_addi);

730 addOps(Result, Inst, 0);

731 addOps(Result, Inst, 1);

732 addOps(Result, Inst, 2);

733 break;

734 case Hexagon::A2_add:

735 Result.setOpcode(Hexagon::SA1_addrx);

736 addOps(Result, Inst, 0);

737 addOps(Result, Inst, 1);

738 addOps(Result, Inst, 2);

739 break;

740 case Hexagon::S2_allocframe:

741 Result.setOpcode(Hexagon::SS2_allocframe);

742 addOps(Result, Inst, 2);

743 break;

744 case Hexagon::A2_andir:

746 Result.setOpcode(Hexagon::SA1_zxtb);

747 addOps(Result, Inst, 0);

748 addOps(Result, Inst, 1);

749 break;

750 } else {

751 Result.setOpcode(Hexagon::SA1_and1);

752 addOps(Result, Inst, 0);

753 addOps(Result, Inst, 1);

754 break;

755 }

756 case Hexagon::C2_cmpeqi:

757 Result.setOpcode(Hexagon::SA1_cmpeqi);

758 addOps(Result, Inst, 1);

759 addOps(Result, Inst, 2);

760 break;

761 case Hexagon::A4_combineii:

762 case Hexagon::A2_combineii:

764 assert(Absolute);(void)Absolute;

765 if (Value == 1) {

766 Result.setOpcode(Hexagon::SA1_combine1i);

767 addOps(Result, Inst, 0);

768 addOps(Result, Inst, 2);

769 break;

770 }

771 if (Value == 3) {

772 Result.setOpcode(Hexagon::SA1_combine3i);

773 addOps(Result, Inst, 0);

774 addOps(Result, Inst, 2);

775 break;

776 }

777 if (Value == 0) {

778 Result.setOpcode(Hexagon::SA1_combine0i);

779 addOps(Result, Inst, 0);

780 addOps(Result, Inst, 2);

781 break;

782 }

783 if (Value == 2) {

784 Result.setOpcode(Hexagon::SA1_combine2i);

785 addOps(Result, Inst, 0);

786 addOps(Result, Inst, 2);

787 break;

788 }

789 break;

790 case Hexagon::A4_combineir:

791 Result.setOpcode(Hexagon::SA1_combinezr);

792 addOps(Result, Inst, 0);

793 addOps(Result, Inst, 2);

794 break;

795 case Hexagon::A4_combineri:

796 Result.setOpcode(Hexagon::SA1_combinerz);

797 addOps(Result, Inst, 0);

798 addOps(Result, Inst, 1);

799 break;

800 case Hexagon::L4_return_tnew_pnt:

801 case Hexagon::L4_return_tnew_pt:

802 Result.setOpcode(Hexagon::SL2_return_tnew);

803 break;

804 case Hexagon::L4_return_fnew_pnt:

805 case Hexagon::L4_return_fnew_pt:

806 Result.setOpcode(Hexagon::SL2_return_fnew);

807 break;

808 case Hexagon::L4_return_f:

809 Result.setOpcode(Hexagon::SL2_return_f);

810 break;

811 case Hexagon::L4_return_t:

812 Result.setOpcode(Hexagon::SL2_return_t);

813 break;

814 case Hexagon::L4_return:

815 Result.setOpcode(Hexagon::SL2_return);

816 break;

817 case Hexagon::L2_deallocframe:

818 Result.setOpcode(Hexagon::SL2_deallocframe);

819 break;

820 case Hexagon::EH_RETURN_JMPR:

821 case Hexagon::J2_jumpr:

822 case Hexagon::PS_jmpret:

823 Result.setOpcode(Hexagon::SL2_jumpr31);

824 break;

825 case Hexagon::J2_jumprf:

826 case Hexagon::PS_jmpretf:

827 Result.setOpcode(Hexagon::SL2_jumpr31_f);

828 break;

829 case Hexagon::J2_jumprfnew:

830 case Hexagon::PS_jmpretfnewpt:

831 case Hexagon::PS_jmpretfnew:

832 Result.setOpcode(Hexagon::SL2_jumpr31_fnew);

833 break;

834 case Hexagon::J2_jumprt:

835 case Hexagon::PS_jmprett:

836 Result.setOpcode(Hexagon::SL2_jumpr31_t);

837 break;

838 case Hexagon::J2_jumprtnew:

839 case Hexagon::PS_jmprettnewpt:

840 case Hexagon::PS_jmprettnew:

841 Result.setOpcode(Hexagon::SL2_jumpr31_tnew);

842 break;

843 case Hexagon::L2_loadrb_io:

844 Result.setOpcode(Hexagon::SL2_loadrb_io);

845 addOps(Result, Inst, 0);

846 addOps(Result, Inst, 1);

847 addOps(Result, Inst, 2);

848 break;

849 case Hexagon::L2_loadrd_io:

850 Result.setOpcode(Hexagon::SL2_loadrd_sp);

851 addOps(Result, Inst, 0);

852 addOps(Result, Inst, 2);

853 break;

854 case Hexagon::L2_loadrh_io:

855 Result.setOpcode(Hexagon::SL2_loadrh_io);

856 addOps(Result, Inst, 0);

857 addOps(Result, Inst, 1);

858 addOps(Result, Inst, 2);

859 break;

860 case Hexagon::L2_loadrub_io:

861 Result.setOpcode(Hexagon::SL1_loadrub_io);

862 addOps(Result, Inst, 0);

863 addOps(Result, Inst, 1);

864 addOps(Result, Inst, 2);

865 break;

866 case Hexagon::L2_loadruh_io:

867 Result.setOpcode(Hexagon::SL2_loadruh_io);

868 addOps(Result, Inst, 0);

869 addOps(Result, Inst, 1);

870 addOps(Result, Inst, 2);

871 break;

872 case Hexagon::L2_loadri_io:

874 Result.setOpcode(Hexagon::SL2_loadri_sp);

875 addOps(Result, Inst, 0);

876 addOps(Result, Inst, 2);

877 break;

878 } else {

879 Result.setOpcode(Hexagon::SL1_loadri_io);

880 addOps(Result, Inst, 0);

881 addOps(Result, Inst, 1);

882 addOps(Result, Inst, 2);

883 break;

884 }

885 case Hexagon::S4_storeirb_io:

887 assert(Absolute);(void)Absolute;

888 if (Value == 0) {

889 Result.setOpcode(Hexagon::SS2_storebi0);

890 addOps(Result, Inst, 0);

891 addOps(Result, Inst, 1);

892 break;

893 } else if (Value == 1) {

894 Result.setOpcode(Hexagon::SS2_storebi1);

895 addOps(Result, Inst, 0);

896 addOps(Result, Inst, 1);

897 break;

898 }

899 break;

900 case Hexagon::S2_storerb_io:

901 Result.setOpcode(Hexagon::SS1_storeb_io);

902 addOps(Result, Inst, 0);

903 addOps(Result, Inst, 1);

904 addOps(Result, Inst, 2);

905 break;

906 case Hexagon::S2_storerd_io:

907 Result.setOpcode(Hexagon::SS2_stored_sp);

908 addOps(Result, Inst, 1);

909 addOps(Result, Inst, 2);

910 break;

911 case Hexagon::S2_storerh_io:

912 Result.setOpcode(Hexagon::SS2_storeh_io);

913 addOps(Result, Inst, 0);

914 addOps(Result, Inst, 1);

915 addOps(Result, Inst, 2);

916 break;

917 case Hexagon::S4_storeiri_io:

919 assert(Absolute);(void)Absolute;

920 if (Value == 0) {

921 Result.setOpcode(Hexagon::SS2_storewi0);

922 addOps(Result, Inst, 0);

923 addOps(Result, Inst, 1);

924 break;

925 } else if (Value == 1) {

926 Result.setOpcode(Hexagon::SS2_storewi1);

927 addOps(Result, Inst, 0);

928 addOps(Result, Inst, 1);

929 break;

931 Result.setOpcode(Hexagon::SS2_storew_sp);

932 addOps(Result, Inst, 1);

933 addOps(Result, Inst, 2);

934 break;

935 }

936 break;

937 case Hexagon::S2_storeri_io:

939 Result.setOpcode(Hexagon::SS2_storew_sp);

940 addOps(Result, Inst, 1);

941 addOps(Result, Inst, 2);

942 } else {

943 Result.setOpcode(Hexagon::SS1_storew_io);

944 addOps(Result, Inst, 0);

945 addOps(Result, Inst, 1);

946 addOps(Result, Inst, 2);

947 }

948 break;

949 case Hexagon::A2_sxtb:

950 Result.setOpcode(Hexagon::SA1_sxtb);

951 addOps(Result, Inst, 0);

952 addOps(Result, Inst, 1);

953 break;

954 case Hexagon::A2_sxth:

955 Result.setOpcode(Hexagon::SA1_sxth);

956 addOps(Result, Inst, 0);

957 addOps(Result, Inst, 1);

958 break;

959 case Hexagon::A2_tfr:

960 Result.setOpcode(Hexagon::SA1_tfr);

961 addOps(Result, Inst, 0);

962 addOps(Result, Inst, 1);

963 break;

964 case Hexagon::C2_cmovenewif:

965 Result.setOpcode(Hexagon::SA1_clrfnew);

966 addOps(Result, Inst, 0);

967 addOps(Result, Inst, 1);

968 break;

969 case Hexagon::C2_cmovenewit:

970 Result.setOpcode(Hexagon::SA1_clrtnew);

971 addOps(Result, Inst, 0);

972 addOps(Result, Inst, 1);

973 break;

974 case Hexagon::C2_cmoveif:

975 Result.setOpcode(Hexagon::SA1_clrf);

976 addOps(Result, Inst, 0);

977 addOps(Result, Inst, 1);

978 break;

979 case Hexagon::C2_cmoveit:

980 Result.setOpcode(Hexagon::SA1_clrt);

981 addOps(Result, Inst, 0);

982 addOps(Result, Inst, 1);

983 break;

984 case Hexagon::A2_tfrsi:

986 if (Absolute && Value == -1) {

987 Result.setOpcode(Hexagon::SA1_setin1);

988 addOps(Result, Inst, 0);

989 addOps(Result, Inst, 1);

990 break;

991 } else {

992 Result.setOpcode(Hexagon::SA1_seti);

993 addOps(Result, Inst, 0);

994 addOps(Result, Inst, 1);

995 break;

996 }

997 case Hexagon::A2_zxtb:

998 Result.setOpcode(Hexagon::SA1_zxtb);

999 addOps(Result, Inst, 0);

1000 addOps(Result, Inst, 1);

1001 break;

1002

1003 case Hexagon::A2_zxth:

1004 Result.setOpcode(Hexagon::SA1_zxth);

1005 addOps(Result, Inst, 0);

1006 addOps(Result, Inst, 1);

1007 break;

1008 }

1009 return Result;

1010}

1013 switch (opCode) {

1014 case Hexagon::S2_storeri_io:

1015 case Hexagon::S2_storerb_io:

1016 case Hexagon::S2_storerh_io:

1017 case Hexagon::S2_storerd_io:

1018 case Hexagon::S4_storeiri_io:

1019 case Hexagon::S4_storeirb_io:

1020 case Hexagon::S2_allocframe:

1021 return true;

1022 default:

1023 return false;

1024 }

1025}

1030 MCInst const &MCB) {

1033

1035

1036 for (unsigned distance = 1; distance < numInstrInPacket; ++distance) {

1038 k = j + distance;

1039 (j < numInstrInPacket) && (k < numInstrInPacket); ++j, ++k) {

1040

1041

1042 bool bisReversable = true;

1045 LLVM_DEBUG(dbgs() << "skip out of order write pair: " << k << "," << j

1046 << "\n");

1047 bisReversable = false;

1048 }

1050 bisReversable = false;

1051

1052

1058 bisReversable, STI)) {

1059

1063

1064

1066 LLVM_DEBUG(dbgs() << "adding pair: " << j << "," << k << ":"

1069 continue;

1070 } else {

1071 LLVM_DEBUG(dbgs() << "skipping pair: " << j << "," << k << ":"

1074 }

1075

1076

1077 if (bisReversable) {

1083 bisReversable, STI)) {

1084

1088

1089

1092 << "adding pair:" << k << "," << j << ":"

1095 } else {

1097 << "skipping pair: " << k << "," << j << ":"

1100 }

1101 }

1102 }

1103 }

1104 return duplexToTry;

1105}