LLVM: llvm::HexagonMCInstrInfo Namespace Reference (original) (raw)

Functions
void	addConstant (MCInst &MI, uint64_t Value, MCContext &Context)
void	addConstExtender (MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
iterator_range< Hexagon::PacketIterator >	bundleInstructions (MCInstrInfo const &MCII, MCInst const &MCI)
iterator_range< MCInst::const_iterator >	bundleInstructions (MCInst const &MCI)
size_t	bundleSize (MCInst const &MCI)
bool	canonicalizePacket (MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCB, HexagonMCChecker *Checker, bool AttemptCompatibility=false)
bool	IsABranchingInst (MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &I)
MCInst *	deriveDuplex (MCContext &Context, unsigned iClass, MCInst const &inst0, MCInst const &inst1)
MCInst	deriveExtender (MCInstrInfo const &MCII, MCInst const &Inst, MCOperand const &MO)
MCInst	deriveSubInst (MCInst const &Inst)
MCInst const *	extenderForIndex (MCInst const &MCB, size_t Index)
void	extendIfNeeded (MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, MCInst const &MCI)
unsigned	getMemAccessSize (MCInstrInfo const &MCII, MCInst const &MCI)
unsigned	getAddrMode (MCInstrInfo const &MCII, MCInst const &MCI)
MCInstrDesc const &	getDesc (MCInstrInfo const &MCII, MCInst const &MCI)
unsigned	getDuplexCandidateGroup (MCInst const &MI)
SmallVector< DuplexCandidate, 8 >	getDuplexPossibilties (MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCB)
unsigned	getDuplexRegisterNumbering (MCRegister Reg)
MCExpr const &	getExpr (MCExpr const &Expr)
unsigned short	getExtendableOp (MCInstrInfo const &MCII, MCInst const &MCI)
MCOperand const &	getExtendableOperand (MCInstrInfo const &MCII, MCInst const &MCI)
unsigned	getExtentAlignment (MCInstrInfo const &MCII, MCInst const &MCI)
unsigned	getExtentBits (MCInstrInfo const &MCII, MCInst const &MCI)
bool	isExtentSigned (MCInstrInfo const &MCII, MCInst const &MCI)
int	getMaxValue (MCInstrInfo const &MCII, MCInst const &MCI)
	Return the maximum value of an extendable operand.
int	getMinValue (MCInstrInfo const &MCII, MCInst const &MCI)
	Return the minimum value of an extendable operand.
StringRef	getName (MCInstrInfo const &MCII, MCInst const &MCI)
unsigned short	getNewValueOp (MCInstrInfo const &MCII, MCInst const &MCI)
MCOperand const &	getNewValueOperand (MCInstrInfo const &MCII, MCInst const &MCI)
unsigned short	getNewValueOp2 (MCInstrInfo const &MCII, MCInst const &MCI)
	Return the new value or the newly produced value.
MCOperand const &	getNewValueOperand2 (MCInstrInfo const &MCII, MCInst const &MCI)
unsigned	getType (MCInstrInfo const &MCII, MCInst const &MCI)
	Return the Hexagon ISA class for the insn.
unsigned	getCVIResources (MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
	Return the resources used by this instruction.
unsigned	getUnits (MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
	Return the slots used by the insn.
unsigned	getOtherReservedSlots (MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
	Return the slots this instruction consumes in addition to the slot(s) it can execute out of.
bool	hasDuplex (MCInstrInfo const &MCII, MCInst const &MCI)
bool	hasExtenderForIndex (MCInst const &MCB, size_t Index)
bool	hasImmExt (MCInst const &MCI)
bool	hasNewValue (MCInstrInfo const &MCII, MCInst const &MCI)
	Return whether the insn produces a value.
bool	hasNewValue2 (MCInstrInfo const &MCII, MCInst const &MCI)
	Return whether the insn produces a second value.
bool	hasTmpDst (MCInstrInfo const &MCII, MCInst const &MCI)
bool	hasHvxTmp (MCInstrInfo const &MCII, MCInst const &MCI)
unsigned	iClassOfDuplexPair (unsigned Ga, unsigned Gb)
int64_t	minConstant (MCInst const &MCI, size_t Index)
template<unsigned N, unsigned S>
bool	inRange (MCInst const &MCI, size_t Index)
template<unsigned N, unsigned S>
bool	inSRange (MCInst const &MCI, size_t Index)
template<unsigned N>
bool	inRange (MCInst const &MCI, size_t Index)
MCInst const &	instruction (MCInst const &MCB, size_t Index)
bool	isAccumulator (MCInstrInfo const &MCII, MCInst const &MCI)
	Return where the instruction is an accumulator.
bool	isBundle (MCInst const &MCI)
bool	isCanon (MCInstrInfo const &MCII, MCInst const &MCI)
bool	isCofMax1 (MCInstrInfo const &MCII, MCInst const &MCI)
bool	isCofRelax1 (MCInstrInfo const &MCII, MCInst const &MCI)
bool	isCofRelax2 (MCInstrInfo const &MCII, MCInst const &MCI)
bool	isCompound (MCInstrInfo const &MCII, MCInst const &MCI)
bool	isConstExtended (MCInstrInfo const &MCII, MCInst const &MCI)
bool	isCVINew (MCInstrInfo const &MCII, MCInst const &MCI)
bool	isDblRegForSubInst (MCRegister Reg)
bool	isDuplex (MCInstrInfo const &MCII, MCInst const &MCI)
bool	isDuplexPair (MCInst const &MIa, MCInst const &MIb)
	Symmetrical. See if these two instructions are fit for duplex pair.
bool	isDuplexPairMatch (unsigned Ga, unsigned Gb)
bool	isExtendable (MCInstrInfo const &MCII, MCInst const &MCI)
bool	isExtended (MCInstrInfo const &MCII, MCInst const &MCI)
bool	isFloat (MCInstrInfo const &MCII, MCInst const &MCI)
	Return whether it is a floating-point insn.
bool	isHVX (MCInstrInfo const &MCII, MCInst const &MCI)
bool	isImmext (MCInst const &MCI)
bool	isInnerLoop (MCInst const &MCI)
bool	isIntReg (MCRegister Reg)
bool	isIntRegForSubInst (MCRegister Reg)
bool	isMemReorderDisabled (MCInst const &MCI)
bool	isNewValue (MCInstrInfo const &MCII, MCInst const &MCI)
	Return whether the insn expects newly produced value.
bool	isNewValueStore (MCInstrInfo const &MCII, MCInst const &MCI)
	Return true if the operand is a new-value store insn.
bool	isOpExtendable (MCInstrInfo const &MCII, MCInst const &MCI, unsigned short)
	Return whether the operand is extendable.
bool	isOrderedDuplexPair (MCInstrInfo const &MCII, MCInst const &MIa, bool ExtendedA, MCInst const &MIb, bool ExtendedB, bool bisReversable, MCSubtargetInfo const &STI)
	non-Symmetrical. See if these two instructions are fit for duplex pair.
bool	isOuterLoop (MCInst const &MCI)
bool	isPredicated (MCInstrInfo const &MCII, MCInst const &MCI)
bool	isPredicateLate (MCInstrInfo const &MCII, MCInst const &MCI)
bool	isPredicatedNew (MCInstrInfo const &MCII, MCInst const &MCI)
	Return whether the insn is newly predicated.
bool	isPredicatedTrue (MCInstrInfo const &MCII, MCInst const &MCI)
bool	isPredReg (MCRegisterInfo const &MRI, MCRegister Reg)
bool	isPredRegister (MCInstrInfo const &MCII, MCInst const &Inst, unsigned I)
bool	isPrefix (MCInstrInfo const &MCII, MCInst const &MCI)
bool	isSolo (MCInstrInfo const &MCII, MCInst const &MCI)
	Return whether the insn is solo, i.e., cannot be in a packet.
bool	isSoloAX (MCInstrInfo const &MCII, MCInst const &MCI)
	Return whether the insn can be packaged only with A and X-type insns.
bool	isRestrictSlot1AOK (MCInstrInfo const &MCII, MCInst const &MCI)
	Return whether the insn can be packaged only with an A-type insn in slot #1.
bool	isRestrictNoSlot1Store (MCInstrInfo const &MCII, MCInst const &MCI)
bool	isSubInstruction (MCInst const &MCI)
bool	isVector (MCInstrInfo const &MCII, MCInst const &MCI)
bool	mustExtend (MCExpr const &Expr)
bool	mustNotExtend (MCExpr const &Expr)
bool	requiresSlot (MCSubtargetInfo const &STI, MCInst const &MCI)
bool	LoopNeedsPadding (MCInst const &MCB)
unsigned	packetSize (StringRef CPU)
unsigned	packetSizeSlots (MCSubtargetInfo const &STI)
unsigned	slotsConsumed (MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI)
void	padEndloop (MCInst &MCI, MCContext &Context)
PredicateInfo	predicateInfo (MCInstrInfo const &MCII, MCInst const &MCI)
bool	prefersSlot3 (MCInstrInfo const &MCII, MCInst const &MCI)
void	replaceDuplex (MCContext &Context, MCInst &MCI, DuplexCandidate Candidate)
bool	s27_2_reloc (MCExpr const &Expr)
void	setInnerLoop (MCInst &MCI)
void	setMemReorderDisabled (MCInst &MCI)
void	setMustExtend (MCExpr const &Expr, bool Val=true)
void	setMustNotExtend (MCExpr const &Expr, bool Val=true)
void	setS27_2_reloc (MCExpr const &Expr, bool Val=true)
void	setOuterLoop (MCInst &MCI)
bool	subInstWouldBeExtended (MCInst const &potentialDuplex)
unsigned	SubregisterBit (MCRegister Consumer, MCRegister Producer, MCRegister Producer2)
bool	IsVecRegSingle (MCRegister VecReg)
bool	IsVecRegPair (MCRegister VecReg)
bool	IsReverseVecRegPair (MCRegister VecReg)
bool	IsSingleConsumerRefPairProducer (MCRegister Producer, MCRegister Consumer)
std::pair< unsigned, unsigned >	GetVecRegPairIndices (MCRegister VecRegPair)
	Returns an ordered pair of the constituent register ordinals for each of the elements of VecRegPair.
void	tryCompound (MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCI)
	tryCompound - Given a bundle check for compound insns when one is found update the contents of the bundle with the compound insn.

Variables
constexpr size_t	innerLoopOffset = 0
constexpr int64_t	innerLoopMask = 1 << innerLoopOffset
constexpr size_t	outerLoopOffset = 1
constexpr int64_t	outerLoopMask = 1 << outerLoopOffset
constexpr size_t	memReorderDisabledOffset = 2
constexpr int64_t	memReorderDisabledMask = 1 << memReorderDisabledOffset
constexpr size_t	splitNoMemOrderOffset = 3
constexpr int64_t	splitNoMemorderMask = 1 << splitNoMemOrderOffset
constexpr size_t	noShuffleOffset = 4
constexpr int64_t	noShuffleMask = 1 << noShuffleOffset
constexpr size_t	bundleInstructionsOffset = 1

◆ addConstant()

◆ addConstExtender()

◆ bundleInstructions() [1/2]

◆ bundleInstructions() [2/2]

◆ bundleSize()

size_t llvm::HexagonMCInstrInfo::bundleSize	(	MCInst const &	MCI	)

◆ canonicalizePacket()

◆ deriveDuplex()

◆ deriveExtender()

Definition at line 191 of file HexagonMCInstrInfo.cpp.

References llvm::MCInst::addOperand(), assert(), llvm::MCOperand::createExpr(), llvm::MCOperand::createImm(), llvm::MCOperand::getExpr(), llvm::MCOperand::getImm(), llvm::MCOperand::isExpr(), isExtendable(), isExtended(), llvm::MCOperand::isImm(), llvm_unreachable, and llvm::MCInst::setOpcode().

Referenced by addConstExtender().

◆ deriveSubInst()

◆ extenderForIndex()

◆ extendIfNeeded()

◆ getAddrMode()

◆ getCVIResources()

◆ getDesc()

Definition at line 255 of file HexagonMCInstrInfo.cpp.

References llvm::MCInstrInfo::get(), and llvm::MCInst::getOpcode().

Referenced by llvm::HexagonMCCodeEmitter::encodeSingleInstruction(), getAddrMode(), getCVIResources(), getExtendableOp(), getExtentAlignment(), getExtentBits(), llvm::HexagonMCCodeEmitter::getMachineOpValue(), getMemAccessSize(), getNewValueOp(), getNewValueOp2(), getOtherReservedSlots(), llvm::HexagonShuffler::GetPacketSummary(), getUnits(), hasHvxTmp(), hasNewValue(), hasNewValue2(), llvm::HexagonCVIResource::HexagonCVIResource(), IsABranchingInst(), isAccumulator(), isCanon(), isCofMax1(), isCofRelax1(), isCofRelax2(), isConstExtended(), isCVINew(), isExtendable(), isExtended(), isExtentSigned(), isFloat(), isNewValue(), isNewValueStore(), isPredicated(), isPredicatedNew(), isPredicatedTrue(), isPredicateLate(), isPredRegister(), isRestrictNoSlot1Store(), isRestrictSlot1AOK(), isSoloAX(), isVector(), predicateInfo(), prefersSlot3(), llvm::HexagonShuffler::restrictNoSlot1Store(), llvm::HexagonShuffler::restrictStoreLoadOrder(), and llvm::HexagonShuffler::shuffle().

◆ getDuplexCandidateGroup()

Definition at line 189 of file HexagonMCDuplexInfo.cpp.

References llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::MCOperand::getReg(), llvm::HexagonII::HSIG_A, llvm::HexagonII::HSIG_L1, llvm::HexagonII::HSIG_L2, llvm::HexagonII::HSIG_None, llvm::HexagonII::HSIG_S1, llvm::HexagonII::HSIG_S2, inRange(), inSRange(), isDblRegForSubInst(), isIntReg(), isIntRegForSubInst(), and minConstant().

Referenced by getDuplexPossibilties(), isDuplexPair(), and isOrderedDuplexPair().

◆ getDuplexPossibilties()

Definition at line 1028 of file HexagonMCDuplexInfo.cpp.

References assert(), bundleInstructionsOffset, llvm::dbgs(), getDuplexCandidateGroup(), llvm::MCOperand::getInst(), llvm::MCInst::getNumOperands(), llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), hasExtenderForIndex(), iClassOfDuplexPair(), isBundle(), isMemReorderDisabled(), isOrderedDuplexPair(), isStoreInst(), LLVM_DEBUG, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ getDuplexRegisterNumbering()

◆ getExpr()

◆ getExtendableOp()

◆ getExtendableOperand()

◆ getExtentAlignment()

◆ getExtentBits()

◆ getMaxValue()

◆ getMemAccessSize()

◆ getMinValue()

◆ getName()

◆ getNewValueOp()

◆ getNewValueOp2()

◆ getNewValueOperand()

◆ getNewValueOperand2()

◆ getOtherReservedSlots()

◆ getType()

Return the Hexagon ISA class for the insn.

Definition at line 423 of file HexagonMCInstrInfo.cpp.

References F, llvm::MCInstrInfo::get(), llvm::MCInst::getOpcode(), llvm::MCInstrDesc::TSFlags, llvm::HexagonII::TypeMask, and llvm::HexagonII::TypePos.

Referenced by llvm::HexagonShuffler::GetPacketSummary(), isConstExtended(), isDuplex(), isNeitherAnorX(), isPrefix(), lookForCompound(), and llvm::HexagonShuffler::restrictSlot1AOK().

◆ getUnits()

◆ GetVecRegPairIndices()

◆ hasDuplex()

◆ hasExtenderForIndex()

bool llvm::HexagonMCInstrInfo::hasExtenderForIndex	(	MCInst const &	MCB,
size_t	Index )

◆ hasHvxTmp()

◆ hasImmExt()

◆ hasNewValue()

◆ hasNewValue2()

◆ hasTmpDst()

◆ iClassOfDuplexPair()

◆ inRange() [1/2]

bool llvm::HexagonMCInstrInfo::inRange	(	MCInst const &	MCI,
size_t	Index )

◆ inRange() [2/2]

bool llvm::HexagonMCInstrInfo::inRange	(	MCInst const &	MCI,
size_t	Index )

◆ inSRange()

bool llvm::HexagonMCInstrInfo::inSRange	(	MCInst const &	MCI,
size_t	Index )

◆ instruction()

◆ IsABranchingInst()

◆ isAccumulator()

◆ isBundle()

Definition at line 539 of file HexagonMCInstrInfo.cpp.

References assert(), llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::MCOperand::isImm(), and llvm::MCInst::size().

Referenced by addConstExtender(), bundleInstructions(), bundleInstructions(), bundleSize(), llvm::HexagonMCCodeEmitter::encodeInstruction(), llvm::HexagonMCCodeEmitter::encodeSingleInstruction(), getDuplexPossibilties(), hasDuplex(), hasImmExt(), llvm::HexagonMCShuffle(), llvm::HexagonMCShuffle(), llvm::HexagonMCShuffle(), instruction(), IsABranchingInst(), isInnerLoop(), isMemReorderDisabled(), isOuterLoop(), lookForCompound(), padEndloop(), replaceDuplex(), setInnerLoop(), setMemReorderDisabled(), setOuterLoop(), and tryCompound().

◆ isCanon()

◆ isCofMax1()

◆ isCofRelax1()

◆ isCofRelax2()

◆ isCompound()

◆ isConstExtended()

Definition at line 545 of file HexagonMCInstrInfo.cpp.

References assert(), getDesc(), llvm::MCOperand::getExpr(), getExtendableOperand(), getMaxValue(), getMinValue(), llvm::MCInst::getOpcode(), getType(), llvm::isa(), isBranch(), isExtendable(), isExtended(), isExtentSigned(), llvm::MCOperand::isImm(), mustExtend(), mustNotExtend(), llvm::HexagonII::TypeCJ, llvm::HexagonII::TypeCR, llvm::HexagonII::TypeJ, and llvm::HexagonII::TypeNCJ.

Referenced by extendIfNeeded(), llvm::HexagonInstPrinter::printBrtarget(), and llvm::HexagonInstPrinter::printOperand().

◆ isCVINew()

◆ isDblRegForSubInst()

◆ isDuplex()

◆ isDuplexPair()

◆ isDuplexPairMatch()

◆ isExtendable()

◆ isExtended()

◆ isExtentSigned()

◆ isFloat()

◆ isHVX()

◆ isImmext()

◆ isInnerLoop()

◆ isIntReg()

◆ isIntRegForSubInst()

◆ isMemReorderDisabled()

◆ isNewValue()

◆ isNewValueStore()

◆ isOpExtendable()

◆ isOrderedDuplexPair()

non-Symmetrical. See if these two instructions are fit for duplex pair.

Definition at line 572 of file HexagonMCDuplexInfo.cpp.

References deriveSubInst(), llvm::StringRef::equals_insensitive(), llvm::MCSubtargetInfo::getCPU(), getDuplexCandidateGroup(), llvm::MCInst::getNumOperands(), llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::MCOperand::getReg(), llvm::HexagonII::HSIG_L2, llvm::HexagonII::HSIG_None, llvm::HexagonII::HSIG_S1, llvm::HexagonII::HSIG_S2, isDuplexPairMatch(), llvm::MCOperand::isReg(), opcodeData, and subInstWouldBeExtended().

Referenced by getDuplexPossibilties().

◆ isOuterLoop()

◆ isPredicated()

◆ isPredicatedNew()

◆ isPredicatedTrue()

◆ isPredicateLate()

◆ isPredReg()

◆ isPredRegister()

◆ isPrefix()

◆ isRestrictNoSlot1Store()

◆ isRestrictSlot1AOK()

◆ IsReverseVecRegPair()

bool llvm::HexagonMCInstrInfo::IsReverseVecRegPair	(	MCRegister	VecReg	)

◆ IsSingleConsumerRefPairProducer()

◆ isSolo()

◆ isSoloAX()

◆ isSubInstruction()

◆ IsVecRegPair()

◆ IsVecRegSingle()

◆ isVector()

◆ LoopNeedsPadding()

◆ minConstant()

int64_t llvm::HexagonMCInstrInfo::minConstant	(	MCInst const &	MCI,
size_t	Index )

◆ mustExtend()

◆ mustNotExtend()

◆ packetSize()

◆ packetSizeSlots()

◆ padEndloop()

void llvm::HexagonMCInstrInfo::padEndloop	(	MCInst &	MCI,
MCContext &	Context )

◆ predicateInfo()

◆ prefersSlot3()

◆ replaceDuplex()

Definition at line 1001 of file HexagonMCInstrInfo.cpp.

References assert(), llvm::MCInst::begin(), deriveDuplex(), llvm::MCInst::erase(), llvm::MCOperand::getInst(), llvm::MCInst::getOperand(), llvm::DuplexCandidate::iClass, isBundle(), llvm::DuplexCandidate::packetIndexI, llvm::DuplexCandidate::packetIndexJ, llvm::MCOperand::setInst(), and llvm::MCInst::size().

Referenced by llvm::HexagonMCShuffle().

◆ requiresSlot()

◆ s27_2_reloc()

◆ setInnerLoop()

void llvm::HexagonMCInstrInfo::setInnerLoop	(	MCInst &	MCI	)

◆ setMemReorderDisabled()

void llvm::HexagonMCInstrInfo::setMemReorderDisabled	(	MCInst &	MCI	)

◆ setMustExtend()

void llvm::HexagonMCInstrInfo::setMustExtend	(	MCExpr const &	Expr,
bool	Val = true )

◆ setMustNotExtend()

void llvm::HexagonMCInstrInfo::setMustNotExtend	(	MCExpr const &	Expr,
bool	Val = true )

◆ setOuterLoop()

void llvm::HexagonMCInstrInfo::setOuterLoop	(	MCInst &	MCI	)

◆ setS27_2_reloc()

void llvm::HexagonMCInstrInfo::setS27_2_reloc	(	MCExpr const &	Expr,
bool	Val = true )

◆ slotsConsumed()

◆ subInstWouldBeExtended()

bool llvm::HexagonMCInstrInfo::subInstWouldBeExtended	(	MCInst const &	potentialDuplex	)

◆ SubregisterBit()

◆ tryCompound()

◆ bundleInstructionsOffset

size_t llvm::HexagonMCInstrInfo::bundleInstructionsOffset = 1	constexpr

◆ innerLoopMask

int64_t llvm::HexagonMCInstrInfo::innerLoopMask = 1 << innerLoopOffset	constexpr

◆ innerLoopOffset

size_t llvm::HexagonMCInstrInfo::innerLoopOffset = 0	constexpr

◆ memReorderDisabledMask

int64_t llvm::HexagonMCInstrInfo::memReorderDisabledMask = 1 << memReorderDisabledOffset	constexpr

◆ memReorderDisabledOffset

size_t llvm::HexagonMCInstrInfo::memReorderDisabledOffset = 2	constexpr

◆ noShuffleMask

int64_t llvm::HexagonMCInstrInfo::noShuffleMask = 1 << noShuffleOffset	constexpr

◆ noShuffleOffset

size_t llvm::HexagonMCInstrInfo::noShuffleOffset = 4	constexpr

◆ outerLoopMask

int64_t llvm::HexagonMCInstrInfo::outerLoopMask = 1 << outerLoopOffset	constexpr

◆ outerLoopOffset

size_t llvm::HexagonMCInstrInfo::outerLoopOffset = 1	constexpr

◆ splitNoMemorderMask

int64_t llvm::HexagonMCInstrInfo::splitNoMemorderMask = 1 << splitNoMemOrderOffset	constexpr

◆ splitNoMemOrderOffset

size_t llvm::HexagonMCInstrInfo::splitNoMemOrderOffset = 3	constexpr