HexagonMCTargetDesc.cpp Source File (original) (raw)

41#include

42#include

43#include

44#include

45#include

46#include <unordered_map>

48using namespace llvm;

50#define GET_INSTRINFO_MC_DESC

51#define ENABLE_INSTR_PREDICATE_VERIFIER

52#include "HexagonGenInstrInfo.inc"

54#define GET_SUBTARGETINFO_MC_DESC

55#include "HexagonGenSubtargetInfo.inc"

57#define GET_REGINFO_MC_DESC

58#include "HexagonGenRegisterInfo.inc"

61 ("mno-compound",

62 cl::desc("Disable looking for compound instructions for Hexagon"));

65 ("mno-pairing",

66 cl::desc("Disable looking for duplex instructions for Hexagon"));

68namespace {

101}

102

104 "mhvx", cl::desc("Enable Hexagon Vector eXtensions"),

117

119

121

124 cl::desc("Disable Hexagon Vector eXtensions"));

125

128 cl::desc("Enable HVX IEEE floating point extensions"));

131

133

135 if (MV5)

136 return "hexagonv5";

137 if (MV55)

138 return "hexagonv55";

139 if (MV60)

140 return "hexagonv60";

141 if (MV62)

142 return "hexagonv62";

143 if (MV65)

144 return "hexagonv65";

145 if (MV66)

146 return "hexagonv66";

147 if (MV67)

148 return "hexagonv67";

149 if (MV67T)

150 return "hexagonv67t";

151 if (MV68)

152 return "hexagonv68";

153 if (MV69)

154 return "hexagonv69";

155 if (MV71)

156 return "hexagonv71";

157 if (MV71T)

158 return "hexagonv71t";

159 if (MV73)

160 return "hexagonv73";

161 if (MV75)

162 return "hexagonv75";

163 if (MV79)

164 return "hexagonv79";

165 if (MV81)

166 return "hexagonv81";

167

168 return "";

169}

170

173 if (!ArchV.empty() && !CPU.empty()) {

174

175

176 std::pair<StringRef, StringRef> ArchP = ArchV.split('t');

177 std::pair<StringRef, StringRef> CPUP = CPU.split('t');

178 if (ArchP.first != CPUP.first)

180 return CPU;

181 }

182 if (ArchV.empty()) {

183 if (CPU.empty())

185 return CPU;

186 }

187 return ArchV;

188}

189

191

193 enum {

194 CVI_NONE = 0,

195 CVI_XLANE = 1 << 0,

196 CVI_SHIFT = 1 << 1,

197 CVI_MPY0 = 1 << 2,

198 CVI_MPY1 = 1 << 3,

199 CVI_ZW = 1 << 4

200 };

201

202 if (ItinUnits == HexagonItinerariesV62FU::CVI_ALL ||

203 ItinUnits == HexagonItinerariesV62FU::CVI_ALL_NOMEM)

204 return (*Lanes = 4, CVI_XLANE);

205 else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY01 &&

206 ItinUnits & HexagonItinerariesV62FU::CVI_XLSHF)

207 return (*Lanes = 2, CVI_XLANE | CVI_MPY0);

208 else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY01)

209 return (*Lanes = 2, CVI_MPY0);

210 else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLSHF)

211 return (*Lanes = 2, CVI_XLANE);

212 else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLANE &&

213 ItinUnits & HexagonItinerariesV62FU::CVI_SHIFT &&

214 ItinUnits & HexagonItinerariesV62FU::CVI_MPY0 &&

215 ItinUnits & HexagonItinerariesV62FU::CVI_MPY1)

216 return (*Lanes = 1, CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1);

217 else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLANE &&

218 ItinUnits & HexagonItinerariesV62FU::CVI_SHIFT)

219 return (*Lanes = 1, CVI_XLANE | CVI_SHIFT);

220 else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY0 &&

221 ItinUnits & HexagonItinerariesV62FU::CVI_MPY1)

222 return (*Lanes = 1, CVI_MPY0 | CVI_MPY1);

223 else if (ItinUnits == HexagonItinerariesV62FU::CVI_ZW)

224 return (*Lanes = 1, CVI_ZW);

225 else if (ItinUnits == HexagonItinerariesV62FU::CVI_XLANE)

226 return (*Lanes = 1, CVI_XLANE);

227 else if (ItinUnits == HexagonItinerariesV62FU::CVI_SHIFT)

228 return (*Lanes = 1, CVI_SHIFT);

229

230 return (*Lanes = 0, CVI_NONE);

231}

232

233

234namespace llvm {

237 return HexagonItinerariesV62FU::SLOT0 == units;

238}

239}

240}

241

242namespace {

243

245 formatted_raw_ostream &OS;

246

247public:

248 HexagonTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS,

249 MCInstPrinter &IP)

250 : HexagonTargetStreamer(S), OS(OS) {}

251

252 void prettyPrintAsm(MCInstPrinter &InstPrinter, uint64_t Address,

253 const MCInst &Inst, const MCSubtargetInfo &STI,

254 raw_ostream &OS) override {

257 std::string Buffer;

258 {

259 raw_string_ostream TempStream(Buffer);

261 InstPrinter.printInst(I.getInst(), Address, "", STI, TempStream);

262 TempStream << "\n";

263 }

264 }

265

266 std::string LoopString = "";

269 if (IsLoop0) {

270 LoopString += (IsLoop1 ? " :endloop01" : " :endloop0");

271 } else if (IsLoop1) {

272 LoopString += " :endloop1";

273 }

274

275 StringRef Contents(Buffer);

276 auto PacketBundle = Contents.rsplit('\n');

277 auto HeadTail = PacketBundle.first.split('\n');

278 StringRef Separator = "\n";

279 StringRef Indent = "\t";

280 OS << "\t{\n";

281 while (!HeadTail.first.empty()) {

282 StringRef InstTxt;

283 auto Duplex = HeadTail.first.split('\v');

284 if (!Duplex.second.empty()) {

285 OS << Indent << Duplex.first << Separator;

286 InstTxt = Duplex.second;

287 } else if (!HeadTail.first.trim().starts_with("immext")) {

288 InstTxt = Duplex.first;

289 }

290 if (!InstTxt.empty())

291 OS << Indent << InstTxt << Separator;

292 HeadTail = HeadTail.second.split('\n');

293 }

294

296 OS << "\n\t} :mem_noshuf" << LoopString;

297 else

298 OS << "\t}" << LoopString;

299 }

300

301 void finish() override { finishAttributeSection(); }

302

303 void finishAttributeSection() override {}

304

305 void emitAttribute(unsigned Attribute, unsigned Value) override {

306 OS << "\t.attribute\t" << Attribute << ", " << Twine(Value);

307 if (getStreamer().isVerboseAsm()) {

310 if ( Name .empty())

311 OS << "\t// " << Name;

312 }

313 OS << "\n";

314 }

315};

316

318public:

319 MCELFStreamer &getStreamer() {

320 return static_cast<MCELFStreamer &>(Streamer);

321 }

322 HexagonTargetELFStreamer(MCStreamer &S, MCSubtargetInfo const &STI)

323 : HexagonTargetStreamer(S) {

325 }

326

327 void emitCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,

328 unsigned ByteAlignment,

329 unsigned AccessSize) override {

330 HexagonMCELFStreamer &HexagonELFStreamer =

331 static_cast<HexagonMCELFStreamer &>(getStreamer());

333 Symbol, Size, Align(ByteAlignment), AccessSize);

334 }

335

336 void emitLocalCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,

337 unsigned ByteAlignment,

338 unsigned AccessSize) override {

339 HexagonMCELFStreamer &HexagonELFStreamer =

340 static_cast<HexagonMCELFStreamer &>(getStreamer());

342 Symbol, Size, Align(ByteAlignment), AccessSize);

343 }

344

345 void finish() override { finishAttributeSection(); }

346

347 void reset() override { AttributeSection = nullptr; }

348

349private:

350 MCSection *AttributeSection = nullptr;

351

352 void finishAttributeSection() override {

353 MCELFStreamer &S = getStreamer();

355 return;

356

359 }

360

361 void emitAttribute(uint32_t Attribute, uint32_t Value) override {

363 true);

364 }

365};

366

367}

368

371 InitHexagonMCInstrInfo(X);

372 return X;

373}

374

377 InitHexagonMCRegisterInfo(X, Hexagon::R31, 0,

378 0, Hexagon::PC);

379 return X;

380}

381

386

387

389 nullptr, MRI.getDwarfRegNum(Hexagon::R30, true), 0);

391

392 return MAI;

393}

394

396 unsigned SyntaxVariant,

400{

401 if (SyntaxVariant == 0)

403 else

404 return nullptr;

405}

406

410 return new HexagonTargetAsmStreamer(S, OS, *IP);

411}

412

414 std::unique_ptr &&MAB,

415 std::unique_ptr &&OW,

416 std::unique_ptr &&Emitter) {

419}

420

423 return new HexagonTargetELFStreamer(S, STI);

424}

425

429

434

438

439namespace {

442 if (.empty())

443 Result.push_back(FS);

444

448 break;

450 Result.push_back("+hvxv60");

451 break;

453 Result.push_back("+hvxv62");

454 break;

456 Result.push_back("+hvxv65");

457 break;

459 Result.push_back("+hvxv66");

460 break;

462 Result.push_back("+hvxv67");

463 break;

465 Result.push_back("+hvxv68");

466 break;

468 Result.push_back("+hvxv69");

469 break;

471 Result.push_back("+hvxv71");

472 break;

474 Result.push_back("+hvxv73");

475 break;

477 Result.push_back("+hvxv75");

478 break;

480 Result.push_back("+hvxv79");

481 break;

483 Result.push_back("+hvxv81");

484 break;

485

488 .Case("hexagonv60", "+hvxv60")

489 .Case("hexagonv62", "+hvxv62")

490 .Case("hexagonv65", "+hvxv65")

491 .Case("hexagonv66", "+hvxv66")

492 .Case("hexagonv67", "+hvxv67")

493 .Case("hexagonv67t", "+hvxv67")

494 .Case("hexagonv68", "+hvxv68")

495 .Case("hexagonv69", "+hvxv69")

496 .Case("hexagonv71", "+hvxv71")

497 .Case("hexagonv71t", "+hvxv71")

498 .Case("hexagonv73", "+hvxv73")

499 .Case("hexagonv75", "+hvxv75")

500 .Case("hexagonv79", "+hvxv79")

501 .Case("hexagonv81", "+hvxv81"));

502 break;

503 }

505

506 break;

507 }

509 Result.push_back("+hvx-ieee-fp");

511 Result.push_back("+cabac");

512

514}

515}

516

520

521namespace {

522std::pair<std::string, std::string> selectCPUAndFS(StringRef CPU,

524 std::pair<std::string, std::string> Result;

526 Result.second = selectHexagonFS(Result.first, FS);

528}

529std::mutex ArchSubtargetMutex;

530std::unordered_map<std::string, std::unique_ptr>

531 ArchSubtarget;

532}

533

536 std::lock_guardstd::mutex Lock(ArchSubtargetMutex);

537 auto Existing = ArchSubtarget.find(std::string(STI->getCPU()));

538 if (Existing == ArchSubtarget.end())

539 return nullptr;

540 return Existing->second.get();

541}

542

545

546

548 unsigned CpuArch = ArchV5;

549 for (unsigned F :

550 {ArchV81, ArchV79, ArchV75, ArchV73, ArchV71, ArchV69, ArchV68, ArchV67,

551 ArchV66, ArchV65, ArchV62, ArchV60, ArchV55, ArchV5}) {

553 continue;

554 CpuArch = F;

555 break;

556 }

557 bool UseHvx = false;

558 for (unsigned F : {ExtensionHVX, ExtensionHVX64B, ExtensionHVX128B}) {

560 continue;

561 UseHvx = true;

562 break;

563 }

564 bool HasHvxVer = false;

565 for (unsigned F :

566 {ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66,

567 ExtensionHVXV67, ExtensionHVXV68, ExtensionHVXV69, ExtensionHVXV71,

568 ExtensionHVXV73, ExtensionHVXV75, ExtensionHVXV79, ExtensionHVXV81}) {

570 continue;

571 HasHvxVer = true;

572 UseHvx = true;

573 break;

574 }

575

576 if (!UseHvx || HasHvxVer)

577 return FB;

578

579

580 switch (CpuArch) {

581 case ArchV81:

582 FB.set(ExtensionHVXV81);

583 [[fallthrough]];

584 case ArchV79:

585 FB.set(ExtensionHVXV79);

586 [[fallthrough]];

587 case ArchV75:

588 FB.set(ExtensionHVXV75);

589 [[fallthrough]];

590 case ArchV73:

591 FB.set(ExtensionHVXV73);

592 [[fallthrough]];

593 case ArchV71:

594 FB.set(ExtensionHVXV71);

595 [[fallthrough]];

596 case ArchV69:

597 FB.set(ExtensionHVXV69);

598 [[fallthrough]];

599 case ArchV68:

600 FB.set(ExtensionHVXV68);

601 [[fallthrough]];

602 case ArchV67:

603 FB.set(ExtensionHVXV67);

604 [[fallthrough]];

605 case ArchV66:

606 FB.set(ExtensionHVXV66);

607 [[fallthrough]];

608 case ArchV65:

609 FB.set(ExtensionHVXV65);

610 [[fallthrough]];

611 case ArchV62:

612 FB.set(ExtensionHVXV62);

613 [[fallthrough]];

614 case ArchV60:

615 FB.set(ExtensionHVXV60);

616 break;

617 }

618 return FB;

619}

620

624 std::pair<std::string, std::string> Features = selectCPUAndFS(CPU, FS);

625 StringRef CPUName = Features.first;

626 StringRef ArchFS = Features.second;

627

629 TT, CPUName, CPUName, ArchFS);

630 if (X != nullptr && (CPUName == "hexagonv67t" || CPUName == "hexagon71t"))

632

633 if (CPU == "help")

634 exit(0);

635

637 errs() << "error: invalid CPU \"" << CPUName.str().c_str()

638 << "\" specified\n";

639 return nullptr;

640 }

641

642

643

645 !ArchFS.contains("-hvx-qfloat")) {

647 X->setFeatureBits(Features.set(Hexagon::ExtensionHVXQFloat));

648 }

649

652 X->setFeatureBits(Features.reset(Hexagon::FeatureDuplex));

653 }

654

656

657

658

659

660 const bool ZRegOnDefault =

661 (CPUName == "hexagonv67") || (CPUName == "hexagonv66");

662 if (ZRegOnDefault) {

664 X->setFeatureBits(Features.set(Hexagon::ExtensionZReg));

665 }

666

667 return X;

668}

669

671 assert(STI != nullptr);

675 std::lock_guardstd::mutex Lock(ArchSubtargetMutex);

676 ArchSubtarget[std::string(STI->getCPU())] =

677 std::unique_ptr(ArchSTI);

678 }

679}

680

681std::optional

683 for (auto Arch : {Hexagon::ExtensionHVXV81, Hexagon::ExtensionHVXV79,

684 Hexagon::ExtensionHVXV75, Hexagon::ExtensionHVXV73,

685 Hexagon::ExtensionHVXV71, Hexagon::ExtensionHVXV69,

686 Hexagon::ExtensionHVXV68, Hexagon::ExtensionHVXV67,

687 Hexagon::ExtensionHVXV66, Hexagon::ExtensionHVXV65,

688 Hexagon::ExtensionHVXV62, Hexagon::ExtensionHVXV60})

689 if (Features.test(Arch))

690 return Arch;

691 return {};

692}

693

695 for (auto Arch :

696 {Hexagon::ArchV81, Hexagon::ArchV79, Hexagon::ArchV75, Hexagon::ArchV73,

697 Hexagon::ArchV71, Hexagon::ArchV69, Hexagon::ArchV68, Hexagon::ArchV67,

698 Hexagon::ArchV66, Hexagon::ArchV65, Hexagon::ArchV62, Hexagon::ArchV60,

699 Hexagon::ArchV55, Hexagon::ArchV5})

700 if (Features.test(Arch))

701 return Arch;

703 return 0;

704}

705

726

730

731namespace {

733public:

735

737

739 }

740

741 bool isConditionalBranch(MCInst const &Inst) const override {

742

744 }

745

746 bool evaluateBranch(MCInst const &Inst, uint64_t Addr,

747 uint64_t Size, uint64_t &Target) const override {

749 isConditionalBranch(Inst)))

750 return false;

751

752

754 return false;

758 if ( Extended .getExpr()->evaluateAsAbsolute(Value))

759 return false;

761 return true;

762 }

763

764 uint32_t getValueFromMask(uint32_t Instruction, uint32_t Mask) const {

767 while (Mask) {

768 if (Instruction & (Mask & -Mask))

772 }

774 }

775

776 std::vector<std::pair<uint64_t, uint64_t>>

777 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,

778 const MCSubtargetInfo &STI) const override {

779

780 std::vector<std::pair<uint64_t, uint64_t>> Result;

781 for (uint64_t Byte = 0x0, End = PltContents.size(); Byte < End; Byte += 4) {

782

784 if ((ImmExt & 0x00004000) != 0x00004000)

785 continue;

786 uint32_t LoadGotPlt =

788 if ((LoadGotPlt & 0x6a49c00c) != 0x6a49c00c)

789 continue;

790 uint32_t Address = (getValueFromMask(ImmExt, 0xfff3fff) << 6) +

791 getValueFromMask(LoadGotPlt, 0x1f80) + PltSectionVA +

793 Result.emplace_back(PltSectionVA + Byte, Address);

794 }

796 }

797};

798}

799

801 return new HexagonMCInstrAnalysis(Info);

802}

803

804

807

809

810

813

814

817

818

821

822

825

826

829

830

833

834

836

837

840

841

844

845

848

849

852}

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static bool isUnconditionalBranch(Instruction *Term)

static MCStreamer * createMCStreamer(const Triple &T, MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter)

static MCTargetStreamer * createMCAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint)

Analysis containing CSE Info

#define clEnumValN(ENUMVAL, FLAGNAME, DESC)

#define LLVM_EXTERNAL_VISIBILITY

dxil DXContainer Global Emitter

static cl::opt< bool > EnableHexagonCabac("mcabac", cl::desc("tbd"), cl::init(false))

static MCTargetStreamer * createHexagonNullTargetStreamer(MCStreamer &S)

Definition HexagonMCTargetDesc.cpp:426

static MCTargetStreamer * createHexagonObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)

Definition HexagonMCTargetDesc.cpp:422

static MCTargetStreamer * createMCAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *IP)

Definition HexagonMCTargetDesc.cpp:407

LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTargetMC()

Definition HexagonMCTargetDesc.cpp:806

static MCInstrAnalysis * createHexagonMCInstrAnalysis(const MCInstrInfo *Info)

Definition HexagonMCTargetDesc.cpp:800

static MCInstPrinter * createHexagonMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)

Definition HexagonMCTargetDesc.cpp:395

static cl::opt< Hexagon::ArchEnum > EnableHVX("mhvx", cl::desc("Enable Hexagon Vector eXtensions"), cl::values(clEnumValN(Hexagon::ArchEnum::V60, "v60", "Build for HVX v60"), clEnumValN(Hexagon::ArchEnum::V62, "v62", "Build for HVX v62"), clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"), clEnumValN(Hexagon::ArchEnum::V66, "v66", "Build for HVX v66"), clEnumValN(Hexagon::ArchEnum::V67, "v67", "Build for HVX v67"), clEnumValN(Hexagon::ArchEnum::V68, "v68", "Build for HVX v68"), clEnumValN(Hexagon::ArchEnum::V69, "v69", "Build for HVX v69"), clEnumValN(Hexagon::ArchEnum::V71, "v71", "Build for HVX v71"), clEnumValN(Hexagon::ArchEnum::V73, "v73", "Build for HVX v73"), clEnumValN(Hexagon::ArchEnum::V75, "v75", "Build for HVX v75"), clEnumValN(Hexagon::ArchEnum::V79, "v79", "Build for HVX v79"), clEnumValN(Hexagon::ArchEnum::V81, "v81", "Build for HVX v81"), clEnumValN(Hexagon::ArchEnum::Generic, "", "")), cl::init(Hexagon::ArchEnum::NoArch), cl::ValueOptional)

static cl::opt< bool > DisableHVX("mno-hvx", cl::Hidden, cl::desc("Disable Hexagon Vector eXtensions"))

static MCStreamer * createMCStreamer(Triple const &T, MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter)

Definition HexagonMCTargetDesc.cpp:413

static bool isCPUValid(StringRef CPU)

Definition HexagonMCTargetDesc.cpp:517

static MCRegisterInfo * createHexagonMCRegisterInfo(const Triple &TT)

Definition HexagonMCTargetDesc.cpp:375

static cl::opt< bool > EnableHvxIeeeFp("mhvx-ieee-fp", cl::Hidden, cl::desc("Enable HVX IEEE floating point extensions"))

static MCAsmInfo * createHexagonMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT, const MCTargetOptions &Options)

Definition HexagonMCTargetDesc.cpp:382

static StringRef HexagonGetArchVariant()

Definition HexagonMCTargetDesc.cpp:134

static void clearFeature(MCSubtargetInfo *STI, uint64_t F)

Definition HexagonMCTargetDesc.cpp:430

static bool checkFeature(MCSubtargetInfo *STI, uint64_t F)

Definition HexagonMCTargetDesc.cpp:435

static constexpr StringRef DefaultArch

Definition HexagonMCTargetDesc.cpp:132

#define HEXAGON_PACKET_SIZE

static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

size_t size() const

size - Get the array size.

Container class for subtarget features.

constexpr FeatureBitset & reset(unsigned I)

constexpr bool test(unsigned I) const

Prints bundles as a newline separated list of individual instructions Duplexes are separated by a ver...

void HexagonMCEmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size, Align ByteAlignment, unsigned AccessSize)

void HexagonMCEmitCommonSymbol(MCSymbol *Symbol, uint64_t Size, Align ByteAlignment, unsigned AccessSize)

This class is intended to be used as a base class for asm properties and features specific to the tar...

void addInitialFrameState(const MCCFIInstruction &Inst)

static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int64_t Offset, SMLoc Loc={})

.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.

Context object for machine code objects.

SmallVector< AttributeItem, 64 > Contents

void emitAttributesSection(StringRef Vendor, const Twine &Section, unsigned Type, MCSection *&AttributeSection)

This is an instance of a target assembly language printer that converts an MCInst to valid target ass...

virtual void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &OS)=0

Print the specified MCInst to the specified raw_ostream.

Instances of this class represent a single low-level machine instruction.

virtual bool isUnconditionalBranch(const MCInst &Inst) const

virtual bool isConditionalBranch(const MCInst &Inst) const

Interface to description of machine instruction set.

MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...

Streaming machine code generation interface.

Generic base class for all target subtargets.

bool hasFeature(unsigned Feature) const

const Triple & getTargetTriple() const

FeatureBitset ToggleFeature(uint64_t FB)

Toggle a feature and return the re-computed feature bits.

Target specific streamer interface.

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StringRef - Represent a constant reference to a string, i.e.

std::pair< StringRef, StringRef > split(char Separator) const

Split into two substrings around the first occurrence of a separator character.

std::string str() const

str - Get the contents as an std::string.

constexpr bool empty() const

empty - Check if the string is empty.

bool contains(StringRef Other) const

Return true if the given string is a substring of *this, and false otherwise.

StringRef drop_back(size_t N=1) const

Return a StringRef equal to 'this' but with the last N elements dropped.

A switch()-like statement whose cases are string literals.

StringSwitch & Case(StringLiteral S, T Value)

Triple - Helper class for working with autoconf configuration names.

formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

constexpr char Align[]

Key for Kernel::Arg::Metadata::mAlign.

constexpr std::underlying_type_t< E > Mask()

Get a bitmask with 1s in all places up to the high-order bit of E's largest value.

LLVM_ABI StringRef attrTypeAsString(unsigned attr, TagNameMap tagNameMap, bool hasTagPrefix=true)

LLVM_ABI const TagNameMap & getHexagonAttributeTags()

bool isSlot0Only(unsigned units)

Definition HexagonMCTargetDesc.cpp:236

bool isOuterLoop(MCInst const &MCI)

size_t bundleSize(MCInst const &MCI)

bool isMemReorderDisabled(MCInst const &MCI)

iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)

bool isBundle(MCInst const &MCI)

bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)

bool isInnerLoop(MCInst const &MCI)

MCOperand const & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)

llvm::ArrayRef< MCPhysReg > GetVectRegRev()

Definition HexagonMCTargetDesc.cpp:727

unsigned getArchVersion(const FeatureBitset &Features)

Definition HexagonMCTargetDesc.cpp:694

unsigned GetELFFlags(const MCSubtargetInfo &STI)

Definition HexagonMCTargetDesc.cpp:706

std::optional< unsigned > getHVXVersion(const FeatureBitset &Features)

Definition HexagonMCTargetDesc.cpp:682

MCSubtargetInfo const * getArchSubtarget(MCSubtargetInfo const *STI)

Definition HexagonMCTargetDesc.cpp:535

StringRef selectHexagonCPU(StringRef CPU)

Definition HexagonMCTargetDesc.cpp:171

void addArchSubtarget(MCSubtargetInfo const *STI, StringRef FS)

Definition HexagonMCTargetDesc.cpp:670

FeatureBitset completeHVXFeatures(const FeatureBitset &FB)

Definition HexagonMCTargetDesc.cpp:543

MCSubtargetInfo * createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)

Create a Hexagon MCSubtargetInfo instance.

Definition HexagonMCTargetDesc.cpp:621

std::optional< Hexagon::ArchEnum > getCpu(StringRef CPU)

ValuesClass values(OptsTy... Options)

Helper to build a ValuesClass by forwarding a variable number of arguments as an initializer list to ...

initializer< Ty > init(const Ty &Val)

uint32_t read32le(const void *P)

This is an optimization pass for GlobalISel generic memory operations.

FunctionAddr VTableAddr Value

unsigned HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes)

Definition HexagonMCTargetDesc.cpp:192

cl::opt< bool > HexagonDisableCompound

MCCodeEmitter * createHexagonMCCodeEmitter(const MCInstrInfo &MCII, MCContext &MCT)

unsigned HexagonGetLastSlot()

Definition HexagonMCTargetDesc.cpp:190

Target & getTheHexagonTarget()

MCAsmBackend * createHexagonAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)

LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)

LLVM_ABI raw_fd_ostream & errs()

This returns a reference to a raw_ostream for standard error.

std::string join(IteratorT Begin, IteratorT End, StringRef Separator)

Joins the strings in the range [Begin, End), adding Separator between the elements.

MCInstrInfo * createHexagonMCInstrInfo()

Definition HexagonMCTargetDesc.cpp:369

ArrayRef(const T &OneElt) -> ArrayRef< T >

MCStreamer * createHexagonELFStreamer(Triple const &TT, MCContext &Context, std::unique_ptr< MCAsmBackend > MAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > CE)

cl::opt< bool > HexagonDisableDuplex

RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.

static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)

RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.

static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)

RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.

static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)

RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.

static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)

RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.

static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)

static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)

RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.

static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)

static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)

static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)

RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.

static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)

RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.

static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)