LLVM: lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h Source File (original) (raw)

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13#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H

14#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H

15

18#include

19

20#define Hexagon_POINTER_SIZE 4

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22#define Hexagon_PointerSize (Hexagon_POINTER_SIZE)

23#define Hexagon_PointerSize_Bits (Hexagon_POINTER_SIZE * 8)

24#define Hexagon_WordSize Hexagon_PointerSize

25#define Hexagon_WordSize_Bits Hexagon_PointerSize_Bits

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27

28

29#define HEXAGON_LRFP_SIZE 8

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31

32#define HEXAGON_INSTR_SIZE 4

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34

35#define HEXAGON_PACKET_SIZE 4

36#define HEXAGON_MAX_PACKET_SIZE (HEXAGON_PACKET_SIZE * HEXAGON_INSTR_SIZE)

37

38#define HEXAGON_PACKET_INNER_SIZE 2

39#define HEXAGON_PACKET_OUTER_SIZE 3

40

41

42#define HEXAGON_PRESHUFFLE_PACKET_SIZE (HEXAGON_PACKET_SIZE + 3)

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44

45#define HEXAGON_GOT_SYM_NAME "_GLOBAL_OFFSET_TABLE_"

46

47namespace llvm {

48

49struct InstrStage;

50class FeatureBitset;

51class MCAsmBackend;

52class MCCodeEmitter;

53class MCContext;

54class MCInstrInfo;

55class MCObjectTargetWriter;

56class MCRegisterInfo;

57class MCSubtargetInfo;

58class MCTargetOptions;

59class Target;

60class Triple;

61class StringRef;

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69

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98std::unique_ptr

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103

104}

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109#define GET_REGINFO_ENUM

110#include "HexagonGenRegisterInfo.inc"

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114#define GET_INSTRINFO_ENUM

115#define GET_INSTRINFO_SCHED_ENUM

116#define GET_INSTRINFO_MC_HELPER_DECLS

117#include "HexagonGenInstrInfo.inc"

118

119#define GET_SUBTARGETINFO_ENUM

120#include "HexagonGenSubtargetInfo.inc"

121

122#endif

unsigned const MachineRegisterInfo * MRI

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Container class for subtarget features.

Generic interface to target specific assembler backends.

MCCodeEmitter - Generic instruction encoding interface.

Context object for machine code objects.

Interface to description of machine instruction set.

MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...

Generic base class for all target subtargets.

StringRef - Represent a constant reference to a string, i.e.

Target - Wrapper for Target specific information.

Triple - Helper class for working with autoconf configuration names.

llvm::ArrayRef< MCPhysReg > GetVectRegRev()

unsigned getArchVersion(const FeatureBitset &Features)

unsigned GetELFFlags(const MCSubtargetInfo &STI)

std::optional< unsigned > getHVXVersion(const FeatureBitset &Features)

MCSubtargetInfo const * getArchSubtarget(MCSubtargetInfo const *STI)

StringRef selectHexagonCPU(StringRef CPU)

void addArchSubtarget(MCSubtargetInfo const *STI, StringRef FS)

FeatureBitset completeHVXFeatures(const FeatureBitset &FB)

MCSubtargetInfo * createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)

Create a Hexagon MCSubtargetInfo instance.

template class LLVM_TEMPLATE_ABI opt< bool >

This is an optimization pass for GlobalISel generic memory operations.

unsigned HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes)

cl::opt< bool > HexagonDisableCompound

MCCodeEmitter * createHexagonMCCodeEmitter(const MCInstrInfo &MCII, MCContext &MCT)

MCRegisterInfo * createHexagonMCRegisterInfo(StringRef TT)

unsigned HexagonGetLastSlot()

std::unique_ptr< MCObjectTargetWriter > createHexagonELFObjectWriter(uint8_t OSABI, StringRef CPU)

MCAsmBackend * createHexagonAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)

MCInstrInfo * createHexagonMCInstrInfo()

const InstrStage HexagonStages[]

cl::opt< bool > HexagonDisableDuplex