HexagonSubtarget.h Source File (original) (raw)

13#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H

14#define LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H

28#include

29#include

30#include

32#define GET_SUBTARGETINFO_HEADER

33#include "HexagonGenSubtargetInfo.inc"

35namespace llvm {

37class MachineInstr;

38class SDep;

39class SUnit;

40class TargetMachine;

41class Triple;

44 virtual void anchor();

46 bool UseHVX64BOps = false;

47 bool UseHVX128BOps = false;

49 bool UseAudioOps = false;

50 bool UseCompound = false;

51 bool UseLongCalls = false;

52 bool UseMemops = false;

53 bool UsePackets = false;

54 bool UseNewValueJumps = false;

55 bool UseNewValueStores = false;

56 bool UseSmallData = false;

57 bool UseZRegOps = false;

58 bool UseHVXIEEEFPOps = false;

59 bool UseHVXQFloatOps = false;

60 bool UseHVXFloatingPoint = false;

61 bool UseCabac = false;

63 bool HasPreV65 = false;

64 bool HasMemNoShuf = false;

65 bool EnableDuplex = false;

66 bool ReservedR19 = false;

67 bool NoreturnStackElim = false;

69public:

85 private:

87 const SUnit &Inst1, const SUnit &Inst2) const;

88 };

93private:

94 enum HexagonProcFamilyEnum { Others, TinyCore };

96 std::string CPUString;

97 HexagonProcFamilyEnum HexagonProcFamily = Others;

100

101

107

108public:

111

114 return TargetTriple.getEnvironment() == Triple::Musl;

115 }

116

117

118

120 return &InstrItins;

121 }

124 return &InstrInfo.getRegisterInfo();

125 }

127 return &TLInfo;

128 }

130 return &FrameLowering;

131 }

133 return &TSInfo;

134 }

135

138

139

140

142

144

235

245 bool useCabac() const { return UseCabac; }

246

247 bool isTinyCore() const { return HexagonProcFamily == TinyCore; }

249

287

291

293

296

297

298

299

301

302

303

305

306

308

310

311 const std::string &getCPUString () const { return CPUString; }

312

316

318 std::vector<std::unique_ptr> &Mutations)

319 const override;

320

322 std::vector<std::unique_ptr> &Mutations)

323 const override;

324

325

326

327 bool useAA() const override;

328

329

330

334

338 return 64;

340 return 128;

342 }

343

345 static MVT Types[] = {MVT::i8, MVT::i16, MVT::i32};

346 static MVT TypesV68[] = {MVT::i8, MVT::i16, MVT::i32, MVT::f16, MVT::f32};

347 static MVT TypesV81[] = {MVT::i8, MVT::i16, MVT::i32,

348 MVT::f16, MVT::bf16, MVT::f32};

349

355 }

356

359 bool isTypeForHVX(Type *VecTy, bool IncludeBool = false) const;

360

364 return Align(std::max(1, Ty.getSizeInBits() / 8));

365 }

366

369

371

372private:

373

375 bool IsArtificial, int Latency) const;

376 void restoreLatency(SUnit *Src, SUnit *Dst) const;

377 void changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat) const;

381};

382

383}

384

385#endif

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

This file defines the SmallSet class.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Definition HexagonSubtarget.h:43

bool isTinyCoreWithDuplex() const

Definition HexagonSubtarget.h:248

const InstrItineraryData * getInstrItineraryData() const override

getInstrItins - Return the instruction itineraries based on subtarget selection.

Definition HexagonSubtarget.h:119

Hexagon::ArchEnum HexagonArchVersion

Definition HexagonSubtarget.h:70

void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep, const TargetSchedModel *SchedModel) const override

Perform target specific adjustments to the latency of a schedule dependency.

bool useHVXV67Ops() const

Definition HexagonSubtarget.h:270

bool usePackets() const

Definition HexagonSubtarget.h:240

bool hasV68OpsOnly() const

Definition HexagonSubtarget.h:190

bool usePredicatedCalls() const

bool hasReservedR19() const

Definition HexagonSubtarget.h:289

bool useLongCalls() const

Definition HexagonSubtarget.h:238

bool useAudioOps() const

Definition HexagonSubtarget.h:236

bool enableMachineSchedDefaultSched() const override

Definition HexagonSubtarget.h:300

const HexagonInstrInfo * getInstrInfo() const override

Definition HexagonSubtarget.h:122

bool hasV79OpsOnly() const

Definition HexagonSubtarget.h:220

const HexagonFrameLowering * getFrameLowering() const override

Definition HexagonSubtarget.h:129

Hexagon::ArchEnum HexagonHVXVersion

Definition HexagonSubtarget.h:71

bool useCabac() const

Definition HexagonSubtarget.h:245

bool useSmallData() const

Definition HexagonSubtarget.h:243

const HexagonRegisterInfo * getRegisterInfo() const override

Definition HexagonSubtarget.h:123

bool hasV55OpsOnly() const

Definition HexagonSubtarget.h:154

const Hexagon::ArchEnum & getHexagonArchVersion() const

Definition HexagonSubtarget.h:313

void getSMSMutations(std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const override

HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM)

bool noreturnStackElim() const

Definition HexagonSubtarget.h:292

bool isHVXVectorType(EVT VecTy, bool IncludeBool=false) const

bool hasV68Ops() const

Definition HexagonSubtarget.h:187

bool hasV79Ops() const

Definition HexagonSubtarget.h:217

const Triple & getTargetTriple() const

Definition HexagonSubtarget.h:112

bool hasV66Ops() const

Definition HexagonSubtarget.h:175

void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation > > &Mutations) const override

bool useHVXV62Ops() const

Definition HexagonSubtarget.h:261

const HexagonTargetLowering * getTargetLowering() const override

Definition HexagonSubtarget.h:126

bool hasV75OpsOnly() const

Definition HexagonSubtarget.h:214

bool hasV65OpsOnly() const

Definition HexagonSubtarget.h:172

bool useNewValueStores() const

Definition HexagonSubtarget.h:242

bool hasV67Ops() const

Definition HexagonSubtarget.h:181

bool UseBSBScheduling

True if the target should use Back-Skip-Back scheduling.

Definition HexagonSubtarget.h:75

bool isTinyCore() const

Definition HexagonSubtarget.h:247

unsigned getL1PrefetchDistance() const

ArrayRef< MVT > getHVXElementTypes() const

Definition HexagonSubtarget.h:344

bool useHVXFloatingPoint() const

Definition HexagonSubtarget.h:254

bool hasV62OpsOnly() const

Definition HexagonSubtarget.h:166

bool useHVXV79Ops() const

Definition HexagonSubtarget.h:223

bool hasV55Ops() const

Definition HexagonSubtarget.h:151

bool useHVXV69Ops() const

Definition HexagonSubtarget.h:276

bool hasMemNoShuf() const

Definition HexagonSubtarget.h:288

bool enableSubRegLiveness() const override

bool hasV73OpsOnly() const

Definition HexagonSubtarget.h:208

bool hasV69Ops() const

Definition HexagonSubtarget.h:193

bool hasV73Ops() const

Definition HexagonSubtarget.h:205

Align getTypeAlignment(MVT Ty) const

Definition HexagonSubtarget.h:361

bool useHVXV71Ops() const

Definition HexagonSubtarget.h:279

bool hasV81Ops() const

Definition HexagonSubtarget.h:226

bool hasV71OpsOnly() const

Definition HexagonSubtarget.h:202

bool useHVXV81Ops() const

Definition HexagonSubtarget.h:232

bool useZRegOps() const

Definition HexagonSubtarget.h:244

bool useNewValueJumps() const

Definition HexagonSubtarget.h:241

bool useHVXOps() const

Definition HexagonSubtarget.h:255

bool useHVXQFloatOps() const

Definition HexagonSubtarget.h:251

CodeGenOptLevel OptLevel

Definition HexagonSubtarget.h:72

unsigned getVectorLength() const

Definition HexagonSubtarget.h:335

AntiDepBreakMode getAntiDepBreakMode() const override

Definition HexagonSubtarget.h:304

bool hasV66OpsOnly() const

Definition HexagonSubtarget.h:178

bool useHVX128BOps() const

Definition HexagonSubtarget.h:285

bool hasV67OpsOnly() const

Definition HexagonSubtarget.h:184

void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)

ParseSubtargetFeatures - Parses features string setting specified subtarget options.

bool hasV69OpsOnly() const

Definition HexagonSubtarget.h:196

bool hasV60Ops() const

Definition HexagonSubtarget.h:157

bool useHVXV68Ops() const

Definition HexagonSubtarget.h:273

bool useHVXV66Ops() const

Definition HexagonSubtarget.h:267

bool hasV5Ops() const

Definition HexagonSubtarget.h:145

bool useHVXIEEEFPOps() const

Definition HexagonSubtarget.h:250

unsigned getL1CacheLineSize() const

bool useHVXV73Ops() const

Definition HexagonSubtarget.h:282

bool isTypeForHVX(Type *VecTy, bool IncludeBool=false) const

Intrinsic::ID getIntrinsicId(unsigned Opc) const

HexagonSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS)

const HexagonSelectionDAGInfo * getSelectionDAGInfo() const override

Definition HexagonSubtarget.h:132

bool enableMachineScheduler() const override

bool useHVXV65Ops() const

Definition HexagonSubtarget.h:264

bool hasV75Ops() const

Definition HexagonSubtarget.h:211

bool hasV71Ops() const

Definition HexagonSubtarget.h:199

bool hasV81OpsOnly() const

Definition HexagonSubtarget.h:229

bool hasV65Ops() const

Definition HexagonSubtarget.h:169

bool hasV62Ops() const

Definition HexagonSubtarget.h:163

bool enablePostRAScheduler() const override

True if the subtarget should run a scheduler after register allocation.

Definition HexagonSubtarget.h:307

bool useHVX64BOps() const

Definition HexagonSubtarget.h:286

bool isEnvironmentMusl() const

Definition HexagonSubtarget.h:113

bool useHVXV60Ops() const

Definition HexagonSubtarget.h:258

bool useBSBScheduling() const

Definition HexagonSubtarget.h:294

bool useCompound() const

Definition HexagonSubtarget.h:237

bool isHVXElementType(MVT Ty, bool IncludeBool=false) const

bool hasV60OpsOnly() const

Definition HexagonSubtarget.h:160

const std::string & getCPUString() const

Definition HexagonSubtarget.h:311

bool useMemops() const

Definition HexagonSubtarget.h:239

bool isXRaySupported() const override

Definition HexagonSubtarget.h:143

bool useAA() const override

Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...

bool hasV5OpsOnly() const

Definition HexagonSubtarget.h:148

Itinerary data supplied by a subtarget to be used by a target.

Representation of each machine instruction.

Scheduling unit. This is a node in the scheduling DAG.

A ScheduleDAG for scheduling lists of MachineInstr.

Mutate the DAG as a postpass after normal DAG building.

SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.

StringRef - Represent a constant reference to a string, i.e.

Primary interface to the complete machine description for the target machine.

Provide an instruction scheduling machine model to CodeGen passes.

Triple - Helper class for working with autoconf configuration names.

The instances of the Type class are immutable: once they are created, they are never changed.

A Use represents the edge between a Value definition and its users.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

This is an optimization pass for GlobalISel generic memory operations.

CodeGenOptLevel

Code generation optimization level.

ArrayRef(const T &OneElt) -> ArrayRef< T >

This struct is a compact representation of a valid (non-zero power of two) alignment.

Definition HexagonSubtarget.h:89

void apply(ScheduleDAGInstrs *DAG) override

Definition HexagonSubtarget.h:83

void apply(ScheduleDAGInstrs *DAG) override

Definition HexagonSubtarget.h:80

void apply(ScheduleDAGInstrs *DAG) override

Definition HexagonSubtarget.h:77

void apply(ScheduleDAGInstrs *DAG) override