LLVM: lib/MCA/Stages/InOrderIssueStage.cpp File Reference (original) (raw)
InOrderIssueStage implements an in-order execution pipeline. More...
#include "[llvm/MCA/Stages/InOrderIssueStage.h](InOrderIssueStage%5F8h%5Fsource.html)"#include "[llvm/MCA/HardwareUnits/LSUnit.h](LSUnit%5F8h%5Fsource.html)"#include "[llvm/MCA/HardwareUnits/RegisterFile.h](RegisterFile%5F8h%5Fsource.html)"#include "[llvm/MCA/HardwareUnits/RetireControlUnit.h](RetireControlUnit%5F8h%5Fsource.html)"#include "[llvm/MCA/Instruction.h](MCA%5F2Instruction%5F8h%5Fsource.html)"
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| Namespaces | |
|---|---|
| namespace | llvm |
| This is an optimization pass for GlobalISel generic memory operations. | |
| namespace | llvm::mca |
| Macros | |
|---|---|
| #define | DEBUG_TYPE "llvm-mca" |
| Functions | |
|---|---|
| static bool | llvm::mca::hasResourceHazard (const ResourceManager &RM, const InstRef &IR) |
| static unsigned | llvm::mca::findFirstWriteBackCycle (const InstRef &IR) |
| static unsigned | llvm::mca::checkRegisterHazard (const RegisterFile &PRF, const MCSubtargetInfo &STI, const InstRef &IR) |
| Return a number of cycles left until register requirements of the instructions are met. | |
| static void | llvm::mca::addRegisterReadWrite (RegisterFile &PRF, Instruction &IS, unsigned SourceIndex, const MCSubtargetInfo &STI, SmallVectorImpl< unsigned > &UsedRegs) |
Detailed Description
InOrderIssueStage implements an in-order execution pipeline.
Definition in file InOrderIssueStage.cpp.
Macro Definition Documentation
◆ DEBUG_TYPE
#define DEBUG_TYPE "llvm-mca"
Definition at line 20 of file InOrderIssueStage.cpp.