InitUndef.cpp Source File (original) (raw)

55using namespace llvm;

57#define DEBUG_TYPE "init-undef"

58#define INIT_UNDEF_NAME "Init Undef Pass"

60namespace {

72public:

73 static char ID;

81 }

85private:

92};

94}

96char InitUndef::ID = 0;

102 return DefMO.isReg() && DefMO.isEarlyClobber();

103 });

104}

105

107 for (auto &DefMI : MRI->def_instructions(Reg)) {

108 if (DefMI.getOpcode() == TargetOpcode::IMPLICIT_DEF)

109 return true;

110 }

111 return false;

112}

113

115 bool Changed = false;

116 for (auto &UseMO : MI->uses()) {

117 if (!UseMO.isReg())

118 continue;

119 if (UseMO.isTied())

120 continue;

121 if (!UseMO.getReg().isVirtual())

122 continue;

123

125 Changed |= fixupIllOperand(MI, UseMO);

126 }

127 return Changed;

128}

129

132 bool Changed = false;

133

135 if (!UseMO.isReg())

136 continue;

137 if (!UseMO.getReg().isVirtual())

138 continue;

139 if (UseMO.isTied())

140 continue;

141

143 if (NewRegs.count(Reg))

144 continue;

147

148 if (Info.UsedLanes == Info.DefinedLanes)

149 continue;

150

152

153 LaneBitmask NeedDef = Info.UsedLanes & ~Info.DefinedLanes;

154

156 dbgs() << "Instruction has undef subregister.\n";

160 << " Need Def: " << PrintLaneMask(NeedDef) << "\n";

161 });

162

164 TRI->getCoveringSubRegIndexes(TargetRegClass, NeedDef,

165 SubRegIndexNeedInsert);

166

167

168

169

170 if (any_of(SubRegIndexNeedInsert, [&](unsigned Ind) -> bool {

171 return TRI ->getSubRegisterClass(TargetRegClass, Ind);

172 }))

173 continue;

174

176 for (auto ind : SubRegIndexNeedInsert) {

177 Changed = true;

179 TRI->getSubRegisterClass(TargetRegClass, ind);

180 Register TmpInitSubReg = MRI->createVirtualRegister(SubRegClass);

181 LLVM_DEBUG(dbgs() << "Register Class ID" << SubRegClass->getID() << "\n");

183 TII->get(TargetOpcode::INIT_UNDEF), TmpInitSubReg);

184 Register NewReg = MRI->createVirtualRegister(TargetRegClass);

186 TII->get(TargetOpcode::INSERT_SUBREG), NewReg)

188 .addReg(TmpInitSubReg)

190 LatestReg = NewReg;

191 }

192

193 UseMO.setReg(LatestReg);

194 }

195

196 return Changed;

197}

198

200

202 dbgs() << "Emitting PseudoInitUndef Instruction for implicit register "

204

206 LLVM_DEBUG(dbgs() << "Register Class ID" << TargetRegClass->getID() << "\n");

207 Register NewReg = MRI->createVirtualRegister(TargetRegClass);

209 TII->get(TargetOpcode::INIT_UNDEF), NewReg);

213 return true;

214}

215

218 bool Changed = false;

221

222

223

224 unsigned UseOpIdx;

225 if (MI.getNumDefs() != 0 && MI.isRegTiedToUseOperand(0, &UseOpIdx)) {

229 TII->getRegClass(MI.getDesc(), UseOpIdx, TRI, MF);

230 Register NewDest = MRI->createVirtualRegister(RC);

231

232

233 NewRegs.insert(NewDest);

234 BuildMI(MBB, I, I->getDebugLoc(), TII->get(TargetOpcode::IMPLICIT_DEF),

235 NewDest);

236 UseMO.setReg(NewDest);

237 Changed = true;

238 }

239 }

240

242 if (MRI->subRegLivenessEnabled())

243 Changed |= handleSubReg(MF, MI, *DLD);

244 Changed |= handleReg(&MI);

245 }

246 }

247 return Changed;

248}

249

250bool InitUndef::runOnMachineFunction(MachineFunction &MF) {

252

253

254

255 if (->requiresDisjointEarlyClobberAndUndef())

256 return false;

257

259 TII = ST->getInstrInfo();

260 TRI = MRI->getTargetRegisterInfo();

261

262 bool Changed = false;

263 std::unique_ptr DLD;

264 if (MRI->subRegLivenessEnabled()) {

265 DLD = std::make_unique(MRI, TRI);

266 DLD->computeSubRegisterLaneBitInfo();

267 }

268

270 Changed |= processBasicBlock(MF, BB, DLD.get());

271

272 for (auto *DeadMI : DeadInsts)

273 DeadMI->eraseFromParent();

274 DeadInsts.clear();

275 NewRegs.clear();

276

277 return Changed;

278}

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder MachineInstrBuilder & DefMI

Analysis containing CSE Info

Analysis that tracks defined/used subregister lanes across COPY instructions and instructions that ge...

const HexagonInstrInfo * TII

static bool isEarlyClobberMI(MachineInstr &MI)

static bool findImplictDefMIFromReg(Register Reg, MachineRegisterInfo *MRI)

unsigned const TargetRegisterInfo * TRI

#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)

This file defines the SmallSet class.

This file defines the SmallVector class.

Represent the analysis usage information of a pass.

void setPreservesCFG()

This function should be called by the pass, iff they do not:

const VRegInfo & getVRegInfo(unsigned RegIdx) const

static constexpr unsigned NoRegister

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

virtual bool runOnMachineFunction(MachineFunction &MF)=0

runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

void setReg(Register Reg)

Change the register this operand corresponds to.

void setIsUndef(bool Val=true)

getReg - Returns the register number.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

virtual StringRef getPassName() const

getPassName - Return a nice clean name for a pass.

Wrapper class representing virtual and physical registers.

static unsigned virtReg2Index(Register Reg)

Convert a virtual register number to a 0-based index.

SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StringRef - Represent a constant reference to a string, i.e.

TargetInstrInfo - Interface to description of machine instruction set.

unsigned getID() const

Return the register class ID number.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

TargetSubtargetInfo - Generic base class for all target subtargets.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

Reg

All possible values of the reg field in the ModR/M byte.

This is an optimization pass for GlobalISel generic memory operations.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

Printable PrintLaneMask(LaneBitmask LaneMask)

Create Printable object to print LaneBitmasks on a raw_ostream.

bool any_of(R &&range, UnaryPredicate P)

Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.

raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)

Prints virtual and physical registers with or without a TRI instance.

Contains a bitmask of which lanes of a given virtual register are defined and which ones are actually...