InitUndef.cpp Source File (original) (raw)

56using namespace llvm;

58#define DEBUG_TYPE "init-undef"

59#define INIT_UNDEF_NAME "Init Undef Pass"

61namespace {

64public:

65 static char ID;

71 void getAnalysisUsage(AnalysisUsage &AU) const override {

74 }

77};

79class InitUndef {

89public:

92private:

99};

100

101}

102

103char InitUndefLegacy::ID = 0;

106

109 return DefMO.isReg() && DefMO.isEarlyClobber();

110 });

111}

112

114 for (auto &DefMI : MRI->def_instructions(Reg)) {

115 if (DefMI.getOpcode() == TargetOpcode::IMPLICIT_DEF)

116 return true;

117 }

118 return false;

119}

120

123 for (auto &UseMO : MI->uses()) {

124 if (!UseMO.isReg())

125 continue;

126 if (UseMO.isTied())

127 continue;

128 if (!UseMO.getReg().isVirtual())

129 continue;

130

132 Changed |= fixupIllOperand(MI, UseMO);

133 }

135}

136

137bool InitUndef::handleSubReg(MachineFunction &MF, MachineInstr &MI,

138 const DeadLaneDetector &DLD) {

140

141 for (MachineOperand &UseMO : MI.uses()) {

142 if (!UseMO.isReg())

143 continue;

144 if (!UseMO.getReg().isVirtual())

145 continue;

146 if (UseMO.isTied())

147 continue;

148

150 if (NewRegs.count(Reg))

151 continue;

153

154 if (Info.UsedLanes == Info.DefinedLanes)

155 continue;

156

157 const TargetRegisterClass *TargetRegClass = MRI->getRegClass(Reg);

158

159 LaneBitmask NeedDef = Info.UsedLanes & ~Info.DefinedLanes;

160

162 dbgs() << "Instruction has undef subregister.\n";

166 << " Need Def: " << PrintLaneMask(NeedDef) << "\n";

167 });

168

169 SmallVector SubRegIndexNeedInsert;

170 TRI->getCoveringSubRegIndexes(TargetRegClass, NeedDef,

171 SubRegIndexNeedInsert);

172

173

174

175

176 if (any_of(SubRegIndexNeedInsert, [&](unsigned Ind) -> bool {

177 return TRI ->getSubRegisterClass(TargetRegClass, Ind);

178 }))

179 continue;

180

182 for (auto ind : SubRegIndexNeedInsert) {

184 const TargetRegisterClass *SubRegClass =

185 TRI->getSubRegisterClass(TargetRegClass, ind);

186 Register TmpInitSubReg = MRI->createVirtualRegister(SubRegClass);

187 LLVM_DEBUG(dbgs() << "Register Class ID" << SubRegClass->getID() << "\n");

189 TII->get(TargetOpcode::INIT_UNDEF), TmpInitSubReg);

190 Register NewReg = MRI->createVirtualRegister(TargetRegClass);

192 TII->get(TargetOpcode::INSERT_SUBREG), NewReg)

194 .addReg(TmpInitSubReg)

196 LatestReg = NewReg;

197 }

198

199 UseMO.setReg(LatestReg);

200 }

201

203}

204

205bool InitUndef::fixupIllOperand(MachineInstr *MI, MachineOperand &MO) {

206

208 dbgs() << "Emitting PseudoInitUndef Instruction for implicit register "

210

211 const TargetRegisterClass *TargetRegClass = MRI->getRegClass(MO.getReg());

212 LLVM_DEBUG(dbgs() << "Register Class ID" << TargetRegClass->getID() << "\n");

213 Register NewReg = MRI->createVirtualRegister(TargetRegClass);

215 TII->get(TargetOpcode::INIT_UNDEF), NewReg);

219 return true;

220}

221

222bool InitUndef::processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB,

223 const DeadLaneDetector *DLD) {

226 MachineInstr &MI = *I;

227

228

229

230 unsigned UseOpIdx;

231 if (MI.getNumDefs() != 0 && MI.isRegTiedToUseOperand(0, &UseOpIdx)) {

232 MachineOperand &UseMO = MI.getOperand(UseOpIdx);

234 const TargetRegisterClass *RC =

235 TII->getRegClass(MI.getDesc(), UseOpIdx);

236 Register NewDest = MRI->createVirtualRegister(RC);

237

238

239 NewRegs.insert(NewDest);

240 BuildMI(MBB, I, I->getDebugLoc(), TII->get(TargetOpcode::IMPLICIT_DEF),

241 NewDest);

242 UseMO.setReg(NewDest);

244 }

245 }

246

248 if (MRI->subRegLivenessEnabled())

249 Changed |= handleSubReg(MF, MI, *DLD);

251 }

252 }

254}

255

256bool InitUndefLegacy::runOnMachineFunction(MachineFunction &MF) {

257 return InitUndef().run(MF);

258}

259

262 if (!InitUndef().run(MF))

266 return PA;

267}

268

271

272

273

275 return false;

276

279 TRI = MRI->getTargetRegisterInfo();

280

282 std::unique_ptr DLD;

283 if (MRI->subRegLivenessEnabled()) {

284 DLD = std::make_unique(MRI, TRI);

285 DLD->computeSubRegisterLaneBitInfo();

286 }

287

289 Changed |= processBasicBlock(MF, BB, DLD.get());

290

291 for (auto *DeadMI : DeadInsts)

292 DeadMI->eraseFromParent();

293 DeadInsts.clear();

294 NewRegs.clear();

295

297}

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder MachineInstrBuilder & DefMI

Analysis containing CSE Info

Analysis that tracks defined/used subregister lanes across COPY instructions and instructions that ge...

const HexagonInstrInfo * TII

static bool isEarlyClobberMI(MachineInstr &MI)

Definition InitUndef.cpp:107

#define INIT_UNDEF_NAME

Definition InitUndef.cpp:59

static bool findImplictDefMIFromReg(Register Reg, MachineRegisterInfo *MRI)

Definition InitUndef.cpp:113

Promote Memory to Register

#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)

This file defines the SmallSet class.

This file defines the SmallVector class.

Represent the analysis usage information of a pass.

LLVM_ABI void setPreservesCFG()

This function should be called by the pass, iff they do not:

Represents analyses that only rely on functions' control flow.

const VRegInfo & getVRegInfo(unsigned RegIdx) const

PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)

Definition InitUndef.cpp:260

static constexpr unsigned NoRegister

MachineInstrBundleIterator< MachineInstr > iterator

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

LLVM_ABI void setReg(Register Reg)

Change the register this operand corresponds to.

void setIsUndef(bool Val=true)

getReg - Returns the register number.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

A set of analyses that are preserved following a run of a transformation pass.

static PreservedAnalyses all()

Construct a special preserved set that preserves all passes.

Wrapper class representing virtual and physical registers.

unsigned virtRegIndex() const

Convert a virtual register number to a 0-based index.

SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StringRef - Represent a constant reference to a string, i.e.

TargetInstrInfo - Interface to description of machine instruction set.

unsigned getID() const

Return the register class ID number.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

TargetSubtargetInfo - Generic base class for all target subtargets.

virtual bool requiresDisjointEarlyClobberAndUndef() const

Whether the target has instructions where an early-clobber result operand cannot overlap with an unde...

virtual const TargetInstrInfo * getInstrInfo() const

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

This is an optimization pass for GlobalISel generic memory operations.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

LLVM_ABI char & InitUndefID

Definition InitUndef.cpp:105

Printable PrintLaneMask(LaneBitmask LaneMask)

Create Printable object to print LaneBitmasks on a raw_ostream.

AnalysisManager< MachineFunction > MachineFunctionAnalysisManager

LLVM_ABI PreservedAnalyses getMachineFunctionPassPreservedAnalyses()

Returns the minimum set of Analyses that all machine function passes must preserve.

bool any_of(R &&range, UnaryPredicate P)

Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

LLVM_ABI Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)

Prints virtual and physical registers with or without a TRI instance.