LanaiAsmParser.cpp Source File (original) (raw)

33#include

34#include

35#include

36#include

37#include

39using namespace llvm;

44namespace {

46struct LanaiOperand;

50 std::unique_ptr parseRegister(bool RestoreOnFailure = false);

54 std::unique_ptr parseIdentifier();

56 unsigned parseAluOperator(bool PreOp, bool PostOp);

62 bool parsePrePost(StringRef Type, int *OffsetValue);

69 SMLoc &EndLoc) override;

71 bool matchAndEmitInstruction(SMLoc IdLoc, unsigned &Opcode,

74 bool MatchingInlineAsm) override;

77#define GET_ASSEMBLER_HEADER

78#include "LanaiGenAsmMatcher.inc"

84public:

88 Lexer(Parser.getLexer()), SubtargetInfo(STI) {

89 setAvailableFeatures(

90 ComputeAvailableFeatures(SubtargetInfo.getFeatureBits()));

91 }

93private:

94 MCAsmParser &Parser;

95 AsmLexer &Lexer;

97 const MCSubtargetInfo &SubtargetInfo;

98};

100

101

103 enum KindTy {

104 TOKEN,

105 REGISTER,

106 IMMEDIATE,

107 MEMORY_IMM,

108 MEMORY_REG_IMM,

109 MEMORY_REG_REG,

110 } Kind;

111

112 SMLoc StartLoc, EndLoc;

113

114 struct Token {

115 const char *Data;

116 unsigned Length;

117 };

118

119 struct RegOp {

120 MCRegister RegNum;

121 };

122

123 struct ImmOp {

124 const MCExpr *Value;

125 };

126

127 struct MemOp {

128 MCRegister BaseReg;

129 MCRegister OffsetReg;

130 unsigned AluOp;

131 const MCExpr *Offset;

132 };

133

134 union {

135 struct Token Tok;

136 struct RegOp Reg;

137 struct ImmOp Imm;

138 struct MemOp Mem;

139 };

140

141 explicit LanaiOperand(KindTy Kind) : Kind(Kind) {}

142

143public:

144

145

146

147

148 SMLoc getStartLoc() const override { return StartLoc; }

149

150

151 SMLoc getEndLoc() const override { return EndLoc; }

152

153 MCRegister getReg() const override {

154 assert(isReg() && "Invalid type access!");

155 return Reg.RegNum;

156 }

157

158 const MCExpr *getImm() const {

159 assert(isImm() && "Invalid type access!");

160 return Imm.Value;

161 }

162

164 assert(isToken() && "Invalid type access!");

165 return StringRef(Tok.Data, Tok.Length);

166 }

167

168 MCRegister getMemBaseReg() const {

169 assert(isMem() && "Invalid type access!");

170 return Mem.BaseReg;

171 }

172

173 MCRegister getMemOffsetReg() const {

174 assert(isMem() && "Invalid type access!");

175 return Mem.OffsetReg;

176 }

177

178 const MCExpr *getMemOffset() const {

179 assert(isMem() && "Invalid type access!");

180 return Mem.Offset;

181 }

182

183 unsigned getMemOp() const {

184 assert(isMem() && "Invalid type access!");

185 return Mem.AluOp;

186 }

187

188

189 bool isReg() const override { return Kind == REGISTER; }

190

191 bool isImm() const override { return Kind == IMMEDIATE; }

192

193 bool isMem() const override {

194 return isMemImm() || isMemRegImm() || isMemRegReg();

195 }

196

197 bool isMemImm() const { return Kind == MEMORY_IMM; }

198

199 bool isMemRegImm() const { return Kind == MEMORY_REG_IMM; }

200

201 bool isMemRegReg() const { return Kind == MEMORY_REG_REG; }

202

203 bool isMemSpls() const { return isMemRegImm() || isMemRegReg(); }

204

205 bool isToken() const override { return Kind == TOKEN; }

206

207 bool isBrImm() {

208 if (!isImm())

209 return false;

210

211

213 if (!MCE)

214 return true;

216

218 }

219

220 bool isBrTarget() { return isBrImm() || isToken(); }

221

222 bool isCallTarget() { return isImm() || isToken(); }

223

224 bool isHiImm16() {

225 if (!isImm())

226 return false;

227

228

230 int64_t Value = ConstExpr->getValue();

232 }

233

234

237

238

240 if (const auto *SymbolRefExpr =

243

244 return false;

245 }

246

247 bool isHiImm16And() {

248 if (!isImm())

249 return false;

250

252 if (ConstExpr) {

254

255 return (Value != 0) && ((Value & ~0xffff0000) == 0xffff);

256 }

257 return false;

258 }

259

260 bool isLoImm16() {

261 if (!isImm())

262 return false;

263

264

267

269 }

270

271

274

275

277 if (const auto *SymbolRefExpr =

280

281 return false;

282 }

283

284 bool isLoImm16Signed() {

285 if (!isImm())

286 return false;

287

288

291

293 }

294

295

298

299

301 if (const auto *SymbolRefExpr =

304

305 return false;

306 }

307

308 bool isLoImm16And() {

309 if (!isImm())

310 return false;

311

313 if (ConstExpr) {

315

316 return ((Value & ~0xffff) == 0xffff0000);

317 }

318 return false;

319 }

320

321 bool isImmShift() {

322 if (!isImm())

323 return false;

324

326 if (!ConstExpr)

327 return false;

329 return (Value >= -31) && (Value <= 31);

330 }

331

332 bool isLoImm21() {

333 if (!isImm())

334 return false;

335

336

340 }

341

342

344 return SymbolRefExpr->getSpecifier() == Lanai::S_None;

345 if (const MCSymbolRefExpr *SymbolRefExpr =

347 return SymbolRefExpr->getSpecifier() == 0;

348 }

349

350

352 if (const auto *SymbolRefExpr =

354 return SymbolRefExpr->getSpecifier() == Lanai::S_None;

355 if (const MCSymbolRefExpr *SymbolRefExpr =

357 return SymbolRefExpr->getSpecifier() == 0;

358 }

359

360 return false;

361 }

362

363 bool isImm10() {

364 if (!isImm())

365 return false;

366

368 if (!ConstExpr)

369 return false;

372 }

373

374 bool isCondCode() {

375 if (!isImm())

376 return false;

377

379 if (!ConstExpr)

380 return false;

382

383

384

386 }

387

388 void addExpr(MCInst &Inst, const MCExpr *Expr) const {

389

390 if (Expr == nullptr)

395 else

397 }

398

399 void addRegOperands(MCInst &Inst, unsigned N) const {

400 assert(N == 1 && "Invalid number of operands!");

402 }

403

404 void addImmOperands(MCInst &Inst, unsigned N) const {

405 assert(N == 1 && "Invalid number of operands!");

406 addExpr(Inst, getImm());

407 }

408

409 void addBrTargetOperands(MCInst &Inst, unsigned N) const {

410 assert(N == 1 && "Invalid number of operands!");

411 addExpr(Inst, getImm());

412 }

413

415 assert(N == 1 && "Invalid number of operands!");

416 addExpr(Inst, getImm());

417 }

418

419 void addCondCodeOperands(MCInst &Inst, unsigned N) const {

420 assert(N == 1 && "Invalid number of operands!");

421 addExpr(Inst, getImm());

422 }

423

424 void addMemImmOperands(MCInst &Inst, unsigned N) const {

425 assert(N == 1 && "Invalid number of operands!");

426 const MCExpr *Expr = getMemOffset();

427 addExpr(Inst, Expr);

428 }

429

430 void addMemRegImmOperands(MCInst &Inst, unsigned N) const {

431 assert(N == 3 && "Invalid number of operands!");

433 const MCExpr *Expr = getMemOffset();

434 addExpr(Inst, Expr);

436 }

437

438 void addMemRegRegOperands(MCInst &Inst, unsigned N) const {

439 assert(N == 3 && "Invalid number of operands!");

441 assert(getMemOffsetReg() && "Invalid offset");

444 }

445

446 void addMemSplsOperands(MCInst &Inst, unsigned N) const {

447 if (isMemRegImm())

448 addMemRegImmOperands(Inst, N);

449 if (isMemRegReg())

450 addMemRegRegOperands(Inst, N);

451 }

452

453 void addImmShiftOperands(MCInst &Inst, unsigned N) const {

454 assert(N == 1 && "Invalid number of operands!");

455 addExpr(Inst, getImm());

456 }

457

458 void addImm10Operands(MCInst &Inst, unsigned N) const {

459 assert(N == 1 && "Invalid number of operands!");

460 addExpr(Inst, getImm());

461 }

462

463 void addLoImm16Operands(MCInst &Inst, unsigned N) const {

464 assert(N == 1 && "Invalid number of operands!");

469#ifndef NDEBUG

472#endif

475#ifndef NDEBUG

480#endif

482 } else

483 assert(false && "Operand type not supported.");

484 }

485

486 void addLoImm16AndOperands(MCInst &Inst, unsigned N) const {

487 assert(N == 1 && "Invalid number of operands!");

490 else

491 assert(false && "Operand type not supported.");

492 }

493

494 void addHiImm16Operands(MCInst &Inst, unsigned N) const {

495 assert(N == 1 && "Invalid number of operands!");

499#ifndef NDEBUG

502#endif

505#ifndef NDEBUG

510#endif

512 } else

513 assert(false && "Operand type not supported.");

514 }

515

516 void addHiImm16AndOperands(MCInst &Inst, unsigned N) const {

517 assert(N == 1 && "Invalid number of operands!");

520 else

521 assert(false && "Operand type not supported.");

522 }

523

524 void addLoImm21Operands(MCInst &Inst, unsigned N) const {

525 assert(N == 1 && "Invalid number of operands!");

529#ifndef NDEBUG

532#endif

535#ifndef NDEBUG

536 const MCSymbolRefExpr *SymbolRefExpr =

539#endif

542#ifndef NDEBUG

547#endif

549 } else

550 assert(false && "Operand type not supported.");

551 }

552

553 void print(raw_ostream &OS, const MCAsmInfo &MAI) const override {

554 switch (Kind) {

555 case IMMEDIATE:

556 OS << "Imm: " << getImm() << "\n";

557 break;

558 case TOKEN:

559 OS << "Token: " << getToken() << "\n";

560 break;

561 case REGISTER:

562 OS << "Reg: %r" << getReg().id() << "\n";

563 break;

564 case MEMORY_IMM:

565 OS << "MemImm: ";

566 MAI.printExpr(OS, *getMemOffset());

567 OS << '\n';

568 break;

569 case MEMORY_REG_IMM:

570 OS << "MemRegImm: " << getMemBaseReg().id() << "+";

571 MAI.printExpr(OS, *getMemOffset());

572 OS << '\n';

573 break;

574 case MEMORY_REG_REG:

575 assert(getMemOffset() == nullptr);

576 OS << "MemRegReg: " << getMemBaseReg().id() << "+"

577 << "%r" << getMemOffsetReg().id() << "\n";

578 break;

579 }

580 }

581

582 static std::unique_ptr CreateToken(StringRef Str, SMLoc Start) {

583 auto Op = std::make_unique(TOKEN);

584 Op->Tok.Data = Str.data();

585 Op->Tok.Length = Str.size();

588 return Op;

589 }

590

591 static std::unique_ptr createReg(MCRegister Reg, SMLoc Start,

592 SMLoc End) {

593 auto Op = std::make_unique(REGISTER);

594 Op->Reg.RegNum = Reg;

596 Op->EndLoc = End;

597 return Op;

598 }

599

600 static std::unique_ptr createImm(const MCExpr *Value,

601 SMLoc Start, SMLoc End) {

602 auto Op = std::make_unique(IMMEDIATE);

605 Op->EndLoc = End;

606 return Op;

607 }

608

609 static std::unique_ptr

610 MorphToMemImm(std::unique_ptr Op) {

611 const MCExpr *Imm = Op->getImm();

612 Op->Kind = MEMORY_IMM;

613 Op->Mem.BaseReg = MCRegister();

615 Op->Mem.OffsetReg = 0;

616 Op->Mem.Offset = Imm;

617 return Op;

618 }

619

620 static std::unique_ptr

621 MorphToMemRegReg(MCRegister BaseReg, std::unique_ptr Op,

622 unsigned AluOp) {

623 MCRegister OffsetReg = Op->getReg();

624 Op->Kind = MEMORY_REG_REG;

626 Op->Mem.AluOp = AluOp;

627 Op->Mem.OffsetReg = OffsetReg;

628 Op->Mem.Offset = nullptr;

629 return Op;

630 }

631

632 static std::unique_ptr

633 MorphToMemRegImm(MCRegister BaseReg, std::unique_ptr Op,

634 unsigned AluOp) {

635 const MCExpr *Imm = Op->getImm();

636 Op->Kind = MEMORY_REG_IMM;

638 Op->Mem.AluOp = AluOp;

639 Op->Mem.OffsetReg = 0;

640 Op->Mem.Offset = Imm;

641 return Op;

642 }

643};

644

645}

646

647bool LanaiAsmParser::matchAndEmitInstruction(SMLoc IdLoc, unsigned &Opcode,

651 bool MatchingInlineAsm) {

652 MCInst Inst;

653 SMLoc ErrorLoc;

654

655 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {

656 case Match_Success:

659 return false;

660 case Match_MissingFeature:

661 return Error(IdLoc, "Instruction use requires option to be enabled");

662 case Match_MnemonicFail:

663 return Error(IdLoc, "Unrecognized instruction mnemonic");

664 case Match_InvalidOperand: {

665 ErrorLoc = IdLoc;

666 if (ErrorInfo != ~0U) {

667 if (ErrorInfo >= Operands.size())

668 return Error(IdLoc, "Too few operands for instruction");

669

670 ErrorLoc = ((LanaiOperand &)*Operands[ErrorInfo]).getStartLoc();

671 if (ErrorLoc == SMLoc())

672 ErrorLoc = IdLoc;

673 }

674 return Error(ErrorLoc, "Invalid operand for instruction");

675 }

676 default:

677 break;

678 }

679

681}

682

683

684

685

686

687std::unique_ptr

688LanaiAsmParser::parseRegister(bool RestoreOnFailure) {

691 std::optional PercentTok;

692

693 MCRegister Reg;

694

696 PercentTok = Parser.getTok();

697 Parser.Lex();

698 }

701 if ( Reg ) {

702 if (PercentTok && RestoreOnFailure)

703 Lexer.UnLex(*PercentTok);

704 return nullptr;

705 }

706 Parser.Lex();

707 return LanaiOperand::createReg(Reg, Start, End);

708 }

709 if (PercentTok && RestoreOnFailure)

710 Lexer.UnLex(*PercentTok);

711 return nullptr;

712}

713

714bool LanaiAsmParser::parseRegister(MCRegister &RegNum, SMLoc &StartLoc,

715 SMLoc &EndLoc) {

716 const AsmToken &Tok = getParser().getTok();

717 StartLoc = Tok.getLoc();

719 std::unique_ptr Op = parseRegister(false);

720 if (Op != nullptr)

721 RegNum = Op->getReg();

722 return (Op == nullptr);

723}

724

725ParseStatus LanaiAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,

726 SMLoc &EndLoc) {

727 const AsmToken &Tok = getParser().getTok();

728 StartLoc = Tok.getLoc();

730 std::unique_ptr Op = parseRegister(true);

731 if (Op == nullptr)

733 Reg = Op->getReg();

735}

736

737std::unique_ptr LanaiAsmParser::parseIdentifier() {

740 const MCExpr *Res, *RHS = nullptr;

742

744 return nullptr;

745

748 return nullptr;

749

750

751 if (Identifier.equals_insensitive("hi"))

753 else if (Identifier.equals_insensitive("lo"))

755

756

757

761 return nullptr;

762 }

763 Lexer.Lex();

764

765

767 return nullptr;

768 }

769

770

772 return nullptr;

773

774

778 return nullptr;

779 }

780 Lexer.Lex();

781 }

782

786

787

790

791 return LanaiOperand::createImm(Res, Start, End);

792}

793

794std::unique_ptr LanaiAsmParser::parseImmediate() {

797

798 const MCExpr *ExprVal;

799 switch (Lexer.getKind()) {

801 return parseIdentifier();

807 return LanaiOperand::createImm(ExprVal, Start, End);

808 [[fallthrough]];

809 default:

810 return nullptr;

811 }

812}

813

814static unsigned AluWithPrePost(unsigned AluCode, bool PreOp, bool PostOp) {

815 if (PreOp)

817 if (PostOp)

819 return AluCode;

820}

821

822unsigned LanaiAsmParser::parseAluOperator(bool PreOp, bool PostOp) {

823 StringRef IdString;

828 return 0;

829 }

831}

832

836

837bool LanaiAsmParser::parsePrePost(StringRef Type, int *OffsetValue) {

838 bool PreOrPost = false;

840 PreOrPost = true;

845 else

846 return false;

847

848

849 Parser.Lex();

850 Parser.Lex();

852 Parser.Lex();

853 PreOrPost = true;

854 }

855

856 return PreOrPost;

857}

858

860

861

864 return (Value % 4 == 0) && (Value >= 0) && (Value <= 0x1fffff);

865 }

866

867

870

871

872

874 const auto *LHSSymbolRefExpr =

876 return (LHSSymbolRefExpr &&

877 LHSSymbolRefExpr->getSpecifier() == Lanai::S_None);

878 }

879 return false;

880}

881

882

883ParseStatus LanaiAsmParser::parseMemoryOperand(OperandVector &Operands) {

884

885

886

887

888

889

890

891

892

893

894

895 StringRef Type;

896 if (Operands[0]->isToken())

897 Type = static_cast<LanaiOperand *>(Operands[0].get())->getToken();

898

899

900 int OffsetValue = 0;

903 bool PostOp = false, PreOp = false;

904

905

906 std::unique_ptr Op = parseRegister();

907 if ()

909

910

912 if ()

914

915

916

917

920 }

921

922 Parser.Lex();

923 std::unique_ptr Offset = nullptr;

924 if (Op)

926

927

928 PreOp = parsePrePost(Type, &OffsetValue);

929

930 Op = parseRegister();

931 if () {

934 Parser.Lex();

935

936

937

939 Operands.push_back(LanaiOperand::MorphToMemImm(std::move(Op)));

940 } else {

941 if (->isLoImm16Signed())

943 "Memory address is not word aligned and larger than "

944 "class RM can handle");

945 Operands.push_back(LanaiOperand::MorphToMemRegImm(

947 }

949 }

950 }

951

953 "Unknown operand, expected register or immediate");

954 }

956

957

958 if (!PreOp)

959 PostOp = parsePrePost(Type, &OffsetValue);

960

961

963 Parser.Lex();

966 SMLoc End =

968 const MCConstantExpr *OffsetConstExpr =

970 Offset = LanaiOperand::createImm(OffsetConstExpr, Start, End);

971 }

972 } else {

973 if (Offset || OffsetValue != 0)

975

976

977 AluOp = parseAluOperator(PreOp, PostOp);

978

979

980 Offset = parseRegister();

983 Parser.Lex();

984 }

985

986

987

989

990

991 if (Offset->isImm() && Offset ->isLoImm16Signed())

993 "Memory address is not word aligned and larger than class RM "

994 "can handle");

995

998 ? LanaiOperand::MorphToMemRegImm(BaseReg, std::move(Offset), AluOp)

999 : LanaiOperand::MorphToMemRegReg(BaseReg, std::move(Offset), AluOp));

1000

1002}

1003

1004

1005

1006

1007ParseStatus LanaiAsmParser::parseOperand(OperandVector *Operands,

1008 StringRef Mnemonic) {

1009

1010

1011 ParseStatus Result = MatchOperandParserImpl(*Operands, Mnemonic);

1012

1013 if (Result.isSuccess())

1015 if (Result.isFailure()) {

1018 }

1019

1020

1021 std::unique_ptr Op = parseRegister();

1022

1023

1024 if ()

1026

1027

1028 if () {

1032 }

1033

1034

1036

1038}

1039

1040

1041

1042StringRef LanaiAsmParser::splitMnemonic(StringRef Name, SMLoc NameLoc,

1044 size_t Next = Name.find('.');

1045

1046 StringRef Mnemonic = Name;

1047

1049

1050

1051 if (Mnemonic[0] == 'b' ||

1052 (Mnemonic[0] == 's' && !Mnemonic.starts_with("sel") &&

1054

1055

1059 Mnemonic = Mnemonic.slice(0, 1);

1060 Operands->push_back(LanaiOperand::CreateToken(Mnemonic, NameLoc));

1061 Operands->push_back(LanaiOperand::createImm(

1063 if (IsBRR) {

1064 Operands->push_back(LanaiOperand::CreateToken(".r", NameLoc));

1065 }

1066 return Mnemonic;

1067 }

1068 }

1069

1070

1071

1072

1073

1079

1080

1081

1082

1083

1085 Mnemonic = Mnemonic.substr(0, Next + 1);

1086 } else {

1087 Mnemonic = Mnemonic.substr(0, Next);

1088 }

1089 Operands->push_back(LanaiOperand::CreateToken(Mnemonic, NameLoc));

1090 Operands->push_back(LanaiOperand::createImm(

1092 return Mnemonic;

1093 }

1094 }

1095

1096 Operands->push_back(LanaiOperand::CreateToken(Mnemonic, NameLoc));

1097 if (IsBRR) {

1098 Operands->push_back(LanaiOperand::CreateToken(".r", NameLoc));

1099 }

1100

1101 return Mnemonic;

1102}

1103

1105

1106

1107

1108

1109

1110 bool Modifies = false;

1111

1113

1114 if (Operands.size() < 5)

1115 return false;

1116 else if (Operands[0]->isToken() && Operands[1]->isReg() &&

1117 Operands[2]->isImm() && Operands[3]->isImm() && Operands[4]->isReg())

1119 else if (Operands[0]->isToken() && Operands[1]->isToken() &&

1120 Operands[2]->isReg() && Operands[3]->isImm() &&

1121 Operands[4]->isImm() && Operands[5]->isReg())

1123 else

1124 return false;

1125

1126 int PossibleAluOpIdx = Offset + 3;

1127 int PossibleBaseIdx = Offset + 1;

1128 int PossibleDestIdx = Offset + 4;

1129 if (LanaiOperand *PossibleAluOp =

1130 static_cast<LanaiOperand *>(Operands[PossibleAluOpIdx].get()))

1131 if (PossibleAluOp->isImm())

1135 return Modifies && Operands[PossibleBaseIdx]->isReg() &&

1136 Operands[PossibleDestIdx]->isReg() &&

1137 Operands[PossibleBaseIdx]->getReg() ==

1138 Operands[PossibleDestIdx]->getReg();

1139}

1140

1142 return static_cast<const LanaiOperand &>(op).isReg();

1143}

1144

1146 if (Operands.size() < 4 || IsRegister (*Operands[1]) ||

1148 return false;

1150 static_cast<const LanaiOperand &>(*Operands[0]).getToken())

1160}

1161

1162bool LanaiAsmParser::parseInstruction(ParseInstructionInfo & ,

1163 StringRef Name, SMLoc NameLoc,

1165

1166 StringRef Mnemonic = splitMnemonic(Name, NameLoc, &Operands);

1167

1168

1170 return false;

1171

1172

1173 if (!parseOperand(&Operands, Mnemonic).isSuccess())

1174 return true;

1175

1176

1177

1179 Operands.size() == 2) {

1181 Operands.insert(Operands.begin(), LanaiOperand::CreateToken("s", NameLoc));

1183 LanaiOperand::createImm(

1185 NameLoc, NameLoc));

1186 }

1187

1188

1189

1190

1192 Operands.size() == 3) {

1194 Operands.insert(Operands.begin(), LanaiOperand::CreateToken("bt", NameLoc));

1195 }

1196

1197

1199

1200 Lex();

1201

1202

1203 if (!parseOperand(&Operands, Mnemonic).isSuccess())

1204 return true;

1205 }

1206

1209 "the destination register can't equal the base register in an "

1210 "instruction that modifies the base register.");

1211 return true;

1212 }

1213

1214

1215

1218 LanaiOperand::createImm(

1220 NameLoc, NameLoc));

1221 }

1222

1223 return false;

1224}

1225

1226#define GET_REGISTER_MATCHER

1227#define GET_MATCHER_IMPLEMENTATION

1228#include "LanaiGenAsmMatcher.inc"

1229

static MCRegister MatchRegisterName(StringRef Name)

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static bool addCallTargetOperands(MachineInstrBuilder &CallInst, MachineIRBuilder &MIRBuilder, AMDGPUCallLowering::CallLoweringInfo &Info, bool IsDynamicVGPRChainCall=false)

Analysis containing CSE Info

#define LLVM_EXTERNAL_VISIBILITY

static int SizeForSuffix(StringRef T)

Definition LanaiAsmParser.cpp:833

static bool IsMemoryAssignmentError(const OperandVector &Operands)

Definition LanaiAsmParser.cpp:1104

bool shouldBeSls(const LanaiOperand &Op)

Definition LanaiAsmParser.cpp:859

static MCRegister MatchRegisterName(StringRef Name)

static bool MaybePredicatedInst(const OperandVector &Operands)

Definition LanaiAsmParser.cpp:1145

static unsigned AluWithPrePost(unsigned AluCode, bool PreOp, bool PostOp)

Definition LanaiAsmParser.cpp:814

LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLanaiAsmParser()

Definition LanaiAsmParser.cpp:1231

static bool IsRegister(const MCParsedAsmOperand &op)

Definition LanaiAsmParser.cpp:1141

static MCRegister getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)

static bool isReg(const MCInst &MI, unsigned OpNo)

This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...

bool parseImmediate(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes)

SMLoc getLoc() const

Get the current source location.

const AsmToken peekTok(bool ShouldSkipSpace=true)

Look ahead at the next token to be lexed.

void UnLex(AsmToken const &Token)

AsmToken::TokenKind getKind() const

Get the kind of current token.

const AsmToken & getTok() const

Get the current (last) lexed token.

bool is(AsmToken::TokenKind K) const

Check if the current token has kind K.

const AsmToken & Lex()

Consume the next token from the input stream and return it.

bool isNot(AsmToken::TokenKind K) const

Check if the current token has kind K.

LLVM_ABI SMLoc getLoc() const

TokenKind getKind() const

LLVM_ABI SMLoc getEndLoc() const

StringRef getIdentifier() const

Get the identifier string for the current token, which should be an identifier or a string.

Base class for user error types.

void printExpr(raw_ostream &, const MCExpr &) const

Generic assembler parser interface, for use by target specific assembly parsers.

virtual void eatToEndOfStatement()=0

Skip to the end of the current statement, for error recovery.

virtual bool parseExpression(const MCExpr *&Res, SMLoc &EndLoc)=0

Parse an arbitrary expression.

const AsmToken & getTok() const

Get the current AsmToken from the stream.

virtual bool parseIdentifier(StringRef &Res)=0

Parse an identifier or string (as a quoted identifier) and set Res to the identifier contents.

virtual const AsmToken & Lex()=0

Get the next AsmToken in the stream, possibly handling file inclusion first.

Binary assembler expressions.

const MCExpr * getLHS() const

Get the left-hand side expression of the binary operator.

static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx, SMLoc Loc=SMLoc())

static LLVM_ABI const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)

unsigned getOpcode() const

void addOperand(const MCOperand Op)

Interface to description of machine instruction set.

static MCOperand createExpr(const MCExpr *Val)

static MCOperand createReg(MCRegister Reg)

static MCOperand createImm(int64_t Val)

MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand.

Wrapper class representing physical registers. Should be passed by value.

constexpr unsigned id() const

static const MCSpecifierExpr * create(const MCExpr *Expr, Spec S, MCContext &Ctx, SMLoc Loc=SMLoc())

Streaming machine code generation interface.

virtual void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)

Emit the given Instruction into the current section.

Generic base class for all target subtargets.

uint16_t getSpecifier() const

MCTargetAsmParser - Generic interface to target specific assembly parsers.

Ternary parse status returned by various parse* methods.

static constexpr StatusTy Failure

static constexpr StatusTy Success

static constexpr StatusTy NoMatch

Represents a location in source code.

static SMLoc getFromPointer(const char *Ptr)

constexpr const char * getPointer() const

iterator erase(const_iterator CI)

iterator insert(iterator I, T &&Elt)

void push_back(const T &Elt)

StringRef - Represent a constant reference to a string, i.e.

bool consume_back(StringRef Suffix)

Returns true if this StringRef has the given suffix and removes that suffix.

constexpr StringRef substr(size_t Start, size_t N=npos) const

Return a reference to the substring from [Start, Start + N).

bool starts_with(StringRef Prefix) const

Check if this string starts with the given Prefix.

StringRef slice(size_t Start, size_t End) const

Return a reference to the substring from [Start, End).

size_t rfind(char C, size_t From=npos) const

Search for the last character C in the string.

bool ends_with(StringRef Suffix) const

Check if this string ends with the given Suffix.

A switch()-like statement whose cases are string literals.

StringSwitch & StartsWith(StringLiteral S, T Value)

StringSwitch & EndsWith(StringLiteral S, T Value)

The instances of the Type class are immutable: once they are created, they are never changed.

LLVM Value Representation.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

CondCode

ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...

static unsigned makePostOp(unsigned AluOp)

static unsigned makePreOp(unsigned AluOp)

static AluCode stringToLanaiAluCode(StringRef S)

static bool modifiesOp(unsigned AluOp)

static CondCode suffixToLanaiCondCode(StringRef S)

Context & getContext() const

BaseReg

Stack frame base register. Bit 0 of FREInfo.Info.

This is an optimization pass for GlobalISel generic memory operations.

FunctionAddr VTableAddr Value

Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr, unsigned DynamicVGPRBlockSize=0)

constexpr bool isInt(int64_t x)

Checks if an integer fits into the given bit width.

static bool isMem(const MachineInstr &MI, unsigned Op)

LLVM_ABI std::pair< StringRef, StringRef > getToken(StringRef Source, StringRef Delimiters=" \t\n\v\f\r")

getToken - This function extracts one token from source, ignoring any leading characters that appear ...

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

Target & getTheLanaiTarget()

SmallVectorImpl< std::unique_ptr< MCParsedAsmOperand > > OperandVector

MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)

decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)

constexpr bool isUInt(uint64_t x)

Checks if an unsigned integer fits into the given bit width.

bool isa(const From &Val)

isa - Return true if the parameter to the template is an instance of one of the template type argu...

FunctionAddr VTableAddr Next

DWARFExpression::Operation Op

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

constexpr bool isShiftedUInt(uint64_t x)

Checks if a unsigned integer is an N bit number shifted left by S.

RegisterMCAsmParser - Helper template for registering a target specific assembly parser,...