LLVM: lib/Target/Mips/Disassembler/MipsDisassembler.cpp File Reference (original) (raw)

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◆ DEBUG_TYPE

#define DEBUG_TYPE "mips-disassembler"

◆ DecodeStatus

◆ createMipsDisassembler()

◆ createMipselDisassembler()

◆ DecodeACC64DSPRegisterClass()

◆ DecodeAddiGroupBranch()

template

◆ DecodeAddiur2Simm7()

◆ DecodeAFGR64RegisterClass()

◆ DecodeANDI16Imm()

◆ DecodeBgtzGroupBranch()

template

◆ DecodeBgtzGroupBranchMMR6()

template

◆ DecodeBgtzlGroupBranch()

template

◆ DecodeBlezGroupBranch()

template

◆ DecodeBlezGroupBranchMMR6()

template

◆ DecodeBlezlGroupBranch()

template

◆ DecodeBranchTarget()

◆ DecodeBranchTarget10MM()

◆ DecodeBranchTarget1SImm16()

◆ DecodeBranchTarget21()

◆ DecodeBranchTarget21MM()

◆ DecodeBranchTarget26()

◆ DecodeBranchTarget26MM()

◆ DecodeBranchTarget7MM()

◆ DecodeBranchTargetMM()

◆ DecodeCacheeOp_CacheOpR6()

◆ DecodeCacheOp()

◆ DecodeCacheOpMM()

◆ DecodeCCRRegisterClass()

◆ DecodeCOP0RegisterClass()

◆ DecodeCOP2RegisterClass()

◆ DecodeCPU16RegsRegisterClass()

◆ DecodeCRC()

template

◆ DecodeDaddiGroupBranch()

template

◆ DecodeDAHIDATI()

template

◆ DecodeDAHIDATIMMR6()

template

◆ DecodeDEXT()

template

◆ DecodeDINS()

template

◆ DecodeDSPRRegisterClass()

◆ DecodeFCCRegisterClass()

◆ DecodeFGR32RegisterClass()

◆ DecodeFGR64RegisterClass()

◆ DecodeFGRCCRegisterClass()

◆ DecodeFIXMEInstruction()

◆ DecodeFMem()

◆ DecodeFMem2()

◆ DecodeFMem3()

◆ DecodeFMemCop2MMR6()

◆ DecodeFMemCop2R6()

◆ DecodeFMemMMR2()

◆ DecodeGPR32RegisterClass()

◆ DecodeGPR64RegisterClass()

◆ DecodeGPRMM16MovePRegisterClass()

◆ DecodeGPRMM16RegisterClass()

◆ DecodeGPRMM16ZeroRegisterClass()

◆ DecodeHI32DSPRegisterClass()

◆ DecodeHWRegsRegisterClass()

◆ DecodeInsSize()

◆ DecodeINSVE_DF()

template

INSVE_[BHWD] have an implicit operand that the generated decoder doesn't handle.

Definition at line 526 of file MipsDisassembler.cpp.

References Address, assert(), llvm::MCOperand::createImm(), DecodeMSA128BRegisterClass(), DecodeMSA128DRegisterClass(), DecodeMSA128HRegisterClass(), DecodeMSA128WRegisterClass(), llvm::MCDisassembler::Fail, llvm_unreachable, MI, and llvm::MCDisassembler::Success.

◆ DecodeJumpTarget()

◆ DecodeJumpTargetMM()

◆ DecodeJumpTargetXMM()

◆ DecodeLi16Imm()

◆ DecodeLO32DSPRegisterClass()

◆ DecodeLoadByte15()

◆ DecodeMem()

◆ DecodeMemEVA()

◆ DecodeMemMMGPImm7Lsl2()

◆ DecodeMemMMImm12()

Definition at line 1798 of file MipsDisassembler.cpp.

References llvm::MCInst::addOperand(), Address, llvm::sampleprof::Base, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), DecodeRegListOperand(), llvm::MCDisassembler::Fail, llvm::MCInst::getOpcode(), getReg(), Insn, llvm::Offset, and llvm::MCDisassembler::Success.

◆ DecodeMemMMImm16()

◆ DecodeMemMMImm4()

Definition at line 1667 of file MipsDisassembler.cpp.

References llvm::MCInst::addOperand(), Address, llvm::sampleprof::Base, llvm::MCOperand::createImm(), DecodeGPRMM16RegisterClass(), DecodeGPRMM16ZeroRegisterClass(), llvm::MCDisassembler::Fail, llvm::MCInst::getOpcode(), Insn, llvm::Offset, and llvm::MCDisassembler::Success.

◆ DecodeMemMMImm9()

◆ DecodeMemMMReglistImm4Lsl2()

◆ DecodeMemMMSPImm5Lsl2()

◆ DecodeMovePOperands()

◆ DecodeMovePRegPair()

◆ DecodeMSA128BRegisterClass()

◆ DecodeMSA128DRegisterClass()

◆ DecodeMSA128HRegisterClass()

◆ DecodeMSA128Mem()

Definition at line 1620 of file MipsDisassembler.cpp.

References llvm::MCInst::addOperand(), assert(), llvm::sampleprof::Base, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, llvm::MCInst::getOpcode(), getReg(), Insn, llvm::Offset, and llvm::MCDisassembler::Success.

◆ DecodeMSA128WRegisterClass()

◆ DecodeMSACtrlRegisterClass()

◆ DecodePOOL16BEncodedField()

◆ DecodePOP35GroupBranchMMR6()

template

◆ DecodePOP37GroupBranchMMR6()

template

◆ DecodePOP65GroupBranchMMR6()

template

◆ DecodePOP75GroupBranchMMR6()

template

◆ DecodePrefeOpMM()

◆ DecodePtrRegisterClass()

◆ DecodeRegListOperand()

◆ DecodeRegListOperand16()

◆ DecodeSimm18Lsl3()

◆ DecodeSimm19Lsl2()

◆ DecodeSimm23Lsl2()

◆ DecodeSimm9SP()

◆ DecodeSImmWithOffsetAndScale()

template<unsigned Bits, int Offset = 0, int ScaleBy = 1>

◆ DecodeSpecial3LlSc()

◆ DecodeSyncI()

◆ DecodeSyncI_MM()

◆ DecodeSynciR6()

◆ DecodeUImmWithOffset()

◆ DecodeUImmWithOffsetAndScale()

template<unsigned Bits, int Offset, int Scale>

◆ getReg()

Definition at line 520 of file MipsDisassembler.cpp.

References D.

Referenced by AddNodeIDCustom(), llvm::CombinerHelper::applyCombineInsertVecElts(), llvm::AMDGPUCombinerHelper::applyFoldableFneg(), llvm::CombinerHelper::applyFoldBinOpIntoSelect(), llvm::CombinerHelper::applyShiftOfShiftedLogic(), llvm::AArch64FrameLowering::assignCalleeSavedSpillSlots(), buildCopyToRegs(), llvm::CSEMIRBuilder::buildInstr(), llvm::PPCInstrInfo::canInsertSelect(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), llvm::GISelKnownBits::computeKnownBitsImpl(), conversionLibcall(), DecodeACC64DSPRegisterClass(), DecodeAddiGroupBranch(), DecodeAFGR64RegisterClass(), DecodeBgtzGroupBranch(), DecodeBgtzGroupBranchMMR6(), DecodeBgtzlGroupBranch(), DecodeBlezGroupBranch(), DecodeBlezGroupBranchMMR6(), DecodeBlezlGroupBranch(), DecodeCacheeOp_CacheOpR6(), DecodeCacheOp(), DecodeCacheOpMM(), DecodeCCRRegisterClass(), DecodeCOP0RegisterClass(), DecodeCOP2RegisterClass(), DecodeCRC(), DecodeDaddiGroupBranch(), DecodeDAHIDATI(), DecodeDAHIDATIMMR6(), DecodeDEXT(), DecodeDINS(), DecodeFCCRegisterClass(), DecodeFGR32RegisterClass(), DecodeFGR64RegisterClass(), DecodeFGRCCRegisterClass(), DecodeFMem(), DecodeFMem2(), DecodeFMem3(), DecodeFMemCop2MMR6(), DecodeFMemCop2R6(), DecodeFMemMMR2(), DecodeGPR32RegisterClass(), DecodeGPR64RegisterClass(), DecodeGPRMM16MovePRegisterClass(), DecodeGPRMM16RegisterClass(), DecodeGPRMM16ZeroRegisterClass(), DecodeHI32DSPRegisterClass(), DecodeLO32DSPRegisterClass(), DecodeLoadByte15(), DecodeMem(), DecodeMemEVA(), DecodeMemMMGPImm7Lsl2(), DecodeMemMMImm12(), DecodeMemMMImm16(), DecodeMemMMImm9(), DecodeMemMMSPImm5Lsl2(), DecodeMSA128BRegisterClass(), DecodeMSA128DRegisterClass(), DecodeMSA128HRegisterClass(), DecodeMSA128Mem(), DecodeMSA128WRegisterClass(), DecodeMSACtrlRegisterClass(), DecodePOP35GroupBranchMMR6(), DecodePOP37GroupBranchMMR6(), DecodePOP65GroupBranchMMR6(), DecodePOP75GroupBranchMMR6(), DecodePrefeOpMM(), DecodeSpecial3LlSc(), DecodeSyncI(), DecodeSyncI_MM(), DecodeSynciR6(), llvm::SIInstrInfo::expandMovDPP64(), llvm::LegalizerHelper::fewerElementsVectorReductions(), llvm::LegalizerHelper::fewerElementsVectorShuffle(), findRenameRegForSameLdStRegPair(), llvm::MachineInstr::getFirst2LLTs(), llvm::MachineInstr::getFirst2Regs(), llvm::MachineInstr::getFirst3LLTs(), llvm::MachineInstr::getFirst3Regs(), llvm::MachineInstr::getFirst4LLTs(), llvm::MachineInstr::getFirst4Regs(), llvm::MachineInstr::getFirst5LLTs(), llvm::MachineInstr::getFirst5Regs(), getMaskSetter(), getMaxCalleeSavedReg(), getUnderlyingArgRegs(), llvm::HexagonInstrInfo::insertBranch(), llvm::PPCInstrInfo::insertBranch(), llvm::XCoreInstrInfo::insertBranch(), llvm::XtensaInstrInfo::insertBranchAtInst(), llvm::XtensaInstrInfo::insertConstBranchAtInst(), llvm::AArch64InstrInfo::insertSelect(), llvm::PPCInstrInfo::insertSelect(), llvm::MachineInstr::isConstantValuePHI(), llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast(), llvm::AMDGPULegalizerInfo::legalizeAtomicCmpXChg(), llvm::AMDGPULegalizerInfo::legalizeCTLZ_ZERO_UNDEF(), llvm::ARMLegalizerInfo::legalizeCustom(), llvm::AArch64LegalizerInfo::legalizeIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeLaneOp(), llvm::LegalizerHelper::libcall(), llvm::LegalizerHelper::lowerDIVREM(), llvm::LegalizerHelper::lowerFunnelShiftWithInverse(), llvm::AArch64CallLowering::lowerReturn(), llvm::CombinerHelper::matchCombineFAddFpExtFMulToFMadOrFMAAggressive(), llvm::CombinerHelper::matchCombineFSubFMulToFMadOrFMA(), llvm::CombinerHelper::matchCombineFSubFNegFMulToFMadOrFMA(), llvm::CombinerHelper::matchCombineFSubFpExtFMulToFMadOrFMA(), mayCombineMisaligned(), llvm::LegalizerHelper::narrowScalar(), llvm::TargetInstrInfo::PredicateInstruction(), llvm::R600InstrInfo::PredicateInstruction(), llvm::ARMBaseInstrInfo::PredicateInstruction(), llvm::PPCInstrInfo::PredicateInstruction(), llvm::RegisterBankInfo::OperandsMapper::print(), llvm::X86FrameLowering::restoreCalleeSavedRegisters(), llvm::PPCInstrInfo::reverseBranchCondition(), llvm::RISCVDAGToDAGISel::selectVLOp(), simpleLibcall(), llvm::X86FrameLowering::spillCalleeSavedRegisters(), splatPartsI64WithVL(), and llvm::PPCInstrInfo::SubsumesPredicate().

◆ LLVMInitializeMipsDisassembler()

◆ readInstruction16()

◆ readInstruction32()