LLVM: lib/Target/Mips/Disassembler/MipsDisassembler.cpp File Reference (original) (raw)
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| Macros | |
|---|---|
| #define | DEBUG_TYPE "mips-disassembler" |
◆ DEBUG_TYPE
#define DEBUG_TYPE "mips-disassembler"
◆ createMipsDisassembler()
◆ createMipselDisassembler()
◆ DecodeACC64DSPRegisterClass()
◆ DecodeAddiGroupBranch()
template
◆ DecodeAddiur2Simm7()
◆ DecodeAFGR64RegisterClass()
◆ DecodeANDI16Imm()
◆ DecodeBgtzGroupBranch()
template
◆ DecodeBgtzGroupBranchMMR6()
template
◆ DecodeBgtzlGroupBranch()
template
◆ DecodeBlezGroupBranch()
template
◆ DecodeBlezGroupBranchMMR6()
template
◆ DecodeBlezlGroupBranch()
template
◆ DecodeBranchTarget()
◆ DecodeBranchTarget10MM()
◆ DecodeBranchTarget1SImm16()
◆ DecodeBranchTarget21()
◆ DecodeBranchTarget21MM()
◆ DecodeBranchTarget26()
◆ DecodeBranchTarget26MM()
◆ DecodeBranchTarget7MM()
◆ DecodeBranchTargetMM()
◆ DecodeCacheeOp_CacheOpR6()
◆ DecodeCacheOp()
◆ DecodeCacheOpMM()
◆ DecodeCCRRegisterClass()
◆ DecodeCOP0RegisterClass()
◆ DecodeCOP2RegisterClass()
◆ DecodeCPU16RegsRegisterClass()
◆ DecodeCRC()
template
◆ DecodeDaddiGroupBranch()
template
◆ DecodeDAHIDATI()
template
◆ DecodeDAHIDATIMMR6()
template
◆ DecodeDEXT()
template
◆ DecodeDINS()
template
◆ DecodeDSPRRegisterClass()
◆ DecodeFCCRegisterClass()
◆ DecodeFGR32RegisterClass()
◆ DecodeFGR64RegisterClass()
◆ DecodeFGRCCRegisterClass()
◆ DecodeFIXMEInstruction()
◆ DecodeFMem()
◆ DecodeFMem2()
◆ DecodeFMem3()
◆ DecodeFMemCop2MMR6()
◆ DecodeFMemCop2R6()
◆ DecodeFMemMMR2()
◆ DecodeGP32RegisterClass()
◆ DecodeGP64RegisterClass()
◆ DecodeGPR32RegisterClass()
◆ DecodeGPR64RegisterClass()
◆ DecodeGPRMM16MovePRegisterClass()
◆ DecodeGPRMM16RegisterClass()
◆ DecodeGPRMM16ZeroRegisterClass()
◆ DecodeHI32DSPRegisterClass()
◆ DecodeHWRegsRegisterClass()
◆ DecodeInsSize()
◆ DecodeINSVE_DF()
template
Definition at line 294 of file MipsDisassembler.cpp.
References assert(), llvm::MCOperand::createImm(), DecodeMSA128BRegisterClass(), DecodeMSA128DRegisterClass(), DecodeMSA128HRegisterClass(), DecodeMSA128WRegisterClass(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm_unreachable, MI, and llvm::MCDisassembler::Success.
◆ DecodeJumpTarget()
◆ DecodeJumpTargetMM()
◆ DecodeJumpTargetXMM()
◆ DecodeLi16Imm()
◆ DecodeLO32DSPRegisterClass()
◆ DecodeLoadByte15()
◆ DecodeMem()
Definition at line 1024 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::sampleprof::Base, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::MCD::fieldFromInstruction(), llvm::MCInst::getOpcode(), getReg(), llvm::Offset, Reg, llvm::SignExtend32(), and llvm::MCDisassembler::Success.
◆ DecodeMemEVA()
Definition at line 1044 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::sampleprof::Base, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::MCD::fieldFromInstruction(), llvm::MCInst::getOpcode(), getReg(), llvm::Offset, Reg, llvm::SignExtend32(), and llvm::MCDisassembler::Success.
◆ DecodeMemMMGPImm7Lsl2()
◆ DecodeMemMMImm12()
Definition at line 1361 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::sampleprof::Base, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), DecodeRegListOperand(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::MCInst::getOpcode(), getReg(), llvm::Offset, Reg, llvm::SignExtend32(), and llvm::MCDisassembler::Success.
◆ DecodeMemMMImm16()
◆ DecodeMemMMImm4()
Definition at line 1230 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::sampleprof::Base, llvm::MCOperand::createImm(), DecodeGPRMM16RegisterClass(), DecodeGPRMM16ZeroRegisterClass(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::MCInst::getOpcode(), llvm::Offset, Reg, and llvm::MCDisassembler::Success.
◆ DecodeMemMMImm9()
Definition at line 1341 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), llvm::sampleprof::Base, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::MCD::fieldFromInstruction(), llvm::MCInst::getOpcode(), getReg(), llvm::Offset, Reg, llvm::SignExtend32(), and llvm::MCDisassembler::Success.
◆ DecodeMemMMReglistImm4Lsl2()
◆ DecodeMemMMSPImm5Lsl2()
◆ DecodeMovePOperands()
◆ DecodeMovePRegPair()
◆ DecodeMSA128BRegisterClass()
◆ DecodeMSA128DRegisterClass()
◆ DecodeMSA128HRegisterClass()
◆ DecodeMSA128Mem()
Definition at line 1183 of file MipsDisassembler.cpp.
References llvm::MCInst::addOperand(), assert(), llvm::sampleprof::Base, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::MCDisassembler::Fail, llvm::MCD::fieldFromInstruction(), llvm::MCInst::getOpcode(), getReg(), llvm::Offset, Reg, llvm::SignExtend32(), and llvm::MCDisassembler::Success.
◆ DecodeMSA128WRegisterClass()
◆ DecodeMSACtrlRegisterClass()
◆ DecodePOOL16BEncodedField()
◆ DecodePOP35GroupBranchMMR6()
template
◆ DecodePOP37GroupBranchMMR6()
template
◆ DecodePOP65GroupBranchMMR6()
template
◆ DecodePOP75GroupBranchMMR6()
template
◆ DecodePrefeOpMM()
◆ DecodePtrRegisterClass()
◆ DecodeRegListOperand()
◆ DecodeRegListOperand16()
◆ DecodeSimm18Lsl3()
◆ DecodeSimm19Lsl2()
◆ DecodeSimm23Lsl2()
◆ DecodeSimm9SP()
◆ DecodeSImmWithOffsetAndScale()
template<unsigned Bits, int Offset = 0, int ScaleBy = 1>
◆ DecodeSP32RegisterClass()
◆ DecodeSP64RegisterClass()
◆ DecodeSpecial3LlSc()
◆ DecodeSyncI()
◆ DecodeSyncI_MM()
◆ DecodeSynciR6()
◆ DecodeUImmWithOffset()
◆ DecodeUImmWithOffsetAndScale()
template<unsigned Bits, int Offset, int Scale>
◆ getReg()
Definition at line 106 of file MipsDisassembler.cpp.
References D().
Referenced by AddNodeIDCustom(), llvm::CombinerHelper::applyFoldBinOpIntoSelect(), llvm::CombinerHelper::applyRepeatedFPDivisor(), llvm::CombinerHelper::applyShiftOfShiftedLogic(), buildCopyToRegs(), llvm::CSEMIRBuilder::buildInstr(), buildReadLane(), llvm::LegalizerHelper::buildVariableShiftPart(), llvm::PPCInstrInfo::canInsertSelect(), llvm::HexagonPacketizerList::canPromoteToNewValueStore(), llvm::GISelValueTracking::computeKnownBitsImpl(), DecodeACC64DSPRegisterClass(), DecodeAddiGroupBranch(), DecodeAFGR64RegisterClass(), DecodeBgtzGroupBranch(), DecodeBgtzGroupBranchMMR6(), DecodeBgtzlGroupBranch(), DecodeBlezGroupBranch(), DecodeBlezGroupBranchMMR6(), DecodeBlezlGroupBranch(), DecodeCacheeOp_CacheOpR6(), DecodeCacheOp(), DecodeCacheOpMM(), DecodeCCRRegisterClass(), DecodeCOP0RegisterClass(), DecodeCOP2RegisterClass(), DecodeCRC(), DecodeDaddiGroupBranch(), DecodeDAHIDATI(), DecodeDAHIDATIMMR6(), DecodeDEXT(), DecodeDINS(), DecodeFCCRegisterClass(), DecodeFGR32RegisterClass(), DecodeFGR64RegisterClass(), DecodeFGRCCRegisterClass(), DecodeFMem(), DecodeFMem2(), DecodeFMem3(), DecodeFMemCop2MMR6(), DecodeFMemCop2R6(), DecodeFMemMMR2(), DecodeGPR32RegisterClass(), DecodeGPR64RegisterClass(), DecodeGPRMM16MovePRegisterClass(), DecodeGPRMM16RegisterClass(), DecodeGPRMM16ZeroRegisterClass(), DecodeHI32DSPRegisterClass(), DecodeLO32DSPRegisterClass(), DecodeLoadByte15(), DecodeMem(), DecodeMemEVA(), DecodeMemMMGPImm7Lsl2(), DecodeMemMMImm12(), DecodeMemMMImm16(), DecodeMemMMImm9(), DecodeMemMMSPImm5Lsl2(), DecodeMSA128BRegisterClass(), DecodeMSA128DRegisterClass(), DecodeMSA128HRegisterClass(), DecodeMSA128Mem(), DecodeMSA128WRegisterClass(), DecodeMSACtrlRegisterClass(), DecodePOP35GroupBranchMMR6(), DecodePOP37GroupBranchMMR6(), DecodePOP65GroupBranchMMR6(), DecodePOP75GroupBranchMMR6(), DecodePrefeOpMM(), DecodeSpecial3LlSc(), DecodeSyncI(), DecodeSyncI_MM(), DecodeSynciR6(), llvm::SIInstrInfo::expandMovDPP64(), llvm::LegalizerHelper::fewerElementsVectorReductions(), findRenameRegForSameLdStRegPair(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::MachineInstr::getFirst2LLTs(), llvm::MachineInstr::getFirst2Regs(), llvm::MachineInstr::getFirst3LLTs(), llvm::MachineInstr::getFirst3Regs(), llvm::MachineInstr::getFirst4LLTs(), llvm::MachineInstr::getFirst4Regs(), llvm::MachineInstr::getFirst5LLTs(), llvm::MachineInstr::getFirst5Regs(), getMaxCalleeSavedReg(), getUnderlyingArgRegs(), INITIALIZE_PASS(), llvm::HexagonInstrInfo::insertBranch(), llvm::PPCInstrInfo::insertBranch(), llvm::XCoreInstrInfo::insertBranch(), llvm::XtensaInstrInfo::insertBranchAtInst(), llvm::XtensaInstrInfo::insertConstBranchAtInst(), llvm::AArch64InstrInfo::insertSelect(), llvm::PPCInstrInfo::insertSelect(), llvm::MachineInstr::isConstantValuePHI(), llvm::AMDGPULegalizerInfo::legalizeAddrSpaceCast(), llvm::AMDGPULegalizerInfo::legalizeAtomicCmpXChg(), llvm::AMDGPULegalizerInfo::legalizeCTLZ_ZERO_UNDEF(), llvm::AArch64LegalizerInfo::legalizeIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeIsAddrSpace(), llvm::LegalizerHelper::lowerFMinimumMaximum(), llvm::LegalizerHelper::lowerFunnelShiftWithInverse(), llvm::AArch64CallLowering::lowerReturn(), llvm::CombinerHelper::matchCombineFAddFpExtFMulToFMadOrFMAAggressive(), mayCombineMisaligned(), llvm::ARMBaseInstrInfo::PredicateInstruction(), llvm::PPCInstrInfo::PredicateInstruction(), llvm::R600InstrInfo::PredicateInstruction(), llvm::TargetInstrInfo::PredicateInstruction(), llvm::RegisterBankInfo::OperandsMapper::print(), llvm::ARMInstPrinter::printModImmOperand(), llvm::BitTracker::RegisterRef::RegisterRef(), llvm::X86FrameLowering::restoreCalleeSavedRegisters(), llvm::PPCInstrInfo::reverseBranchCondition(), llvm::RISCVDAGToDAGISel::selectVLOp(), llvm::SGPRSpillBuilder::SGPRSpillBuilder(), llvm::X86FrameLowering::spillCalleeSavedRegisters(), and llvm::PPCInstrInfo::SubsumesPredicate().