LanaiISelLowering.cpp Source File (original) (raw)

47#include

48#include

49#include

50#include

51#include

53#define DEBUG_TYPE "lanai-lower"

55using namespace llvm;

66 "lanai-constant-mul-threshold", cl::Hidden,

67 cl::desc("Maximum number of instruction to generate when lowering constant "

68 "multiplication instead of calling library function [default=14]"),

103

110

116

122

127

131

132

137 }

138

140

141

144

146

147

148

149

150

152

159

160

162

164}

165

168 switch (Op.getOpcode()) {

171 case ISD::BR_CC:

189 case ISD::VASTART:

191 case ISD::DYNAMIC_STACKALLOC:

197 default:

199 }

200}

201

202

203

204

205

209

211 .Case("pc", Lanai::PC)

212 .Case("sp", Lanai::SP)

213 .Case("fp", Lanai::FP)

214 .Case("rr1", Lanai::RR1)

215 .Case("r10", Lanai::R10)

216 .Case("rr2", Lanai::RR2)

217 .Case("r11", Lanai::R11)

218 .Case("rca", Lanai::RCA)

220 return Reg;

221}

222

223std::pair<unsigned, const TargetRegisterClass *>

226 MVT VT) const {

227 if (Constraint.size() == 1)

228

229 switch (Constraint[0]) {

230 case 'r':

231 return std::make_pair(0U, &Lanai::GPRRegClass);

232 default:

233 break;

234 }

235

237}

238

239

240

241

244 AsmOperandInfo &Info, const char *Constraint) const {

246 Value *CallOperandVal = Info.CallOperandVal;

247

248

249 if (CallOperandVal == nullptr)

251

252 switch (*Constraint) {

253 case 'I':

254 case 'J':

255 case 'K':

256 case 'L':

257 case 'M':

258 case 'N':

259 case 'O':

262 break;

263 default:

265 break;

266 }

267 return Weight;

268}

269

270

271

276

277

278 if (Constraint.size() > 1)

279 return;

280

281 char ConstraintLetter = Constraint[0];

282 switch (ConstraintLetter) {

283 case 'I':

284

288 Op.getValueType());

289 break;

290 }

291 }

292 return;

293 case 'J':

294 case 'O':

296 if (C->getZExtValue() == 0) {

298 break;

299 }

300 }

301 return;

302 case 'K':

306 Op.getValueType());

307 break;

308 }

309 }

310 return;

311 case 'L':

313 if (C->getZExtValue() <= 31) {

315 Op.getValueType());

316 break;

317 }

318 }

319 return;

320 case 'M':

322 int64_t Val = C->getSExtValue();

323 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)) {

325 break;

326 }

327 }

328 return;

329 case 'N':

331 int64_t Val = C->getSExtValue();

332 if ((Val >= -33554432) && (Val <= 33554431)) {

334 break;

335 }

336 }

337 return;

338 default:

339 break;

340 }

341

342 if (Result.getNode()) {

343 Ops.push_back(Result);

344 return;

345 }

346

348}

349

350

351

352

353

354#include "LanaiGenCallingConv.inc"

355

360

361

362

364 return CC_Lanai32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, OrigTy, State);

365

366

367 if (LocVT == MVT::i8 || LocVT == MVT::i16) {

368 LocVT = MVT::i32;

369 if (ArgFlags.isSExt())

371 else if (ArgFlags.isZExt())

373 else

375 }

376

377

378 unsigned Offset = State.AllocateStack(4, Align(4));

380 return false;

381}

382

383SDValue LanaiTargetLowering::LowerFormalArguments(

387 switch (CallConv) {

390 return LowerCCCArguments(Chain, CallConv, IsVarArg, Ins, DL, DAG, InVals);

391 default:

393 }

394}

395

398 SelectionDAG &DAG = CLI.DAG;

399 SDLoc &DL = CLI.DL;

400 SmallVectorImplISD::OutputArg &Outs = CLI.Outs;

401 SmallVectorImpl &OutVals = CLI.OutVals;

402 SmallVectorImplISD::InputArg &Ins = CLI.Ins;

407 bool IsVarArg = CLI.IsVarArg;

408

409

410 IsTailCall = false;

411

412 switch (CallConv) {

415 return LowerCCCCallTo(Chain, Callee, CallConv, IsVarArg, IsTailCall, Outs,

416 OutVals, Ins, DL, DAG, InVals);

417 default:

419 }

420}

421

422

423

424SDValue LanaiTargetLowering::LowerCCCArguments(

430 MachineRegisterInfo &RegInfo = MF.getRegInfo();

431 LanaiMachineFunctionInfo *LanaiMFI = MF.getInfo();

432

433

435 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,

438 CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32_Fast);

439 } else {

440 CCInfo.AnalyzeFormalArguments(Ins, CC_Lanai32);

441 }

442

443 for (const CCValAssign &VA : ArgLocs) {

444 if (VA.isRegLoc()) {

445

446 EVT RegVT = VA.getLocVT();

448 case MVT::i32: {

450 RegInfo.addLiveIn(VA.getLocReg(), VReg);

452

453

454

455

462

465

467 break;

468 }

469 default:

470 LLVM_DEBUG(dbgs() << "LowerFormalArguments Unhandled argument type: "

471 << RegVT << "\n");

473 }

474 } else {

475

476 assert(VA.isMemLoc());

477

478 unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8;

479

480 if (ObjSize > 4) {

481 errs() << "LowerFormalArguments Unhandled argument type: "

482 << VA.getLocVT() << "\n";

483 }

484

485 int FI = MFI.CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);

486

487

488

491 VA.getLocVT(), DL, Chain, FIN,

493 }

494 }

495

496

497

498

501 if ( Reg ) {

504 }

507 }

508

509 if (IsVarArg) {

510

511

514 }

515

516 return Chain;

517}

518

522 const Type *RetTy) const {

524 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);

525

526 return CCInfo.CheckReturn(Outs, RetCC_Lanai32);

527}

528

531 bool IsVarArg,

535

537

538

541

542

543 CCInfo.AnalyzeReturn(Outs, RetCC_Lanai32);

544

547

548

549 for (unsigned i = 0; i != RVLocs.size(); ++i) {

551 assert(VA.isRegLoc() && "Can only return in registers!");

552

554

555

558 }

559

560

561

562

563

569 "SRetReturnReg should have been set in LowerFormalArguments().");

572

573 Chain = DAG.getCopyToReg(Chain, DL, Lanai::RV, Val, Glue);

575 RetOps.push_back(

577 }

578

579 RetOps[0] = Chain;

580

581 unsigned Opc = LanaiISD::RET_GLUE;

583 RetOps.push_back(Glue);

584

585

588}

589

590

591

592SDValue LanaiTargetLowering::LowerCCCCallTo(

598

600 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,

604

605 if (IsVarArg) {

607 } else {

609 CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32_Fast);

610 else

611 CCInfo.AnalyzeCallOperands(Outs, CC_Lanai32);

612 }

613

614

616

617

619 for (unsigned I = 0, E = Outs.size(); I != E; ++I) {

620 ISD::ArgFlagsTy Flags = Outs[I].Flags;

621 if ( Flags .isByVal())

622 continue;

623

625 unsigned Size = Flags.getByValSize();

626 Align Alignment = Flags.getNonZeroByValAlign();

627

631

632 Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Alignment,

633 false,

634 false,

635 nullptr, std::nullopt, MachinePointerInfo(),

636 MachinePointerInfo());

638 }

639

641

645

646

647 for (unsigned I = 0, J = 0, E = ArgLocs.size(); I != E; ++I) {

648 CCValAssign &VA = ArgLocs[I];

650 ISD::ArgFlagsTy Flags = Outs[I].Flags;

651

652

655 break;

658 break;

661 break;

664 break;

665 default:

667 }

668

669

670 if (Flags.isByVal())

671 Arg = ByValArgs[J++];

672

673

674

677 } else {

679

680 if (StackPtr.getNode() == nullptr)

683

687

689 DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()));

690 }

691 }

692

693

694

695 if (!MemOpChains.empty())

698

700

701

702

703

704 for (const auto &[Reg, N] : RegsToPass) {

707 }

708

709

710

711

713 if (G) {

719 }

720

721

722 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);

724 Ops.push_back(Chain);

725 Ops.push_back(Callee);

726

727

728

729 const uint32_t *Mask =

731 assert(Mask && "Missing call preserved mask for calling convention");

733

734

735

736 for (const auto &[Reg, N] : RegsToPass)

738

740 Ops.push_back(InGlue);

741

742 Chain = DAG.getNode(LanaiISD::CALL, DL, NodeTys,

745

746

749

750

751

752 return LowerCallResult(Chain, InGlue, CallConv, IsVarArg, Ins, DL, DAG,

753 InVals);

754}

755

756

757

758SDValue LanaiTargetLowering::LowerCallResult(

762

766

767 CCInfo.AnalyzeCallResult(Ins, RetCC_Lanai32);

768

769

770 for (unsigned I = 0; I != RVLocs.size(); ++I) {

772 RVLocs[I].getValVT(), InGlue)

776 }

777

778 return Chain;

779}

780

781

782

783

784

788

789

790

791

792

793 switch (SetCCOpcode) {

798 if (RHSC->getZExtValue() == 0xFFFFFFFF) {

799

802 }

808 if (RHSC->getZExtValue() == 0)

809

816 if (RHSC->getZExtValue() == 0xFFFFFFFF) {

817

820 }

826 if (RHSC->getZExtValue() == 0)

827

845 default:

847 }

848}

849

851 SDValue Chain = Op.getOperand(0);

857

860 SDValue Glue = DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS);

861

862 return DAG.getNode(LanaiISD::BR_CC, DL, Op.getValueType(), Chain, Dest,

863 TargetCC, Glue);

864}

865

867 EVT VT = Op->getValueType(0);

868 if (VT != MVT::i32)

870

872 if ()

874

875 int64_t MulAmt = C->getSExtValue();

876 int32_t HighestOne = -1;

878 int SignedDigit[32] = {0};

879

880

881

882

883

884

885

886

887

888

889 int64_t E = std::abs(MulAmt);

890 int S = (MulAmt < 0 ? -1 : 1);

891 int I = 0;

892 while (E > 0) {

893 int ZI = 0;

894 if (E % 2 == 1) {

895 ZI = 2 - (E % 4);

896 if (ZI != 0)

897 ++NonzeroEntries;

898 }

899 SignedDigit[I] = S * ZI;

900 if (SignedDigit[I] == 1)

901 HighestOne = I;

902 E = (E - ZI) / 2;

903 ++I;

904 }

905

906

907

908

909

910

911 int32_t InstrRequired = 2 * NonzeroEntries - 1;

912

913 if (std::abs(MulAmt) % 2 == 1)

914 --InstrRequired;

915

918

922

923

924

925

926 if (HighestOne == -1)

928 else {

931 SignedDigit[HighestOne] = 0;

932 }

933

934

935

936 for (unsigned int I = 0; I < std::size(SignedDigit); ++I) {

937 if (SignedDigit[I] == 0)

938 continue;

939

940

943 if (SignedDigit[I] == 1)

945 else if (SignedDigit[I] == -1)

947 }

948 return Res;

949}

950

956

959 SDValue Glue = DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS);

960

961 return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Glue);

962}

963

968 SDValue TrueV = Op.getOperand(2);

969 SDValue FalseV = Op.getOperand(3);

972

975 SDValue Glue = DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS);

976

977 return DAG.getNode(LanaiISD::SELECT_CC, DL, Op.getValueType(), TrueV, FalseV,

978 TargetCC, Glue);

979}

980

984

988

989

990

992 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),

994}

995

998 SDValue Chain = Op.getOperand(0);

1001

1003

1004

1006

1007

1008

1010

1011

1012

1013

1014

1015

1016

1017

1018

1019

1020

1021 SDValue ArgAdjust = DAG.getNode(LanaiISD::ADJDYNALLOC, DL, MVT::i32, Sub);

1022

1023

1024

1026

1027 SDValue Ops[2] = {ArgAdjust, CopyChain};

1029}

1030

1036

1037 EVT VT = Op.getValueType();

1039 unsigned Depth = Op.getConstantOperandVal(0);

1042 const unsigned Offset = -4;

1046 }

1047

1048

1049

1052}

1053

1058

1059 EVT VT = Op.getValueType();

1062 unsigned Depth = Op.getConstantOperandVal(0);

1063 while (Depth--) {

1064 const unsigned Offset = -8;

1067 FrameAddr =

1069 }

1070 return FrameAddr;

1071}

1072

1077 const Constant *C = N->getConstVal();

1081

1082

1083

1090 DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));

1091 } else {

1094

1096 N->getOffset(), OpFlagHi);

1098 N->getOffset(), OpFlagLo);

1099 Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);

1100 Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);

1102 return Result;

1103 }

1104}

1105

1111

1115

1116

1117

1124 DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));

1125 } else {

1128

1129

1134 Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);

1135 Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);

1137 }

1138}

1139

1144

1147

1150 Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);

1151 Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);

1153 return Result;

1154}

1155

1160

1161

1167 DAG.getNode(LanaiISD::SMALL, DL, MVT::i32, Small));

1168 } else {

1171

1176 Hi = DAG.getNode(LanaiISD::HI, DL, MVT::i32, Hi);

1177 Lo = DAG.getNode(LanaiISD::LO, DL, MVT::i32, Lo);

1179 return Result;

1180 }

1181}

1182

1185 EVT VT = Op.getValueType();

1188 assert(Op.getNumOperands() == 3 && "Unexpected SHL!");

1189 SDValue ShOpLo = Op.getOperand(0);

1190 SDValue ShOpHi = Op.getOperand(1);

1191 SDValue ShAmt = Op.getOperand(2);

1192

1193

1194

1195

1196

1197

1198

1199

1201 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);

1203

1204

1205

1208 LoBitsForHi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, LoBitsForHi);

1209

1213 SDValue HiForNormalShift =

1214 DAG.getNode(ISD::OR, dl, VT, LoBitsForHi, HiBitsForHi);

1215

1217

1220 DAG.getSelect(dl, MVT::i32, SetCC, HiForBigShift, HiForNormalShift);

1221

1222

1223

1226 dl, MVT::i32, SetCC, DAG.getConstant(0, dl, MVT::i32), LoForNormalShift);

1227

1230}

1231

1234 MVT VT = Op.getSimpleValueType();

1237 SDValue ShOpLo = Op.getOperand(0);

1238 SDValue ShOpHi = Op.getOperand(1);

1239 SDValue ShAmt = Op.getOperand(2);

1240

1241

1242

1243

1244

1245

1246

1247

1248

1249

1250

1251

1256

1258 Hi = DAG.getSelect(dl, MVT::i32, SetCC, Zero, Hi);

1259

1263 DAG.getNode(ISD::SHL, dl, MVT::i32, ShOpHi, NegatedPlus32);

1265 Lo = DAG.getSelect(dl, MVT::i32, ShiftIsZero, Lo,

1267

1270}

1271

1272

1276

1277

1278

1279

1280

1281

1282

1283

1284

1285

1286

1287

1288

1289

1290

1291

1292

1293

1294

1296 bool &Invert, SDValue &OtherOp,

1298 switch (N->getOpcode()) {

1299 default:

1300 return false;

1302 CC = N->getOperand(0);

1303 SDValue N1 = N->getOperand(1);

1304 SDValue N2 = N->getOperand(2);

1306 Invert = false;

1307 OtherOp = N2;

1308 return true;

1309 }

1311 Invert = true;

1312 OtherOp = N1;

1313 return true;

1314 }

1315 return false;

1316 }

1318

1320 return false;

1321 CC = N->getOperand(0);

1323 return false;

1325 EVT VT = N->getValueType(0);

1327 Invert = true;

1328 return true;

1329 }

1331 CC = N->getOperand(0);

1333 return false;

1335 EVT VT = N->getValueType(0);

1338

1339

1341 else

1343 return true;

1344 }

1345 }

1346}

1347

1348

1349

1350

1351

1352

1353

1354

1355

1356

1357

1358

1359

1360

1361

1362

1363

1364

1369 EVT VT = N->getValueType(0);

1372 bool SwapSelectOps;

1374 NonConstantVal, DAG))

1376

1377

1378 SDValue TrueVal = OtherOp;

1380 DAG.getNode(N->getOpcode(), SDLoc(N), VT, OtherOp, NonConstantVal);

1381

1382 if (SwapSelectOps)

1384

1386}

1387

1388

1392 SDValue N0 = N->getOperand(0);

1393 SDValue N1 = N->getOperand(1);

1396 return Result;

1399 return Result;

1401}

1402

1403

1406 SDValue N0 = N->getOperand(0);

1407 SDValue N1 = N->getOperand(1);

1408

1409

1412 return Result;

1413

1415}

1416

1419 switch (N->getOpcode()) {

1420 default:

1421 break;

1430 }

1431

1433}

1434

1439 switch (Op.getOpcode()) {

1440 default:

1441 break;

1442 case LanaiISD::SETCC:

1445 break;

1446 case LanaiISD::SELECT_CC:

1451 break;

1452 }

1453}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

This file implements a class to represent arbitrary precision integral constant values and operations...

static bool isZeroOrAllOnes(SDValue N, bool AllOnes)

static SDValue PerformSUBCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget)

PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.

static SDValue combineSelectAndUseCommutative(SDNode *N, bool AllOnes, TargetLowering::DAGCombinerInfo &DCI)

static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes, SDValue &CC, bool &Invert, SDValue &OtherOp, SelectionDAG &DAG)

static SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, TargetLowering::DAGCombinerInfo &DCI, bool AllOnes=false)

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

static LPCC::CondCode IntCondCCodeToICC(SDValue CC, const SDLoc &DL, SDValue &RHS, SelectionDAG &DAG)

Definition LanaiISelLowering.cpp:785

static cl::opt< int > LanaiLowerConstantMulThreshold("lanai-constant-mul-threshold", cl::Hidden, cl::desc("Maximum number of instruction to generate when lowering constant " "multiplication instead of calling library function [default=14]"), cl::init(14))

static bool CC_Lanai32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State)

Definition LanaiISelLowering.cpp:356

Promote Memory to Register

static CodeModel::Model getCodeModel(const PPCSubtarget &S, const TargetMachine &TM, const MachineOperand &MO)

static constexpr MCPhysReg SPReg

const SmallVectorImpl< MachineOperand > & Cond

This file defines the SmallVector class.

This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...

Class for arbitrary precision integers.

void setBits(unsigned loBit, unsigned hiBit)

Set the bits from loBit (inclusive) to hiBit (exclusive) to 1.

The address of a basic block.

CCState - This class holds information needed while lowering arguments and return values.

LLVM_ABI bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)

CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...

CCValAssign - Represent assignment of one arg/retval to a location.

LocInfo getLocInfo() const

static CCValAssign getMem(unsigned ValNo, MVT ValVT, int64_t Offset, MVT LocVT, LocInfo HTP, bool IsCustom=false)

int64_t getLocMemOffset() const

This is an important base class in LLVM.

bool hasStructRetAttr() const

Determine if the function returns a structure through first or second pointer argument.

LLVM_ABI const GlobalObject * getAliaseeObject() const

This is an important class for using LLVM in a threaded context.

void setVarArgsFrameIndex(int Index)

void setSRetReturnReg(Register Reg)

int getVarArgsFrameIndex() const

const LanaiRegisterInfo * getRegisterInfo() const override

SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const

Definition LanaiISelLowering.cpp:1073

SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const

Definition LanaiISelLowering.cpp:1156

SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const

Definition LanaiISelLowering.cpp:1031

SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const

Definition LanaiISelLowering.cpp:1232

SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const

Definition LanaiISelLowering.cpp:866

void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override

Determine which of the bits specified in Mask are known to be either zero or one and return them in t...

Definition LanaiISelLowering.cpp:1435

SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const

Definition LanaiISelLowering.cpp:1183

SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const

Definition LanaiISelLowering.cpp:850

LanaiTargetLowering(const TargetMachine &TM, const LanaiSubtarget &STI)

Definition LanaiISelLowering.cpp:71

SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const

Definition LanaiISelLowering.cpp:981

SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const

Definition LanaiISelLowering.cpp:1106

Return the register ID of the name passed in.

Definition LanaiISelLowering.cpp:206

SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const

Definition LanaiISelLowering.cpp:951

SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const

Definition LanaiISelLowering.cpp:964

SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const

Definition LanaiISelLowering.cpp:1054

SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const

Definition LanaiISelLowering.cpp:1140

bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context, const Type *RetTy) const override

This hook should be implemented to check whether the return values described by the Outs array can fi...

Definition LanaiISelLowering.cpp:519

ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &Info, const char *Constraint) const override

Examine constraint string and operand type and determine a weight value.

Definition LanaiISelLowering.cpp:243

void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override

Lower the specified operand into the Ops vector.

Definition LanaiISelLowering.cpp:272

SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const

Definition LanaiISelLowering.cpp:996

SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override

This method will be invoked for all target nodes and for any target-independent nodes that the target...

Definition LanaiISelLowering.cpp:1417

std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override

Given a physical register constraint (e.g.

Definition LanaiISelLowering.cpp:224

SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override

This callback is invoked for operations that are unsupported by the target, which are registered to u...

Definition LanaiISelLowering.cpp:166

bool isConstantInSmallSection(const DataLayout &DL, const Constant *CN) const

Return true if this constant should be placed into small data section.

static auto integer_valuetypes()

TypeSize getSizeInBits() const

Returns the size of the specified MVT in bits.

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

LLVM_ABI int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)

Create a new object at a fixed location on the stack.

uint64_t getStackSize() const

Return the number of bytes that must be allocated to hold all of the fixed size frame objects.

LLVM_ABI int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)

Create a new statically sized stack object, returning a nonnegative identifier to represent it.

void setFrameAddressIsTaken(bool T)

void setReturnAddressIsTaken(bool s)

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Function & getFunction()

Return the LLVM function that this machine code represents.

Ty * getInfo()

getInfo - Keep track of various per-function pieces of information for backends that would like to do...

addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...

LLVM_ABI Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")

createVirtualRegister - Create and return a new virtual register in the function with the specified r...

void addLiveIn(MCRegister Reg, Register vreg=Register())

addLiveIn - Add the specified register as a live-in.

Wrapper class representing virtual and physical registers.

Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...

Represents one node in the SelectionDAG.

bool hasOneUse() const

Return true if there is exactly one use of this node.

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.

SDNode * getNode() const

get the SDNode which holds the desired result

SDValue getValue(unsigned R) const

EVT getValueType() const

Return the ValueType of the referenced return value.

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...

SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)

SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, Register Reg, SDValue N)

LLVM_ABI SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)

Create a MERGE_VALUES node from the given operands.

LLVM_ABI SDVTList getVTList(EVT VT)

Return an SDVTList that represents the list of values specified.

LLVM_ABI SDValue getAllOnesConstant(const SDLoc &DL, EVT VT, bool IsTarget=false, bool IsOpaque=false)

SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)

Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...

LLVM_ABI SDValue getRegister(Register Reg, EVT VT)

LLVM_ABI SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)

Loads are not normal binary operators: their result type is not determined by their operands,...

LLVM_ABI SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, const CallInst *CI, std::optional< bool > OverrideTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), BatchAAResults *BatchAA=nullptr)

SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)

SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)

Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).

SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, Register Reg, EVT VT)

SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS, SDNodeFlags Flags=SDNodeFlags())

Helper function to make it easier to build Select's if you just have operands and don't want to check...

const DataLayout & getDataLayout() const

LLVM_ABI SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)

Create a ConstantSDNode wrapping a constant value.

LLVM_ABI SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())

Helper function to build ISD::STORE nodes.

SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)

Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...

LLVM_ABI SDValue getBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, bool isTarget=false, unsigned TargetFlags=0)

LLVM_ABI SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)

LLVM_ABI SDValue getValueType(EVT)

LLVM_ABI SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)

Gets or creates the specified node.

SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)

MachineFunction & getMachineFunction() const

LLVM_ABI SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)

LLVM_ABI KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const

Determine which bits of Op are known to be either zero or one and return them in Known.

LLVM_ABI SDValue getRegisterMask(const uint32_t *RegMask)

LLVMContext * getContext() const

LLVM_ABI SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)

SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)

SDValue getEntryNode() const

Return the token chain corresponding to the entry of the function.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StringRef - Represent a constant reference to a string, i.e.

constexpr size_t size() const

size - Get the string size.

A switch()-like statement whose cases are string literals.

StringSwitch & Case(StringLiteral S, T Value)

void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)

Indicate that the specified operation does not work with the specified type and indicate what to do a...

unsigned MaxStoresPerMemcpyOptSize

Likewise for functions with the OptSize attribute.

virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const

Return the register class that should be used for the specified value type.

const TargetMachine & getTargetMachine() const

void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)

Set the maximum atomic operation size supported by the backend.

If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...

void setMinFunctionAlignment(Align Alignment)

Set the target's minimum function alignment.

unsigned MaxStoresPerMemsetOptSize

Likewise for functions with the OptSize attribute.

void setBooleanContents(BooleanContent Ty)

Specify how the target extends the result of integer and floating point boolean values from i1 to a w...

unsigned MaxStoresPerMemmove

Specify maximum number of store instructions per memmove call.

void computeRegisterProperties(const TargetRegisterInfo *TRI)

Once all of the register classes are added, this allows us to compute derived properties we expose.

unsigned MaxStoresPerMemmoveOptSize

Likewise for functions with the OptSize attribute.

void addRegisterClass(MVT VT, const TargetRegisterClass *RC)

Add the specified register class as an available regclass for the specified value type.

virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const

Return the pointer type for the given address space, defaults to the pointer type from the data layou...

void setPrefFunctionAlignment(Align Alignment)

Set the target's preferred function alignment.

unsigned MaxStoresPerMemset

Specify maximum number of store instructions per memset call.

void setMinimumJumpTableEntries(unsigned Val)

Indicate the minimum number of blocks to generate jump tables.

@ ZeroOrOneBooleanContent

void setStackPointerRegisterToSaveRestore(Register R)

If set to a physical register, this specifies the register that llvm.savestack/llvm....

void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)

Targets should invoke this method for each target independent node that they want to provide a custom...

void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)

Indicate that the specified load with extension does not work with the specified type and indicate wh...

unsigned MaxStoresPerMemcpy

Specify maximum number of store instructions per memcpy call.

void setJumpIsExpensive(bool isExpensive=true)

Tells the code generator not to expand logic operations on comparison predicates into separate sequen...

virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const

Examine constraint string and operand type and determine a weight value.

virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const

Given a physical register constraint (e.g.

TargetLowering(const TargetLowering &)=delete

virtual void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const

Lower the specified operand into the Ops vector.

Primary interface to the complete machine description for the target machine.

virtual TargetLoweringObjectFile * getObjFileLowering() const

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

The instances of the Type class are immutable: once they are created, they are never changed.

LLVM Value Representation.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

constexpr char Align[]

Key for Kernel::Arg::Metadata::mAlign.

constexpr std::underlying_type_t< E > Mask()

Get a bitmask with 1s in all places up to the high-order bit of E's largest value.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ Fast

Attempts to make calls as fast as possible (e.g.

@ C

The default llvm calling convention, compatible with C.

@ SETCC

SetCC operator - This evaluates to a true value iff the condition is true.

@ SMUL_LOHI

SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...

@ BSWAP

Byte Swap and Counting operators.

@ ADD

Simple integer binary arithmetic operators.

@ ANY_EXTEND

ANY_EXTEND - Used for integer types. The high bits are undefined.

@ SDIVREM

SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.

@ SIGN_EXTEND

Conversion operators.

@ SELECT

Select(COND, TRUEVAL, FALSEVAL).

@ MULHU

MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...

@ SHL

Shift and rotation operations.

@ ZERO_EXTEND

ZERO_EXTEND - Used for integer types, zeroing the new bits.

@ SELECT_CC

Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...

@ SIGN_EXTEND_INREG

SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...

@ FRAMEADDR

FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.

@ AND

Bitwise operators - logical and, logical or, logical xor.

@ TokenFactor

TokenFactor - This node takes multiple tokens as input and produces a single token result.

@ TRUNCATE

TRUNCATE - Completely drop the high bits.

@ SHL_PARTS

SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.

@ AssertSext

AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...

CondCode

ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

constexpr bool isInt(int64_t x)

Checks if an integer fits into the given bit width.

LLVM_ABI bool isNullConstant(SDValue V)

Returns true if V is a constant integer zero.

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)

constexpr bool isUInt(uint64_t x)

Checks if an unsigned integer fits into the given bit width.

class LLVM_GSL_OWNER SmallVector

Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...

bool isa(const From &Val)

isa - Return true if the parameter to the template is an instance of one of the template type argu...

LLVM_ABI raw_fd_ostream & errs()

This returns a reference to a raw_ostream for standard error.

@ Sub

Subtraction of integers.

DWARFExpression::Operation Op

ArrayRef(const T &OneElt) -> ArrayRef< T >

constexpr unsigned BitWidth

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

LLVM_ABI bool isAllOnesConstant(SDValue V)

Returns true if V is an integer constant with all bits set.

void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)

Implement std::swap in terms of BitVector swap.

This struct is a compact representation of a valid (non-zero power of two) alignment.

TypeSize getSizeInBits() const

Return the size of the specified value type in bits.

MVT getSimpleVT() const

Return the SimpleValueType held in the specified simple EVT.

unsigned getBitWidth() const

Get the bit width of this value.

KnownBits intersectWith(const KnownBits &RHS) const

Returns KnownBits information that is known to be true for both this and RHS.

This class contains a discriminated union of information about pointers in memory operands,...

static LLVM_ABI MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)

Return a MachinePointerInfo record that refers to the specified FrameIndex.

This contains information for each constraint that we are lowering.

This structure contains all information that is necessary for lowering calls.

SmallVector< ISD::InputArg, 32 > Ins

SmallVector< ISD::OutputArg, 32 > Outs

SmallVector< SDValue, 32 > OutVals