LLVM: lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp File Reference (original) (raw)

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Macros
#define DEBUG_TYPE "legalizevectorops"
#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN)
#define BEGIN_REGISTER_VP_SDNODE(VPID, LEGALPOS, ...)
#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN)

◆ BEGIN_REGISTER_VP_SDNODE

#define BEGIN_REGISTER_VP_SDNODE ( VPID,
LEGALPOS,
... )

Value:

case ISD::VPID: { \

EVT LegalizeVT = LEGALPOS < 0 ? Node->getValueType(-(1 + LEGALPOS)) \

: Node->getOperand(LEGALPOS).getValueType(); \

if (ISD::VPID == ISD::VP_SETCC) { \

Action = TLI.getCondCodeAction(CCCode, LegalizeVT.getSimpleVT()); \

if (Action != TargetLowering::Legal) \

break; \

} \

\

if (Node->getValueType(0).isVector() && \

Node->getValueType(0) != MVT::Other) { \

Action = TargetLowering::Legal; \

break; \

} \

Action = TLI.getOperationAction(Node->getOpcode(), LegalizeVT); \

} break;

CondCode

ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...

NodeAddr< NodeBase * > Node

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

MVT getSimpleVT() const

Return the SimpleValueType held in the specified simple EVT.

◆ DAG_INSTRUCTION [1/2]

#define DAG_INSTRUCTION ( NAME,
NARG,
ROUND_MODE,
INTRINSIC,
DAGN )

◆ DAG_INSTRUCTION [2/2]

#define DAG_INSTRUCTION ( NAME,
NARG,
ROUND_MODE,
INTRINSIC,
DAGN )

◆ DEBUG_TYPE

#define DEBUG_TYPE "legalizevectorops"

◆ createBSWAPShuffleMask()