LegalizeVectorOps.cpp Source File (original) (raw)

44#include

45#include

46#include

47#include

49using namespace llvm;

51#define DEBUG_TYPE "legalizevectorops"

53namespace {

55class VectorLegalizer {

58 bool Changed = false;

67 LegalizedNodes.insert(std::make_pair(From, To));

69 if (From != To)

70 LegalizedNodes.insert(std::make_pair(To, To));

71 }

101

102

103

105

106

108

109

110

111

112

113

115

116

117

118

119

120

122

123

124

125

126

128

129

131

132

133

143 std::pair<SDValue, SDValue> ExpandLoad(SDNode *N);

157

158 bool tryExpandVecMathCall(SDNode *Node, RTLIB::Libcall LC,

160 bool tryExpandVecMathCall(SDNode *Node, RTLIB::Libcall Call_F32,

161 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,

162 RTLIB::Libcall Call_F128,

163 RTLIB::Libcall Call_PPCF128,

165

167

168

169

170

171

173

174

175

176

178

179

180

181

182

184

185

186

187

188

190

192

193

194

195

197 bool NonArithmetic);

198

199public:

202

203

204 bool Run();

205};

206

207}

208

209bool VectorLegalizer::Run() {

210

211 bool HasVectors = false;

214

215

216 HasVectors = llvm::any_of(I->values(), [](EVT T) { return T.isVector(); });

217

218

219 if (HasVectors)

220 break;

221 }

222

223

224 if (!HasVectors)

225 return false;

226

227

228

229

230

231

232

237

238

240 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");

241 DAG.setRoot(LegalizedNodes[OldRoot]);

242

243 LegalizedNodes.clear();

244

245

247

249}

250

251SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDNode *Result) {

252 assert(Op->getNumValues() == Result->getNumValues() &&

253 "Unexpected number of results");

254

255 for (unsigned i = 0, e = Op->getNumValues(); i != e; ++i)

256 AddLegalizedOperand(Op.getValue(i), SDValue(Result, i));

257 return SDValue(Result, Op.getResNo());

258}

259

261VectorLegalizer::RecursivelyLegalizeResults(SDValue Op,

264 "Unexpected number of results");

265

266 for (unsigned i = 0, e = Results.size(); i != e; ++i) {

268 AddLegalizedOperand(Op.getValue(i), Results[i]);

269 }

270

272}

273

275

276

277 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);

278 if (I != LegalizedNodes.end()) return I->second;

279

280

282 for (const SDValue &Oper : Op->op_values())

283 Ops.push_back(LegalizeOp(Oper));

284

286

287 bool HasVectorValueOrOp =

288 llvm::any_of(Node->values(), [](EVT T) { return T.isVector(); }) ||

290 [](SDValue O) { return O.getValueType().isVector(); });

291 if (!HasVectorValueOrOp)

292 return TranslateLegalizeResults(Op, Node);

293

294 TargetLowering::LegalizeAction Action = TargetLowering::Legal;

295 EVT ValVT;

296 switch (Op.getOpcode()) {

297 default:

298 return TranslateLegalizeResults(Op, Node);

299 case ISD::LOAD: {

302 EVT LoadedVT = LD->getMemoryVT();

304 Action = TLI.getLoadExtAction(ExtType, LD->getValueType(0), LoadedVT);

305 break;

306 }

307 case ISD::STORE: {

309 EVT StVT = ST->getMemoryVT();

310 MVT ValVT = ST->getValue().getSimpleValueType();

311 if (StVT.isVector() && ST->isTruncatingStore())

313 break;

314 }

317

318

319 if (Action == TargetLowering::Legal)

320 Action = TargetLowering::Expand;

321 break;

322#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \

323 case ISD::STRICT_##DAGN:

324#include "llvm/IR/ConstrainedOps.def"

325 ValVT = Node->getValueType(0);

328 ValVT = Node->getOperand(1).getValueType();

331 MVT OpVT = Node->getOperand(1).getSimpleValueType();

334 if (Action == TargetLowering::Legal)

336 } else {

338 }

339

340

341

342

343

344 if (Action == TargetLowering::Expand && !TLI.isStrictFPEnabled() &&

346 TargetLowering::Legal) {

349 == TargetLowering::Expand &&

351 == TargetLowering::Legal)

352 Action = TargetLowering::Legal;

353 }

354 break;

404 case ISD::FNEG:

405 case ISD::FABS:

406 case ISD::FMINNUM:

407 case ISD::FMAXNUM:

408 case ISD::FMINNUM_IEEE:

409 case ISD::FMAXNUM_IEEE:

410 case ISD::FMINIMUM:

411 case ISD::FMAXIMUM:

412 case ISD::FMINIMUMNUM:

413 case ISD::FMAXIMUMNUM:

415 case ISD::FSQRT:

416 case ISD::FSIN:

417 case ISD::FCOS:

418 case ISD::FTAN:

419 case ISD::FASIN:

420 case ISD::FACOS:

421 case ISD::FATAN:

422 case ISD::FATAN2:

423 case ISD::FSINH:

424 case ISD::FCOSH:

425 case ISD::FTANH:

426 case ISD::FLDEXP:

427 case ISD::FPOWI:

428 case ISD::FPOW:

429 case ISD::FLOG:

430 case ISD::FLOG2:

431 case ISD::FLOG10:

432 case ISD::FEXP:

433 case ISD::FEXP2:

434 case ISD::FEXP10:

435 case ISD::FCEIL:

436 case ISD::FTRUNC:

437 case ISD::FRINT:

438 case ISD::FNEARBYINT:

439 case ISD::FROUND:

440 case ISD::FROUNDEVEN:

441 case ISD::FFLOOR:

443 case ISD::FP_EXTEND:

463 case ISD::FFREXP:

464 case ISD::FMODF:

465 case ISD::FSINCOS:

466 case ISD::FSINCOSPI:

475 case ISD::MGATHER:

482 break;

491 unsigned Scale = Node->getConstantOperandVal(2);

493 Node->getValueType(0), Scale);

494 break;

495 }

496 case ISD::LROUND:

497 case ISD::LLROUND:

498 case ISD::LRINT:

499 case ISD::LLRINT:

502 case ISD::VECREDUCE_ADD:

503 case ISD::VECREDUCE_MUL:

504 case ISD::VECREDUCE_AND:

505 case ISD::VECREDUCE_OR:

506 case ISD::VECREDUCE_XOR:

507 case ISD::VECREDUCE_SMAX:

508 case ISD::VECREDUCE_SMIN:

509 case ISD::VECREDUCE_UMAX:

510 case ISD::VECREDUCE_UMIN:

511 case ISD::VECREDUCE_FADD:

512 case ISD::VECREDUCE_FMAX:

513 case ISD::VECREDUCE_FMAXIMUM:

514 case ISD::VECREDUCE_FMIN:

515 case ISD::VECREDUCE_FMINIMUM:

516 case ISD::VECREDUCE_FMUL:

517 case ISD::VECTOR_FIND_LAST_ACTIVE:

519 Node->getOperand(0).getValueType());

520 break;

521 case ISD::VECREDUCE_SEQ_FADD:

522 case ISD::VECREDUCE_SEQ_FMUL:

524 Node->getOperand(1).getValueType());

525 break;

527 MVT OpVT = Node->getOperand(0).getSimpleValueType();

530 if (Action == TargetLowering::Legal)

532 break;

533 }

534 case ISD::PARTIAL_REDUCE_UMLA:

535 case ISD::PARTIAL_REDUCE_SMLA:

536 case ISD::PARTIAL_REDUCE_SUMLA:

537 case ISD::PARTIAL_REDUCE_FMLA:

538 Action =

540 Node->getOperand(1).getValueType());

541 break;

542

543#define BEGIN_REGISTER_VP_SDNODE(VPID, LEGALPOS, ...) \

544 case ISD::VPID: { \

545 EVT LegalizeVT = LEGALPOS < 0 ? Node->getValueType(-(1 + LEGALPOS)) \

546 : Node->getOperand(LEGALPOS).getValueType(); \

547 if (ISD::VPID == ISD::VP_SETCC) { \

548 ISD::CondCode CCCode = cast(Node->getOperand(2))->get(); \

549 Action = TLI.getCondCodeAction(CCCode, LegalizeVT.getSimpleVT()); \

550 if (Action != TargetLowering::Legal) \

551 break; \

552 } \

553 \

554 if (!Node->getValueType(0).isVector() && \

555 Node->getValueType(0) != MVT::Other) { \

556 Action = TargetLowering::Legal; \

557 break; \

558 } \

559 Action = TLI.getOperationAction(Node->getOpcode(), LegalizeVT); \

560 } break;

561#include "llvm/IR/VPIntrinsics.def"

562 }

563

565

567 switch (Action) {

568 default: llvm_unreachable("This action is not supported yet!");

569 case TargetLowering::Promote:

570 assert((Op.getOpcode() != ISD::LOAD && Op.getOpcode() != ISD::STORE) &&

571 "This action is not supported yet!");

573 Promote(Node, ResultVals);

574 assert(!ResultVals.empty() && "No results for promotion?");

575 break;

576 case TargetLowering::Legal:

578 break;

579 case TargetLowering::Custom:

580 LLVM_DEBUG(dbgs() << "Trying custom legalization\n");

581 if (LowerOperationWrapper(Node, ResultVals))

582 break;

583 LLVM_DEBUG(dbgs() << "Could not custom legalize node\n");

584 [[fallthrough]];

585 case TargetLowering::Expand:

587 Expand(Node, ResultVals);

588 break;

589 }

590

591 if (ResultVals.empty())

592 return TranslateLegalizeResults(Op, Node);

593

595 return RecursivelyLegalizeResults(Op, ResultVals);

596}

597

598

599

600bool VectorLegalizer::LowerOperationWrapper(SDNode *Node,

601 SmallVectorImpl &Results) {

603

605 return false;

606

607 if (Res == SDValue(Node, 0))

608 return true;

609

610

611

612 if (Node->getNumValues() == 1) {

614 return true;

615 }

616

617

618

620 "Lowering returned the wrong number of results!");

621

622

623 for (unsigned I = 0, E = Node->getNumValues(); I != E; ++I)

625

626 return true;

627}

628

629void VectorLegalizer::PromoteSETCC(SDNode *Node,

630 SmallVectorImpl &Results) {

631 MVT VecVT = Node->getOperand(0).getSimpleValueType();

633

635

636 SDLoc DL(Node);

638

639 Operands[0] = DAG.getNode(ExtOp, DL, NewVecVT, Node->getOperand(0));

640 Operands[1] = DAG.getNode(ExtOp, DL, NewVecVT, Node->getOperand(1));

641 Operands[2] = Node->getOperand(2);

642

643 if (Node->getOpcode() == ISD::VP_SETCC) {

644 Operands[3] = Node->getOperand(3);

645 Operands[4] = Node->getOperand(4);

646 }

647

649 Operands, Node->getFlags());

650

652}

653

654void VectorLegalizer::PromoteSTRICT(SDNode *Node,

655 SmallVectorImpl &Results) {

656 MVT VecVT = Node->getOperand(1).getSimpleValueType();

658

660

661 SDLoc DL(Node);

664

665 for (unsigned j = 1; j != Node->getNumOperands(); ++j)

666 if (Node->getOperand(j).getValueType().isVector() &&

669 {

670

673 {Node->getOperand(0), Node->getOperand(j)});

676 } else

677 Operands[j] = Node->getOperand(j);

678

679 SDVTList VTs = DAG.getVTList(NewVecVT, Node->getValueType(1));

680

682

684 DAG.getNode(Node->getOpcode(), DL, VTs, Operands, Node->getFlags());

685

690

693}

694

695void VectorLegalizer::PromoteFloatVECREDUCE(SDNode *Node,

696 SmallVectorImpl &Results,

697 bool NonArithmetic) {

698 MVT OpVT = Node->getOperand(0).getSimpleValueType();

701

702 SDLoc DL(Node);

703 SDValue NewOp = DAG.getNode(ISD::FP_EXTEND, DL, NewOpVT, Node->getOperand(0));

706 Node->getFlags());

711}

712

713void VectorLegalizer::Promote(SDNode *Node, SmallVectorImpl &Results) {

714

715

716 switch (Node->getOpcode()) {

721

722 PromoteINT_TO_FP(Node, Results);

723 return;

728

729 PromoteFP_TO_INT(Node, Results);

730 return;

731 case ISD::VP_SETCC:

733

734 PromoteSETCC(Node, Results);

735 return;

742 PromoteSTRICT(Node, Results);

743 return;

744 case ISD::VECREDUCE_FADD:

745 PromoteFloatVECREDUCE(Node, Results, false);

746 return;

747 case ISD::VECREDUCE_FMAX:

748 case ISD::VECREDUCE_FMAXIMUM:

749 case ISD::VECREDUCE_FMIN:

750 case ISD::VECREDUCE_FMINIMUM:

751 PromoteFloatVECREDUCE(Node, Results, true);

752 return;

754 case ISD::FP_EXTEND:

755

756

757 llvm_unreachable("Don't know how to promote this operation!");

758 case ISD::VP_FABS:

759 case ISD::VP_FCOPYSIGN:

760 case ISD::VP_FNEG:

761

763 }

764

765

766

767

768

769

771 "Can't promote a vector with multiple results!");

772 MVT VT = Node->getSimpleValueType(0);

774 SDLoc dl(Node);

776

777 for (unsigned j = 0; j != Node->getNumOperands(); ++j) {

778

781 if (Node->getOperand(j).getValueType().isVector() && !SkipPromote)

782 if (Node->getOperand(j)

783 .getValueType()

784 .getVectorElementType()

785 .isFloatingPoint() &&

788 unsigned EVLIdx =

791 Operands[j] =

792 DAG.getNode(ISD::VP_FP_EXTEND, dl, NVT, Node->getOperand(j),

793 Node->getOperand(MaskIdx), Node->getOperand(EVLIdx));

794 } else {

795 Operands[j] =

796 DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(j));

797 }

798 else

799 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(j));

800 else

801 Operands[j] = Node->getOperand(j);

802 }

803

805 DAG.getNode(Node->getOpcode(), dl, NVT, Operands, Node->getFlags());

806

813 Res = DAG.getNode(ISD::VP_FP_ROUND, dl, VT, Res,

814 Node->getOperand(MaskIdx), Node->getOperand(EVLIdx));

815 } else {

818 }

819 else

820 Res = DAG.getNode(ISD::BITCAST, dl, VT, Res);

821

823}

824

825void VectorLegalizer::PromoteINT_TO_FP(SDNode *Node,

826 SmallVectorImpl &Results) {

827

828

829 bool IsStrict = Node->isStrictFPOpcode();

830 MVT VT = Node->getOperand(IsStrict ? 1 : 0).getSimpleValueType();

833 "Vectors have different number of elements!");

834

835 SDLoc dl(Node);

837

842 for (unsigned j = 0; j != Node->getNumOperands(); ++j) {

843 if (Node->getOperand(j).getValueType().isVector())

844 Operands[j] = DAG.getNode(Opc, dl, NVT, Node->getOperand(j));

845 else

846 Operands[j] = Node->getOperand(j);

847 }

848

849 if (IsStrict) {

851 {Node->getValueType(0), MVT::Other}, Operands);

854 return;

855 }

856

858 DAG.getNode(Node->getOpcode(), dl, Node->getValueType(0), Operands);

860}

861

862

863

864

865

866void VectorLegalizer::PromoteFP_TO_INT(SDNode *Node,

867 SmallVectorImpl &Results) {

868 MVT VT = Node->getSimpleValueType(0);

870 bool IsStrict = Node->isStrictFPOpcode();

872 "Vectors have different number of elements!");

873

874 unsigned NewOpc = Node->getOpcode();

875

876

880

884

885 SDLoc dl(Node);

887 if (IsStrict) {

888 Promoted = DAG.getNode(NewOpc, dl, {NVT, MVT::Other},

889 {Node->getOperand(0), Node->getOperand(1)});

890 Chain = Promoted.getValue(1);

891 } else

892 Promoted = DAG.getNode(NewOpc, dl, NVT, Node->getOperand(0));

893

894

895

896

900 else

902

903 Promoted = DAG.getNode(NewOpc, dl, NVT, Promoted,

906 Results.push_back(Promoted);

907 if (IsStrict)

908 Results.push_back(Chain);

909}

910

911std::pair<SDValue, SDValue> VectorLegalizer::ExpandLoad(SDNode *N) {

914}

915

916SDValue VectorLegalizer::ExpandStore(SDNode *N) {

919 return TF;

920}

921

922void VectorLegalizer::Expand(SDNode *Node, SmallVectorImpl &Results) {

923 switch (Node->getOpcode()) {

924 case ISD::LOAD: {

925 std::pair<SDValue, SDValue> Tmp = ExpandLoad(Node);

926 Results.push_back(Tmp.first);

927 Results.push_back(Tmp.second);

928 return;

929 }

930 case ISD::STORE:

931 Results.push_back(ExpandStore(Node));

932 return;

934 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)

936 return;

938 if (SDValue Expanded = ExpandSEXTINREG(Node)) {

939 Results.push_back(Expanded);

940 return;

941 }

942 break;

944 Results.push_back(ExpandANY_EXTEND_VECTOR_INREG(Node));

945 return;

947 Results.push_back(ExpandSIGN_EXTEND_VECTOR_INREG(Node));

948 return;

950 Results.push_back(ExpandZERO_EXTEND_VECTOR_INREG(Node));

951 return;

953 if (SDValue Expanded = ExpandBSWAP(Node)) {

954 Results.push_back(Expanded);

955 return;

956 }

957 break;

958 case ISD::VP_BSWAP:

960 return;

962 if (SDValue Expanded = ExpandVSELECT(Node)) {

963 Results.push_back(Expanded);

964 return;

965 }

966 break;

967 case ISD::VP_SELECT:

968 if (SDValue Expanded = ExpandVP_SELECT(Node)) {

969 Results.push_back(Expanded);

970 return;

971 }

972 break;

973 case ISD::VP_SREM:

974 case ISD::VP_UREM:

975 if (SDValue Expanded = ExpandVP_REM(Node)) {

976 Results.push_back(Expanded);

977 return;

978 }

979 break;

980 case ISD::VP_FNEG:

981 if (SDValue Expanded = ExpandVP_FNEG(Node)) {

982 Results.push_back(Expanded);

983 return;

984 }

985 break;

986 case ISD::VP_FABS:

987 if (SDValue Expanded = ExpandVP_FABS(Node)) {

988 Results.push_back(Expanded);

989 return;

990 }

991 break;

992 case ISD::VP_FCOPYSIGN:

993 if (SDValue Expanded = ExpandVP_FCOPYSIGN(Node)) {

994 Results.push_back(Expanded);

995 return;

996 }

997 break;

999 if (SDValue Expanded = ExpandSELECT(Node)) {

1000 Results.push_back(Expanded);

1001 return;

1002 }

1003 break;

1005 if (Node->getValueType(0).isScalableVector()) {

1010 Node->getOperand(1), Node->getOperand(4));

1012 Node->getOperand(2),

1013 Node->getOperand(3)));

1014 return;

1015 }

1016 break;

1017 }

1019 ExpandFP_TO_UINT(Node, Results);

1020 return;

1022 ExpandUINT_TO_FLOAT(Node, Results);

1023 return;

1024 case ISD::FNEG:

1025 if (SDValue Expanded = ExpandFNEG(Node)) {

1026 Results.push_back(Expanded);

1027 return;

1028 }

1029 break;

1030 case ISD::FABS:

1031 if (SDValue Expanded = ExpandFABS(Node)) {

1032 Results.push_back(Expanded);

1033 return;

1034 }

1035 break;

1037 if (SDValue Expanded = ExpandFCOPYSIGN(Node)) {

1038 Results.push_back(Expanded);

1039 return;

1040 }

1041 break;

1043 ExpandFSUB(Node, Results);

1044 return;

1046 case ISD::VP_SETCC:

1047 ExpandSETCC(Node, Results);

1048 return;

1051 Results.push_back(Expanded);

1052 return;

1053 }

1054 break;

1058 Results.push_back(Expanded);

1059 return;

1060 }

1061 break;

1067 Results.push_back(Expanded);

1068 return;

1069 }

1070 break;

1072 if (SDValue Expanded = ExpandBITREVERSE(Node)) {

1073 Results.push_back(Expanded);

1074 return;

1075 }

1076 break;

1077 case ISD::VP_BITREVERSE:

1079 Results.push_back(Expanded);

1080 return;

1081 }

1082 break;

1085 Results.push_back(Expanded);

1086 return;

1087 }

1088 break;

1089 case ISD::VP_CTPOP:

1091 Results.push_back(Expanded);

1092 return;

1093 }

1094 break;

1098 Results.push_back(Expanded);

1099 return;

1100 }

1101 break;

1102 case ISD::VP_CTLZ:

1103 case ISD::VP_CTLZ_ZERO_UNDEF:

1105 Results.push_back(Expanded);

1106 return;

1107 }

1108 break;

1112 Results.push_back(Expanded);

1113 return;

1114 }

1115 break;

1116 case ISD::VP_CTTZ:

1117 case ISD::VP_CTTZ_ZERO_UNDEF:

1119 Results.push_back(Expanded);

1120 return;

1121 }

1122 break;

1124 case ISD::VP_FSHL:

1126 case ISD::VP_FSHR:

1128 Results.push_back(Expanded);

1129 return;

1130 }

1131 break;

1134 if (SDValue Expanded = TLI.expandROT(Node, false , DAG)) {

1135 Results.push_back(Expanded);

1136 return;

1137 }

1138 break;

1139 case ISD::FMINNUM:

1140 case ISD::FMAXNUM:

1142 Results.push_back(Expanded);

1143 return;

1144 }

1145 break;

1146 case ISD::FMINIMUM:

1147 case ISD::FMAXIMUM:

1149 return;

1150 case ISD::FMINIMUMNUM:

1151 case ISD::FMAXIMUMNUM:

1153 return;

1159 Results.push_back(Expanded);

1160 return;

1161 }

1162 break;

1165 ExpandUADDSUBO(Node, Results);

1166 return;

1169 ExpandSADDSUBO(Node, Results);

1170 return;

1173 ExpandMULO(Node, Results);

1174 return;

1180 Results.push_back(Expanded);

1181 return;

1182 }

1183 break;

1187 Results.push_back(Expanded);

1188 return;

1189 }

1190 break;

1193

1194 if (Node->getValueType(0).isScalableVector()) {

1196 Results.push_back(Expanded);

1197 return;

1198 }

1199 }

1200 break;

1204 Results.push_back(Expanded);

1205 return;

1206 }

1207 break;

1210

1211

1212

1213

1214 break;

1217 ExpandFixedPointDiv(Node, Results);

1218 return;

1221 break;

1222#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \

1223 case ISD::STRICT_##DAGN:

1224#include "llvm/IR/ConstrainedOps.def"

1225 ExpandStrictFPOp(Node, Results);

1226 return;

1227 case ISD::VECREDUCE_ADD:

1228 case ISD::VECREDUCE_MUL:

1229 case ISD::VECREDUCE_AND:

1230 case ISD::VECREDUCE_OR:

1231 case ISD::VECREDUCE_XOR:

1232 case ISD::VECREDUCE_SMAX:

1233 case ISD::VECREDUCE_SMIN:

1234 case ISD::VECREDUCE_UMAX:

1235 case ISD::VECREDUCE_UMIN:

1236 case ISD::VECREDUCE_FADD:

1237 case ISD::VECREDUCE_FMUL:

1238 case ISD::VECREDUCE_FMAX:

1239 case ISD::VECREDUCE_FMIN:

1240 case ISD::VECREDUCE_FMAXIMUM:

1241 case ISD::VECREDUCE_FMINIMUM:

1243 return;

1244 case ISD::PARTIAL_REDUCE_UMLA:

1245 case ISD::PARTIAL_REDUCE_SMLA:

1246 case ISD::PARTIAL_REDUCE_SUMLA:

1247 case ISD::PARTIAL_REDUCE_FMLA:

1249 return;

1250 case ISD::VECREDUCE_SEQ_FADD:

1251 case ISD::VECREDUCE_SEQ_FMUL:

1253 return;

1256 ExpandREM(Node, Results);

1257 return;

1258 case ISD::VP_MERGE:

1259 if (SDValue Expanded = ExpandVP_MERGE(Node)) {

1260 Results.push_back(Expanded);

1261 return;

1262 }

1263 break;

1265 if (tryExpandVecMathCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,

1266 RTLIB::REM_F80, RTLIB::REM_F128,

1267 RTLIB::REM_PPCF128, Results))

1268 return;

1269

1270 break;

1271 case ISD::FSINCOS:

1272 case ISD::FSINCOSPI: {

1273 EVT VT = Node->getValueType(0);

1274 RTLIB::Libcall LC = Node->getOpcode() == ISD::FSINCOS

1277 if (LC != RTLIB::UNKNOWN_LIBCALL &&

1279 return;

1280

1281

1282

1283 break;

1284 }

1285 case ISD::FMODF: {

1286 EVT VT = Node->getValueType(0);

1288 if (LC != RTLIB::UNKNOWN_LIBCALL &&

1290 0))

1291 return;

1292 break;

1293 }

1296 return;

1297 case ISD::VECTOR_FIND_LAST_ACTIVE:

1299 return;

1303 return;

1306 Results.push_back(ExpandLOOP_DEPENDENCE_MASK(Node));

1307 return;

1308

1313 case ISD::FCEIL:

1314 case ISD::FFLOOR:

1315 case ISD::FNEARBYINT:

1316 case ISD::FRINT:

1317 case ISD::FROUND:

1318 case ISD::FROUNDEVEN:

1319 case ISD::FTRUNC:

1320 case ISD::FSQRT:

1322 Results.push_back(Expanded);

1323 return;

1324 }

1325 break;

1326 }

1327

1329 if (Node->getNumValues() == 1) {

1330 Results.push_back(Unrolled);

1331 } else {

1333 "VectorLegalizer Expand returned wrong number of results!");

1336 }

1337}

1338

1339SDValue VectorLegalizer::ExpandSELECT(SDNode *Node) {

1340

1341

1342

1343 EVT VT = Node->getValueType(0);

1344 SDLoc DL(Node);

1345

1349

1352

1353

1354

1355

1356

1357

1358

1359

1360

1366 VT) == TargetLowering::Expand)

1368

1369

1371

1372

1374

1377

1378

1380

1381

1382

1383

1384 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);

1385 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);

1386

1388

1392 return DAG.getNode(ISD::BITCAST, DL, Node->getValueType(0), Val);

1393}

1394

1395SDValue VectorLegalizer::ExpandSEXTINREG(SDNode *Node) {

1396 EVT VT = Node->getValueType(0);

1397

1398

1402

1403 SDLoc DL(Node);

1405

1409

1412}

1413

1414

1415

1416SDValue VectorLegalizer::ExpandANY_EXTEND_VECTOR_INREG(SDNode *Node) {

1417 SDLoc DL(Node);

1418 EVT VT = Node->getValueType(0);

1421 EVT SrcVT = Src.getValueType();

1423

1424

1425

1426 if (SrcVT.bitsLE(VT)) {

1428 "ANY_EXTEND_VECTOR_INREG vector size mismatch");

1431 NumSrcElements);

1433 }

1434

1435

1436 SmallVector<int, 16> ShuffleMask;

1437 ShuffleMask.resize(NumSrcElements, -1);

1438

1439

1440 int ExtLaneScale = NumSrcElements / NumElements;

1442 for (int i = 0; i < NumElements; ++i)

1443 ShuffleMask[i * ExtLaneScale + EndianOffset] = i;

1444

1446 ISD::BITCAST, DL, VT,

1448}

1449

1450SDValue VectorLegalizer::ExpandSIGN_EXTEND_VECTOR_INREG(SDNode *Node) {

1451 SDLoc DL(Node);

1452 EVT VT = Node->getValueType(0);

1454 EVT SrcVT = Src.getValueType();

1455

1456

1457

1459

1460

1461

1462

1468 ShiftAmount);

1469}

1470

1471

1472

1473

1474SDValue VectorLegalizer::ExpandZERO_EXTEND_VECTOR_INREG(SDNode *Node) {

1475 SDLoc DL(Node);

1476 EVT VT = Node->getValueType(0);

1479 EVT SrcVT = Src.getValueType();

1481

1482

1483

1484 if (SrcVT.bitsLE(VT)) {

1486 "ZERO_EXTEND_VECTOR_INREG vector size mismatch");

1489 NumSrcElements);

1491 }

1492

1493

1495

1496

1497

1499

1500 int ExtLaneScale = NumSrcElements / NumElements;

1502 for (int i = 0; i < NumElements; ++i)

1503 ShuffleMask[i * ExtLaneScale + EndianOffset] = NumSrcElements + i;

1504

1505 return DAG.getNode(ISD::BITCAST, DL, VT,

1507}

1508

1512 for (int J = ScalarSizeInBytes - 1; J >= 0; --J)

1513 ShuffleMask.push_back((I * ScalarSizeInBytes) + J);

1514}

1515

1516SDValue VectorLegalizer::ExpandBSWAP(SDNode *Node) {

1517 EVT VT = Node->getValueType(0);

1518

1519

1522

1523

1524 SmallVector<int, 16> ShuffleMask;

1527

1528

1530 SDLoc DL(Node);

1533 return DAG.getNode(ISD::BITCAST, DL, VT, Op);

1534 }

1535

1536

1537

1543

1544

1546}

1547

1548SDValue VectorLegalizer::ExpandBITREVERSE(SDNode *Node) {

1549 EVT VT = Node->getValueType(0);

1550

1551

1554

1555

1558

1559

1560

1561

1563 if (ScalarSizeInBits > 8 && (ScalarSizeInBits % 8) == 0) {

1564 SmallVector<int, 16> BSWAPMask;

1566

1574 SDLoc DL(Node);

1577 BSWAPMask);

1580 return Op;

1581 }

1582 }

1583

1584

1585

1591

1592

1594}

1595

1596SDValue VectorLegalizer::ExpandVSELECT(SDNode *Node) {

1597

1598

1599 SDLoc DL(Node);

1600

1604

1605 EVT VT = Mask.getValueType();

1606

1607

1608

1609

1610

1615

1616

1617

1618

1619

1621 if (BoolContents != TargetLowering::ZeroOrNegativeOneBooleanContent &&

1622 !(BoolContents == TargetLowering::ZeroOrOneBooleanContent &&

1625

1626

1627

1628

1631

1632

1633

1634

1635 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);

1636 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);

1637

1639

1643 return DAG.getNode(ISD::BITCAST, DL, Node->getValueType(0), Val);

1644}

1645

1646SDValue VectorLegalizer::ExpandVP_SELECT(SDNode *Node) {

1647

1648

1649 SDLoc DL(Node);

1650

1655

1656 EVT VT = Mask.getValueType();

1657

1658

1659

1660 if (TLI.getOperationAction(ISD::VP_AND, VT) == TargetLowering::Expand ||

1661 TLI.getOperationAction(ISD::VP_XOR, VT) == TargetLowering::Expand ||

1664

1665

1668

1670 SDValue NotMask = DAG.getNode(ISD::VP_XOR, DL, VT, Mask, Ones, Ones, EVL);

1671

1672 Op1 = DAG.getNode(ISD::VP_AND, DL, VT, Op1, Mask, Ones, EVL);

1673 Op2 = DAG.getNode(ISD::VP_AND, DL, VT, Op2, NotMask, Ones, EVL);

1674 return DAG.getNode(ISD::VP_OR, DL, VT, Op1, Op2, Ones, EVL);

1675}

1676

1677SDValue VectorLegalizer::ExpandVP_MERGE(SDNode *Node) {

1678

1679

1680

1681

1682 SDLoc DL(Node);

1683

1688

1689 EVT MaskVT = Mask.getValueType();

1691

1694

1695

1696 if ((IsFixedLen &&

1698 (!IsFixedLen &&

1702

1703

1704

1706 EVLVecVT) != MaskVT)

1708

1712 DAG.getSetCC(DL, MaskVT, StepVec, SplatEVL, ISD::CondCode::SETULT);

1713

1715 return DAG.getSelect(DL, Node->getValueType(0), FullMask, Op1, Op2);

1716}

1717

1718SDValue VectorLegalizer::ExpandVP_REM(SDNode *Node) {

1719

1720 EVT VT = Node->getValueType(0);

1721

1722 unsigned DivOpc = Node->getOpcode() == ISD::VP_SREM ? ISD::VP_SDIV : ISD::VP_UDIV;

1723

1728

1729 SDLoc DL(Node);

1730

1735

1736

1737 SDValue Div = DAG.getNode(DivOpc, DL, VT, Dividend, Divisor, Mask, EVL);

1738 SDValue Mul = DAG.getNode(ISD::VP_MUL, DL, VT, Divisor, Div, Mask, EVL);

1739 return DAG.getNode(ISD::VP_SUB, DL, VT, Dividend, Mul, Mask, EVL);

1740}

1741

1742SDValue VectorLegalizer::ExpandVP_FNEG(SDNode *Node) {

1743 EVT VT = Node->getValueType(0);

1745

1748

1751

1752 SDLoc DL(Node);

1756 SDValue Xor = DAG.getNode(ISD::VP_XOR, DL, IntVT, Cast, SignMask, Mask, EVL);

1757 return DAG.getNode(ISD::BITCAST, DL, VT, Xor);

1758}

1759

1760SDValue VectorLegalizer::ExpandVP_FABS(SDNode *Node) {

1761 EVT VT = Node->getValueType(0);

1763

1766

1769

1770 SDLoc DL(Node);

1775 DAG.getNode(ISD::VP_AND, DL, IntVT, Cast, ClearSignMask, Mask, EVL);

1776 return DAG.getNode(ISD::BITCAST, DL, VT, ClearSign);

1777}

1778

1779SDValue VectorLegalizer::ExpandVP_FCOPYSIGN(SDNode *Node) {

1780 EVT VT = Node->getValueType(0);

1781

1782 if (VT != Node->getOperand(1).getValueType())

1784

1789

1792

1793 SDLoc DL(Node);

1796

1800 DAG.getNode(ISD::VP_AND, DL, IntVT, Sign, SignMask, Mask, EVL);

1801

1805 DAG.getNode(ISD::VP_AND, DL, IntVT, Mag, ClearSignMask, Mask, EVL);

1806

1807 SDValue CopiedSign = DAG.getNode(ISD::VP_OR, DL, IntVT, ClearedSign, SignBit,

1809

1810 return DAG.getNode(ISD::BITCAST, DL, VT, CopiedSign);

1811}

1812

1813SDValue VectorLegalizer::ExpandLOOP_DEPENDENCE_MASK(SDNode *N) {

1814 SDLoc DL(N);

1815 SDValue SourceValue = N->getOperand(0);

1816 SDValue SinkValue = N->getOperand(1);

1817 SDValue EltSize = N->getOperand(2);

1818

1820 EVT VT = N->getValueType(0);

1822

1824 if (IsReadAfterWrite)

1826

1828

1829

1835

1836

1842 DAG.getSetCC(DL, MaskVT, VectorStep, DiffSplat, ISD::CondCode::SETULT);

1843

1845

1846

1849

1850

1855}

1856

1857void VectorLegalizer::ExpandFP_TO_UINT(SDNode *Node,

1858 SmallVectorImpl &Results) {

1859

1862 Results.push_back(Result);

1863 if (Node->isStrictFPOpcode())

1864 Results.push_back(Chain);

1865 return;

1866 }

1867

1868

1869 if (Node->isStrictFPOpcode()) {

1870 UnrollStrictFPOp(Node, Results);

1871 return;

1872 }

1873

1875}

1876

1877void VectorLegalizer::ExpandUINT_TO_FLOAT(SDNode *Node,

1878 SmallVectorImpl &Results) {

1879 bool IsStrict = Node->isStrictFPOpcode();

1880 unsigned OpNo = IsStrict ? 1 : 0;

1882 EVT SrcVT = Src.getValueType();

1883 EVT DstVT = Node->getValueType(0);

1884 SDLoc DL(Node);

1885

1886

1890 Results.push_back(Result);

1891 if (IsStrict)

1892 Results.push_back(Chain);

1893 return;

1894 }

1895

1896

1898 TargetLowering::Expand) ||

1900 TargetLowering::Expand)) ||

1902 if (IsStrict) {

1903 UnrollStrictFPOp(Node, Results);

1904 return;

1905 }

1906

1908 return;

1909 }

1910

1912 assert((BW == 64 || BW == 32) &&

1913 "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide");

1914

1915

1916

1919 EVT FPVT = BW == 32 ? MVT::f32 : MVT::f64;

1924 if (IsStrict) {

1926 {Node->getOperand(0), Src});

1928 {Node->getOperand(0), UIToFP, TargetZero});

1929 Results.push_back(Result);

1931 } else {

1934 Results.push_back(Result);

1935 }

1936

1937 return;

1938 }

1939

1941

1942

1943

1944

1945 uint64_t HWMask = (BW == 64) ? 0x00000000FFFFFFFF : 0x0000FFFF;

1947

1948

1950

1951

1954

1955 if (IsStrict) {

1956

1957

1958

1960 {Node->getOperand(0), HI});

1962 {fHI.getValue(1), fHI, TWOHW});

1964 {Node->getOperand(0), LO});

1965

1968

1969

1972

1973 Results.push_back(Result);

1975 return;

1976 }

1977

1978

1979

1980

1984

1985

1987}

1988

1989SDValue VectorLegalizer::ExpandFNEG(SDNode *Node) {

1990 EVT VT = Node->getValueType(0);

1992

1995

1996

2000

2001 SDLoc DL(Node);

2006 return DAG.getNode(ISD::BITCAST, DL, VT, Xor);

2007}

2008

2009SDValue VectorLegalizer::ExpandFABS(SDNode *Node) {

2010 EVT VT = Node->getValueType(0);

2012

2015

2016

2020

2021 SDLoc DL(Node);

2026 return DAG.getNode(ISD::BITCAST, DL, VT, ClearedSign);

2027}

2028

2029SDValue VectorLegalizer::ExpandFCOPYSIGN(SDNode *Node) {

2030 EVT VT = Node->getValueType(0);

2032

2033 if (VT != Node->getOperand(1).getValueType() ||

2037

2038

2042

2043 SDLoc DL(Node);

2046

2050

2054

2057

2058 return DAG.getNode(ISD::BITCAST, DL, VT, CopiedSign);

2059}

2060

2061void VectorLegalizer::ExpandFSUB(SDNode *Node,

2062 SmallVectorImpl &Results) {

2063

2064

2065

2066 EVT VT = Node->getValueType(0);

2069 return;

2070

2072 Results.push_back(Expanded);

2073 return;

2074 }

2075

2078}

2079

2080void VectorLegalizer::ExpandSETCC(SDNode *Node,

2081 SmallVectorImpl &Results) {

2082 bool NeedInvert = false;

2083 bool IsVP = Node->getOpcode() == ISD::VP_SETCC;

2087 unsigned Offset = IsStrict ? 1 : 0;

2088

2093

2094 MVT OpVT = LHS.getSimpleValueType();

2096

2097 if (TLI.getCondCodeAction(CCCode, OpVT) != TargetLowering::Expand) {

2098 if (IsStrict) {

2099 UnrollStrictFPOp(Node, Results);

2100 return;

2101 }

2102 Results.push_back(UnrollVSETCC(Node));

2103 return;

2104 }

2105

2107 if (IsVP) {

2110 }

2111

2112 SDLoc dl(Node);

2113 bool Legalized =

2115 EVL, NeedInvert, dl, Chain, IsSignaling);

2116

2117 if (Legalized) {

2118

2119

2121 if (IsStrict) {

2123 {Chain, LHS, RHS, CC}, Node->getFlags());

2124 Chain = LHS.getValue(1);

2125 } else if (IsVP) {

2126 LHS = DAG.getNode(ISD::VP_SETCC, dl, Node->getValueType(0),

2127 {LHS, RHS, CC, Mask, EVL}, Node->getFlags());

2128 } else {

2130 Node->getFlags());

2131 }

2132 }

2133

2134

2135

2136 if (NeedInvert) {

2137 if (!IsVP)

2139 else

2141 }

2142 } else {

2143 assert(!IsStrict && "Don't know how to expand for strict nodes.");

2144

2145

2146

2147 EVT VT = Node->getValueType(0);

2151 CC, Node->getFlags());

2152 }

2153

2155 if (IsStrict)

2156 Results.push_back(Chain);

2157}

2158

2159void VectorLegalizer::ExpandUADDSUBO(SDNode *Node,

2160 SmallVectorImpl &Results) {

2163 Results.push_back(Result);

2164 Results.push_back(Overflow);

2165}

2166

2167void VectorLegalizer::ExpandSADDSUBO(SDNode *Node,

2168 SmallVectorImpl &Results) {

2171 Results.push_back(Result);

2172 Results.push_back(Overflow);

2173}

2174

2175void VectorLegalizer::ExpandMULO(SDNode *Node,

2176 SmallVectorImpl &Results) {

2178 if (!TLI.expandMULO(Node, Result, Overflow, DAG))

2180

2181 Results.push_back(Result);

2182 Results.push_back(Overflow);

2183}

2184

2185void VectorLegalizer::ExpandFixedPointDiv(SDNode *Node,

2186 SmallVectorImpl &Results) {

2187 SDNode *N = Node;

2189 N->getOperand(0), N->getOperand(1), N->getConstantOperandVal(2), DAG))

2190 Results.push_back(Expanded);

2191}

2192

2193void VectorLegalizer::ExpandStrictFPOp(SDNode *Node,

2194 SmallVectorImpl &Results) {

2196 ExpandUINT_TO_FLOAT(Node, Results);

2197 return;

2198 }

2200 ExpandFP_TO_UINT(Node, Results);

2201 return;

2202 }

2203

2206 ExpandSETCC(Node, Results);

2207 return;

2208 }

2209

2210 UnrollStrictFPOp(Node, Results);

2211}

2212

2213void VectorLegalizer::ExpandREM(SDNode *Node,

2214 SmallVectorImpl &Results) {

2216 "Expected REM node");

2217

2219 if (!TLI.expandREM(Node, Result, DAG))

2221 Results.push_back(Result);

2222}

2223

2224

2225

2226

2227

2228

2229

2230bool VectorLegalizer::tryExpandVecMathCall(SDNode *Node, RTLIB::Libcall LC,

2231 SmallVectorImpl &Results) {

2232

2233

2234 assert( Node ->isStrictFPOpcode() && "Unexpected strict fp operation!");

2235

2237 if (!LCName)

2238 return false;

2239 LLVM_DEBUG(dbgs() << "Looking for vector variant of " << LCName << "\n");

2240

2241 EVT VT = Node->getValueType(0);

2243

2244

2245

2246 const TargetLibraryInfo &TLibInfo = DAG.getLibInfo();

2248 if (!VD)

2250 if (!VD)

2251 return false;

2252

2253 LLVMContext *Ctx = DAG.getContext();

2256

2257

2259 for (unsigned i = 0; i < Node->getNumOperands(); ++i) {

2260 assert(Node->getOperand(i).getValueType() == VT &&

2261 "Expected matching vector types!");

2263 }

2264 FunctionType *ScalarFTy = FunctionType::get(ScalarTy, ArgTys, false);

2265

2266

2269 if (!OptVFInfo)

2270 return false;

2271

2273 << "\n");

2274

2275

2276 if (OptVFInfo->Shape.Parameters.size() !=

2278 return false;

2279

2280

2281

2282 SDLoc DL(Node);

2283 TargetLowering::ArgListTy Args;

2284

2285 unsigned OpNum = 0;

2286 for (auto &VFParam : OptVFInfo->Shape.Parameters) {

2287 if (VFParam.ParamKind == VFParamKind::GlobalPredicate) {

2291 continue;

2292 }

2293

2294

2295 if (VFParam.ParamKind != VFParamKind::Vector)

2296 return false;

2297

2298 Args.emplace_back(Node->getOperand(OpNum++), Ty);

2299 }

2300

2301

2304 TargetLowering::CallLoweringInfo CLI(DAG);

2305 CLI.setDebugLoc(DL)

2307 .setLibCallee(CallingConv::C, Ty, Callee, std::move(Args));

2308

2309 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);

2310 Results.push_back(CallResult.first);

2311 return true;

2312}

2313

2314

2315bool VectorLegalizer::tryExpandVecMathCall(

2316 SDNode *Node, RTLIB::Libcall Call_F32, RTLIB::Libcall Call_F64,

2317 RTLIB::Libcall Call_F80, RTLIB::Libcall Call_F128,

2318 RTLIB::Libcall Call_PPCF128, SmallVectorImpl &Results) {

2320 Node->getValueType(0).getVectorElementType(), Call_F32, Call_F64,

2321 Call_F80, Call_F128, Call_PPCF128);

2322

2323 if (LC == RTLIB::UNKNOWN_LIBCALL)

2324 return false;

2325

2326 return tryExpandVecMathCall(Node, LC, Results);

2327}

2328

2329void VectorLegalizer::UnrollStrictFPOp(SDNode *Node,

2330 SmallVectorImpl &Results) {

2331 EVT VT = Node->getValueType(0);

2334 unsigned NumOpers = Node->getNumOperands();

2336

2337 EVT TmpEltVT = EltVT;

2342

2343 EVT ValueVTs[] = {TmpEltVT, MVT::Other};

2345 SDLoc dl(Node);

2346

2349 for (unsigned i = 0; i < NumElems; ++i) {

2352

2353

2355

2356

2357 for (unsigned j = 1; j < NumOpers; ++j) {

2360

2364

2366 }

2367

2368 SDValue ScalarOp = DAG.getNode(Node->getOpcode(), dl, ValueVTs, Opers);

2371

2374 ScalarResult = DAG.getSelect(dl, EltVT, ScalarResult,

2377

2378 OpValues.push_back(ScalarResult);

2379 OpChains.push_back(ScalarChain);

2380 }

2381

2384

2385 Results.push_back(Result);

2386 Results.push_back(NewChain);

2387}

2388

2389SDValue VectorLegalizer::UnrollVSETCC(SDNode *Node) {

2390 EVT VT = Node->getValueType(0);

2396 EVT TmpEltVT = LHS.getValueType().getVectorElementType();

2397 SDLoc dl(Node);

2399 for (unsigned i = 0; i < NumElems; ++i) {

2404

2408 LHSElem, RHSElem, CC);

2412 }

2414}

2415

2417 return VectorLegalizer(*this).Run();

2418}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

Function Alias Analysis Results

static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")

This file defines the DenseMap class.

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

static void createBSWAPShuffleMask(EVT VT, SmallVectorImpl< int > &ShuffleMask)

Definition LegalizeVectorOps.cpp:1509

This file defines the SmallVector class.

This file describes how to lower LLVM code to machine code.

static APInt getSignMask(unsigned BitWidth)

Get the SignMask for a specific bit width.

static APInt getSignedMaxValue(unsigned numBits)

Gets maximum signed value of APInt for a specific bit width.

std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)

unsigned getVectorNumElements() const

bool isVector() const

Return true if this is a vector value type.

MVT getVectorElementType() const

bool isFloatingPoint() const

Return true if this is a FP or a vector FP type.

MVT getScalarType() const

If this is a vector, return the element type, otherwise return this.

MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...

Represents one node in the SelectionDAG.

unsigned getNumValues() const

Return the number of values defined/returned by this operator.

EVT getValueType(unsigned ResNo) const

Return the type of a specified result.

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.

SDNode * getNode() const

get the SDNode which holds the desired result

SDValue getValue(unsigned R) const

EVT getValueType() const

Return the ValueType of the referenced return value.

TypeSize getValueSizeInBits() const

Returns the size of the value in bits.

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...

const SDValue & getRoot() const

Return the root tag of the SelectionDAG.

LLVM_ABI SDVTList getVTList(EVT VT)

Return an SDVTList that represents the list of values specified.

LLVM_ABI SDValue getAllOnesConstant(const SDLoc &DL, EVT VT, bool IsTarget=false, bool IsOpaque=false)

LLVM_ABI bool LegalizeVectors()

This transforms the SelectionDAG into a SelectionDAG that only uses vector math operations supported ...

Definition LegalizeVectorOps.cpp:2416

SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)

Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...

LLVM_ABI SDValue UnrollVectorOp(SDNode *N, unsigned ResNE=0)

Utility function used by legalize and lowering to "unroll" a vector operation by splitting out the sc...

LLVM_ABI SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)

Create a ConstantFPSDNode wrapping a constant value.

SDValue getInsertSubvector(const SDLoc &DL, SDValue Vec, SDValue SubVec, unsigned Idx)

Insert SubVec at the Idx element of Vec.

LLVM_ABI SDValue getStepVector(const SDLoc &DL, EVT ResVT, const APInt &StepVal)

Returns a vector of type ResVT whose elements contain the linear sequence <0, Step,...

LLVM_ABI SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT)

Create a bitwise NOT operation as (XOR Val, -1).

const TargetLowering & getTargetLoweringInfo() const

LLVM_ABI std::pair< SDValue, SDValue > UnrollVectorOverflowOp(SDNode *N, unsigned ResNE=0)

Like UnrollVectorOp(), but for the [US](ADD|SUB|MUL)O family of opcodes.

allnodes_const_iterator allnodes_begin() const

SDValue getUNDEF(EVT VT)

Return an UNDEF node. UNDEF does not have a useful SDLoc.

SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)

Return an ISD::BUILD_VECTOR node.

allnodes_const_iterator allnodes_end() const

SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS, SDNodeFlags Flags=SDNodeFlags())

Helper function to make it easier to build Select's if you just have operands and don't want to check...

const DataLayout & getDataLayout() const

LLVM_ABI SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)

Create a ConstantSDNode wrapping a constant value.

LLVM_ABI void RemoveDeadNodes()

This method deletes all unreachable nodes in the SelectionDAG.

LLVM_ABI SDValue getExternalSymbol(const char *Sym, EVT VT)

LLVM_ABI SDValue getVPLogicalNOT(const SDLoc &DL, SDValue Val, SDValue Mask, SDValue EVL, EVT VT)

Create a vector-predicated logical NOT operation as (VP_XOR Val, BooleanOne, Mask,...

LLVM_ABI SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)

LLVM_ABI SDValue getValueType(EVT)

LLVM_ABI SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)

Gets or creates the specified node.

LLVM_ABI unsigned AssignTopologicalOrder()

Topological-sort the AllNodes list and a assign a unique node id for each node in the DAG based on th...

const TargetLibraryInfo & getLibInfo() const

LLVM_ABI SDValue getBoolConstant(bool V, const SDLoc &DL, EVT VT, EVT OpVT)

Create a true or false constant of type VT using the target's BooleanContent for type OpVT.

LLVM_ABI SDValue getVectorIdxConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)

LLVMContext * getContext() const

const SDValue & setRoot(SDValue N)

Set the current root tag of the SelectionDAG.

LLVM_ABI SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)

Mutate the specified node in-place to have the specified operands.

SDValue getEntryNode() const

Return the token chain corresponding to the entry of the function.

SDValue getSplat(EVT VT, const SDLoc &DL, SDValue Op)

Returns a node representing a splat of one value into all lanes of the provided vector type.

LLVM_ABI SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue N2, ArrayRef< int > Mask)

Return an ISD::VECTOR_SHUFFLE node.

LLVM_ABI SDValue getLogicalNOT(const SDLoc &DL, SDValue Val, EVT VT)

Create a logical NOT operation as (XOR Val, BooleanOne).

ilist< SDNode >::iterator allnodes_iterator

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void push_back(const T &Elt)

constexpr const char * data() const

data - Get a pointer to the start of the string (which may not be null terminated).

const VecDesc * getVectorMappingInfo(StringRef F, const ElementCount &VF, bool Masked) const

virtual bool isShuffleMaskLegal(ArrayRef< int >, EVT) const

Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations,...

LegalizeAction getCondCodeAction(ISD::CondCode CC, MVT VT) const

Return how the condition code should be treated: either it is legal, needs to be expanded to some oth...

LegalizeAction getFixedPointOperationAction(unsigned Op, EVT VT, unsigned Scale) const

Some fixed point operations may be natively supported by the target but only for specific scales.

bool isStrictFPEnabled() const

Return true if the target support strict float operation.

virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const

Return the ValueType of the result of SETCC operations.

BooleanContent getBooleanContents(bool isVec, bool isFloat) const

For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...

virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const

Return the pointer type for the given address space, defaults to the pointer type from the data layou...

LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const

Return how this store with truncation should be treated: either it is legal, needs to be promoted to ...

LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const

Return how this load with extension should be treated: either it is legal, needs to be promoted to a ...

bool isOperationLegalOrCustom(unsigned Op, EVT VT, bool LegalOnly=false) const

Return true if the specified operation is legal on this target or can be made legal with custom lower...

LegalizeAction getPartialReduceMLAAction(unsigned Opc, EVT AccVT, EVT InputVT) const

Return how a PARTIAL_REDUCE_U/SMLA node with Acc type AccVT and Input type InputVT should be treated.

LegalizeAction getStrictFPOperationAction(unsigned Op, EVT VT) const

const char * getLibcallName(RTLIB::Libcall Call) const

Get the libcall routine name for the specified libcall.

LegalizeAction getOperationAction(unsigned Op, EVT VT) const

Return how this operation should be treated: either it is legal, needs to be promoted to a larger siz...

MVT getTypeToPromoteTo(unsigned Op, MVT VT) const

If the action for this operation is to promote, this method returns the ValueType to promote to.

bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT, bool LegalOnly=false) const

Return true if the specified operation is legal on this target or can be made legal with custom lower...

This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...

SDValue expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const

Method for building the DAG expansion of ISD::[US][ADD|SUB]SAT.

bool expandMultipleResultFPLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, SDNode *Node, SmallVectorImpl< SDValue > &Results, std::optional< unsigned > CallRetResNo={}) const

Expands a node with multiple results to an FP or vector libcall.

SDValue expandVPCTLZ(SDNode *N, SelectionDAG &DAG) const

Expand VP_CTLZ/VP_CTLZ_ZERO_UNDEF nodes.

bool expandMULO(SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const

Method for building the DAG expansion of ISD::[US]MULO.

SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const

SDValue expandVPBSWAP(SDNode *N, SelectionDAG &DAG) const

Expand VP_BSWAP nodes.

SDValue expandVecReduceSeq(SDNode *Node, SelectionDAG &DAG) const

Expand a VECREDUCE_SEQ_* into an explicit ordered calculation.

SDValue expandCTLZ(SDNode *N, SelectionDAG &DAG) const

Expand CTLZ/CTLZ_ZERO_UNDEF nodes.

SDValue expandBITREVERSE(SDNode *N, SelectionDAG &DAG) const

Expand BITREVERSE nodes.

SDValue expandCTTZ(SDNode *N, SelectionDAG &DAG) const

Expand CTTZ/CTTZ_ZERO_UNDEF nodes.

SDValue expandABD(SDNode *N, SelectionDAG &DAG) const

Expand ABDS/ABDU nodes.

SDValue expandShlSat(SDNode *Node, SelectionDAG &DAG) const

Method for building the DAG expansion of ISD::[US]SHLSAT.

SDValue expandFP_TO_INT_SAT(SDNode *N, SelectionDAG &DAG) const

Expand FP_TO_[US]INT_SAT into FP_TO_[US]INT and selects or min/max.

void expandSADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const

Method for building the DAG expansion of ISD::S(ADD|SUB)O.

SDValue expandVPBITREVERSE(SDNode *N, SelectionDAG &DAG) const

Expand VP_BITREVERSE nodes.

SDValue expandABS(SDNode *N, SelectionDAG &DAG, bool IsNegative=false) const

Expand ABS nodes.

SDValue expandVecReduce(SDNode *Node, SelectionDAG &DAG) const

Expand a VECREDUCE_* into an explicit calculation.

bool expandFP_TO_UINT(SDNode *N, SDValue &Result, SDValue &Chain, SelectionDAG &DAG) const

Expand float to UINT conversion.

bool expandREM(SDNode *Node, SDValue &Result, SelectionDAG &DAG) const

Expand an SREM or UREM using SDIV/UDIV or SDIVREM/UDIVREM, if legal.

SDValue expandFMINIMUMNUM_FMAXIMUMNUM(SDNode *N, SelectionDAG &DAG) const

Expand fminimumnum/fmaximumnum into multiple comparison with selects.

SDValue expandCTPOP(SDNode *N, SelectionDAG &DAG) const

Expand CTPOP nodes.

SDValue expandVectorNaryOpBySplitting(SDNode *Node, SelectionDAG &DAG) const

std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const

This function lowers an abstract call to a function into an actual call.

SDValue expandBSWAP(SDNode *N, SelectionDAG &DAG) const

Expand BSWAP nodes.

SDValue expandFMINIMUM_FMAXIMUM(SDNode *N, SelectionDAG &DAG) const

Expand fminimum/fmaximum into multiple comparison with selects.

std::pair< SDValue, SDValue > scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const

Turn load of vector type into a load of the individual elements.

SDValue expandFunnelShift(SDNode *N, SelectionDAG &DAG) const

Expand funnel shift.

bool LegalizeSetCCCondCode(SelectionDAG &DAG, EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, SDValue Mask, SDValue EVL, bool &NeedInvert, const SDLoc &dl, SDValue &Chain, bool IsSignaling=false) const

Legalize a SETCC or VP_SETCC with given LHS and RHS and condition code CC on the current target.

virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const

This callback is invoked for operations that are unsupported by the target, which are registered to u...

SDValue expandVPCTPOP(SDNode *N, SelectionDAG &DAG) const

Expand VP_CTPOP nodes.

SDValue expandFixedPointDiv(unsigned Opcode, const SDLoc &dl, SDValue LHS, SDValue RHS, unsigned Scale, SelectionDAG &DAG) const

Method for building the DAG expansion of ISD::[US]DIVFIX[SAT].

SDValue expandVPCTTZ(SDNode *N, SelectionDAG &DAG) const

Expand VP_CTTZ/VP_CTTZ_ZERO_UNDEF nodes.

SDValue expandVECTOR_COMPRESS(SDNode *Node, SelectionDAG &DAG) const

Expand a vector VECTOR_COMPRESS into a sequence of extract element, store temporarily,...

SDValue expandROT(SDNode *N, bool AllowVectorOps, SelectionDAG &DAG) const

Expand rotations.

SDValue expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) const

Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs.

SDValue expandCMP(SDNode *Node, SelectionDAG &DAG) const

Method for building the DAG expansion of ISD::[US]CMP.

SDValue expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) const

Method for building the DAG expansion of ISD::[U|S]MULFIX[SAT].

SDValue expandIntMINMAX(SDNode *Node, SelectionDAG &DAG) const

Method for building the DAG expansion of ISD::[US][MIN|MAX].

SDValue expandVectorFindLastActive(SDNode *N, SelectionDAG &DAG) const

Expand VECTOR_FIND_LAST_ACTIVE nodes.

SDValue expandPartialReduceMLA(SDNode *Node, SelectionDAG &DAG) const

Expands PARTIAL_REDUCE_S/UMLA nodes to a series of simpler operations, consisting of zext/sext,...

void expandUADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const

Method for building the DAG expansion of ISD::U(ADD|SUB)O.

bool expandUINT_TO_FP(SDNode *N, SDValue &Result, SDValue &Chain, SelectionDAG &DAG) const

Expand UINT(i64) to double(f64) conversion.

SDValue expandAVG(SDNode *N, SelectionDAG &DAG) const

Expand vector/scalar AVGCEILS/AVGCEILU/AVGFLOORS/AVGFLOORU nodes.

Type * getScalarType() const

If this is a vector type, return the element type, otherwise return 'this'.

LLVM_ABI std::string getVectorFunctionABIVariantString() const

Returns a vector function ABI variant string on the form: ZGV(<...

StringRef getVectorFnName() const

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

constexpr char Args[]

Key for Kernel::Metadata::mArgs.

constexpr std::underlying_type_t< E > Mask()

Get a bitmask with 1s in all places up to the high-order bit of E's largest value.

@ SETCC

SetCC operator - This evaluates to a true value iff the condition is true.

@ MERGE_VALUES

MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...

@ STRICT_FSETCC

STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used for floating-point operands only.

@ LOOP_DEPENDENCE_RAW_MASK

@ SMUL_LOHI

SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...

@ BSWAP

Byte Swap and Counting operators.

@ SMULFIX

RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...

@ ADD

Simple integer binary arithmetic operators.

@ SMULFIXSAT

Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...

@ ANY_EXTEND

ANY_EXTEND - Used for integer types. The high bits are undefined.

@ FMA

FMA - Perform a * b + c with no intermediate rounding step.

@ SINT_TO_FP

[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...

@ FADD

Simple binary floating point operators.

@ ABS

ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.

@ SIGN_EXTEND_VECTOR_INREG

SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...

@ SDIVREM

SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.

@ FPTRUNC_ROUND

FPTRUNC_ROUND - This corresponds to the fptrunc_round intrinsic.

@ SDIVFIX

RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on 2 integers with the same width...

@ STRICT_FSQRT

Constrained versions of libm-equivalent floating point intrinsics.

@ SIGN_EXTEND

Conversion operators.

@ AVGCEILS

AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an integer of type i[N+2],...

@ CTTZ_ZERO_UNDEF

Bit counting operators with an undefined result for zero inputs.

@ SSUBO

Same for subtraction.

@ STEP_VECTOR

STEP_VECTOR(IMM) - Returns a scalable vector whose lanes are comprised of a linear sequence of unsign...

@ FCANONICALIZE

Returns platform specific canonical encoding of a floating point number.

@ SSUBSAT

RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...

@ SELECT

Select(COND, TRUEVAL, FALSEVAL).

@ SPLAT_VECTOR

SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.

@ SADDO

RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.

@ MULHU

MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...

@ SHL

Shift and rotation operations.

@ EXTRACT_VECTOR_ELT

EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...

@ ZERO_EXTEND

ZERO_EXTEND - Used for integer types, zeroing the new bits.

@ SELECT_CC

Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...

@ SSHLSAT

RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.

@ SMULO

Same for multiplication.

@ ANY_EXTEND_VECTOR_INREG

ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...

@ SIGN_EXTEND_INREG

SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...

@ SMIN

[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.

@ SDIVFIXSAT

Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...

@ VSELECT

Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...

@ STRICT_SINT_TO_FP

STRICT_[US]INT_TO_FP - Convert a signed or unsigned integer to a floating point value.

@ STRICT_FP_ROUND

X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision ...

@ STRICT_FP_TO_SINT

STRICT_FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.

@ FP_TO_SINT

FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.

@ STRICT_FP_EXTEND

X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.

@ AND

Bitwise operators - logical and, logical or, logical xor.

@ SCMP

[US]CMP - 3-way comparison of signed or unsigned integers.

@ AVGFLOORS

AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of type i[N+1],...

@ STRICT_FADD

Constrained versions of the binary floating point operators.

@ TokenFactor

TokenFactor - This node takes multiple tokens as input and produces a single token result.

@ FP_ROUND

X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...

@ VECTOR_COMPRESS

VECTOR_COMPRESS(Vec, Mask, Passthru) consecutively place vector elements based on mask e....

@ ZERO_EXTEND_VECTOR_INREG

ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...

@ FP_TO_SINT_SAT

FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...

@ TRUNCATE

TRUNCATE - Completely drop the high bits.

@ AssertSext

AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...

@ FCOPYSIGN

FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.

@ SADDSAT

RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...

@ ABDS

ABDS/ABDU - Absolute difference - Return the absolute difference between two numbers interpreted as s...

@ BUILD_VECTOR

BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...

@ LOOP_DEPENDENCE_WAR_MASK

Set rounding mode.

LLVM_ABI std::optional< unsigned > getVPMaskIdx(unsigned Opcode)

The operand position of the vector mask.

LLVM_ABI std::optional< unsigned > getVPExplicitVectorLengthIdx(unsigned Opcode)

The operand position of the explicit vector length parameter.

CondCode

ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...

LoadExtType

LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).

LLVM_ABI bool isVPOpcode(unsigned Opcode)

Whether this is a vector-predicated Opcode.

LLVM_ABI Libcall getSINCOSPI(EVT RetVT)

getSINCOSPI - Return the SINCOSPI_* value for the given types, or UNKNOWN_LIBCALL if there is none.

LLVM_ABI Libcall getFPLibCall(EVT VT, Libcall Call_F32, Libcall Call_F64, Libcall Call_F80, Libcall Call_F128, Libcall Call_PPCF128)

GetFPLibCall - Helper to return the right libcall for the given floating point type,...

LLVM_ABI Libcall getMODF(EVT VT)

getMODF - Return the MODF_* value for the given types, or UNKNOWN_LIBCALL if there is none.

LLVM_ABI Libcall getSINCOS(EVT RetVT)

getSINCOS - Return the SINCOS_* value for the given types, or UNKNOWN_LIBCALL if there is none.

LLVM_ABI std::optional< VFInfo > tryDemangleForVFABI(StringRef MangledName, const FunctionType *FTy)

Function to construct a VFInfo out of a mangled names in the following format:

NodeAddr< NodeBase * > Node

This is an optimization pass for GlobalISel generic memory operations.

bool any_of(R &&range, UnaryPredicate P)

Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

SmallVector< ValueTypeFromRangeType< R >, Size > to_vector(R &&Range)

Given a range of type R, iterate the entire range and return a SmallVector with elements of the vecto...

class LLVM_GSL_OWNER SmallVector

Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...

MutableArrayRef(T &OneElt) -> MutableArrayRef< T >

@ Xor

Bitwise or logical XOR of integers.

DWARFExpression::Operation Op

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

auto seq(T Begin, T End)

Iterate over an integral type from Begin up to - but not including - End.

EVT changeVectorElementTypeToInteger() const

Return a vector with the same number of elements as this vector, but with the element type converted ...

static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)

Returns the EVT that represents a vector NumElements in length, where each element is of type VT.

ElementCount getVectorElementCount() const

TypeSize getSizeInBits() const

Return the size of the specified value type in bits.

EVT changeElementType(EVT EltVT) const

Return a VT for a type whose attributes match ourselves with the exception of the element type that i...

uint64_t getScalarSizeInBits() const

bool isFixedLengthVector() const

bool isVector() const

Return true if this is a vector value type.

EVT getScalarType() const

If this is a vector type, return the element type, otherwise return this.

LLVM_ABI Type * getTypeForEVT(LLVMContext &Context) const

This method returns an LLVM type corresponding to the specified EVT.

bool isScalableVector() const

Return true if this is a vector type where the runtime length is machine dependent.

EVT getVectorElementType() const

Given a vector type, return the type of each element.

EVT changeVectorElementType(EVT EltVT) const

Return a VT for a vector type whose attributes match ourselves with the exception of the element type...

unsigned getVectorNumElements() const

Given a vector type, return the number of elements it contains.

bool bitsLE(EVT VT) const

Return true if this has no more bits than VT.