M68kInstrInfo.cpp Source File (original) (raw)

33#include

35using namespace llvm;

37#define DEBUG_TYPE "M68k-instr-info"

39#define GET_INSTRINFO_CTOR_DTOR

40#include "M68kGenInstrInfo.inc"

43void M68kInstrInfo::anchor() {}

51 switch (BrOpc) {

52 default:

54 case M68k::Beq8:

56 case M68k::Bne8:

58 case M68k::Blt8:

60 case M68k::Ble8:

62 case M68k::Bgt8:

64 case M68k::Bge8:

66 case M68k::Bcs8:

68 case M68k::Bls8:

70 case M68k::Bhi8:

72 case M68k::Bcc8:

74 case M68k::Bmi8:

76 case M68k::Bpl8:

78 case M68k::Bvs8:

80 case M68k::Bvc8:

82 }

83}

89 bool AllowModify) const {

91 auto UncondBranch =

92 std::pair<MachineBasicBlock::reverse_iterator, MachineBasicBlock *>{

93 MBB.rend(), nullptr};

96 std::vector<std::reference_wrapperllvm::MachineInstr> EraseList;

98 for (auto &Ref : EraseList)

99 Ref.get().eraseFromParent();

100 });

101

102

103

104 for (auto iter = MBB.rbegin(); iter != MBB.rend(); iter = std::next(iter)) {

105

106 unsigned Opcode = iter->getOpcode();

107

108 if (iter->isDebugInstr())

109 continue;

110

111

112

113 if (!isUnpredicatedTerminator(*iter))

114 break;

115

116

117

118 if (!iter->isBranch())

119 return true;

120

121

122 if (Opcode == M68k::BRA8 || Opcode == M68k::BRA16) {

123 if (!iter->getOperand(0).isMBB())

124 return true;

125 UncondBranch = {iter, iter->getOperand(0).getMBB()};

126

127

128 TBB = UncondBranch.second;

129

130 if (!AllowModify)

131 continue;

132

133

134 EraseList.insert(EraseList.begin(), MBB.rbegin(), iter);

135

136 Cond.clear();

137 FBB = nullptr;

138

139

140 if (MBB.isLayoutSuccessor(UncondBranch.second)) {

141 TBB = nullptr;

142 EraseList.push_back(*iter);

143 UncondBranch = {MBB.rend(), nullptr};

144 }

145

146 continue;

147 }

148

149

151

152

154 return true;

155

156

157

158

159

160

161

162

163 if (Cond.empty()) {

164 if (!iter->getOperand(0).isMBB())

165 return true;

166 MachineBasicBlock *CondBranchTarget = iter->getOperand(0).getMBB();

167

168

169

170

171

172

173

174

175

176 if (UncondBranch.first != MBB.rend()) {

177

178 assert(std::next(UncondBranch.first) == iter && "Wrong block layout.");

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197 if (AllowModify && MBB.isLayoutSuccessor(CondBranchTarget)) {

198

201

202 BuildMI(MBB, *UncondBranch.first, MBB.rfindDebugLoc(iter), get(BNCC))

203 .addMBB(UncondBranch.second);

204

205 EraseList.push_back(*iter);

206 EraseList.push_back(*UncondBranch.first);

207

208 TBB = UncondBranch.second;

209 FBB = nullptr;

211

212

213 } else {

214 TBB = CondBranchTarget;

215 FBB = UncondBranch.second;

217 }

218

219 UncondBranch = {MBB.rend(), nullptr};

220 continue;

221 }

222

223 TBB = CondBranchTarget;

224 FBB = nullptr;

226

227 continue;

228 }

229

230

231

232

235

236

238 if (!iter->getOperand(0).isMBB())

239 return true;

240 auto NewTBB = iter->getOperand(0).getMBB();

241 if (OldBranchCode == BranchCode && TBB == NewTBB)

242 continue;

243

244

245 return true;

246 }

247

248 return false;

249}

250

255 bool AllowModify) const {

257}

258

260 int *BytesRemoved) const {

261 assert(!BytesRemoved && "code size not handled");

262

264 unsigned Count = 0;

265

266 while (I != MBB.begin()) {

267 --I;

268 if (I->isDebugValue())

269 continue;

270 if (I->getOpcode() != M68k::BRA8 &&

272 break;

273

274 I->eraseFromParent();

275 I = MBB.end();

277 }

278

280}

281

285

286 assert(TBB && "InsertBranch must not be told to insert a fallthrough");

288 "M68k branch conditions have one component!");

289 assert(!BytesAdded && "code size not handled");

290

291 if (Cond.empty()) {

292

293 assert(!FBB && "Unconditional branch with multiple successors!");

295 return 1;

296 }

297

298

299 bool FallThru = FBB == nullptr;

300

301

302 unsigned Count = 0;

307 if (!FallThru) {

308

311 }

313}

314

317 unsigned Reg, MVT From, MVT To) const {

318 if (From == MVT::i8) {

319 unsigned R = Reg;

320

321 if (To == MVT::i32) {

322 R = RI.getSubReg(Reg, M68k::MxSubRegIndex16Lo);

323 assert(R && "No viable SUB register available");

324 }

326 }

327

328 if (To == MVT::i32)

330}

331

334 unsigned Reg, MVT From, MVT To) const {

335

336 unsigned Mask, And;

337 if (From == MVT::i8)

338 Mask = 0xFF;

339 else

340 Mask = 0xFFFF;

341

342 if (To == MVT::i16)

343 And = M68k::AND16di;

344 else

345 And = M68k::AND32di;

346

347

349}

350

351

352

356 bool IsAddressReg = false;

357

358 const auto *DR32 = RI.getRegClass(M68k::DR32RegClassID);

359 const auto *AR32 = RI.getRegClass(M68k::AR32RegClassID);

360 const auto *AR16 = RI.getRegClass(M68k::AR16RegClassID);

361

362 if (AR16->contains(Reg) || AR32->contains(Reg))

363 IsAddressReg = true;

364

365

367 MVTSize == MVT::i32

368 ? Reg

369 : Register(RI.getMatchingMegaReg(Reg, IsAddressReg ? AR32 : DR32));

370 assert(SReg && "No viable MEGA register available");

371

373

374

375 if (MVTSize == MVT::i8 || (!IsAddressReg && Imm >= -128 && Imm <= 127)) {

377

380

381

382

383 } else if (DR32->contains(Reg) && isUInt<8>(Imm)) {

385

388

389 unsigned SubReg = RI.getSubReg(Reg, M68k::MxSubRegIndex8Lo);

390 assert(SubReg && "No viable SUB register available");

391

394

396

397

398 } else if (IsAddressReg && Imm == 0) {

400

403

407

409

410

411

412

413

414

415 } else if (AR32->contains(Reg) && isUInt<16>(Imm)) {

417

418 unsigned SubReg = RI.getSubReg(Reg, M68k::MxSubRegIndex16Lo);

419 assert(SubReg && "No viable SUB register available");

420

423

424

425 } else {

427 MIB->setDesc(get(MVTSize == MVT::i16 ? M68k::MOV16ri : M68k::MOV32ri));

428 }

429

430 return true;

431}

432

434 MVT MVTSrc) const {

435 unsigned Move = MVTDst == MVT::i16 ? M68k::MOV16rr : M68k::MOV32rr;

438

439 assert(Dst != Src && "You cannot use the same Regs with MOVX_RR");

440

442

443 const auto *RCDst = TRI.getMaximalPhysRegClass(Dst, MVTDst);

444 const auto *RCSrc = TRI.getMaximalPhysRegClass(Src, MVTSrc);

445

446 assert(RCDst && RCSrc && "Wrong use of MOVX_RR");

447 assert(RCDst != RCSrc && "You cannot use the same Reg Classes with MOVX_RR");

448 (void)RCSrc;

449

450

451 unsigned SSrc = RI.getMatchingMegaReg(Src, RCDst);

452 assert(SSrc && "No viable MEGA register available");

453

455

456

457

458 if (Dst == SSrc) {

461 } else {

465 }

466

467 return true;

468}

469

470

471

473 MVT MVTDst, MVT MVTSrc) const {

475

476 unsigned Move;

477

478 if (MVTDst == MVT::i16)

479 Move = M68k::MOV16rr;

480 else

481 Move = M68k::MOV32rr;

482

485

486 assert(Dst != Src && "You cannot use the same Regs with MOVSX_RR");

487

489

490 const auto *RCDst = TRI.getMaximalPhysRegClass(Dst, MVTDst);

491 const auto *RCSrc = TRI.getMaximalPhysRegClass(Src, MVTSrc);

492

493 assert(RCDst && RCSrc && "Wrong use of MOVSX_RR");

494 assert(RCDst != RCSrc && "You cannot use the same Reg Classes with MOVSX_RR");

495 (void)RCSrc;

496

497

498 unsigned SSrc = RI.getMatchingMegaReg(Src, RCDst);

499 assert(SSrc && "No viable MEGA register available");

500

503

504 if (Dst != SSrc) {

507 }

508

509 if (IsSigned) {

512 } else {

515 }

516

518

519 return true;

520}

521

524 MVT MVTSrc) const {

526

528

529

530

531

532

533

534 unsigned SubDst =

535 RI.getSubReg(Dst, MVTSrc == MVT::i8 ? M68k::MxSubRegIndex8Lo

536 : M68k::MxSubRegIndex16Lo);

537 assert(SubDst && "No viable SUB register available");

538

539

542

544 I++;

547

548 if (IsSigned) {

551 } else {

554 }

555

556 return true;

557}

558

562 I++;

566 if (IsPush)

568 else

570

572 return true;

573}

574

576 if (MIB->getOpcode() == M68k::MOV8cd) {

577

580 Opd.getReg(), M68k::MxSubRegIndex8Lo, &M68k::DR16RegClass));

581 }

582

583

584 if (IsToCCR)

586 else

587

589

590 return true;

591}

592

599

600 if (IsRM) {

604 } else {

608 }

609

610 unsigned Mask = 1 << RI.getSpillRegisterOrder(Reg);

611 if (IsRM) {

618 } else {

625 }

626

628

629 return true;

630}

631

632

633

634

635

636

637

638

641 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");

644

645

646

648

651 return true;

652}

653

656 switch (MI.getOpcode()) {

657 case M68k::PUSH8d:

659 case M68k::PUSH16d:

661 case M68k::PUSH32r:

663

664 case M68k::POP8d:

666 case M68k::POP16d:

668 case M68k::POP32r:

670

671 case M68k::SETCS_C8d:

673 case M68k::SETCS_C16d:

675 case M68k::SETCS_C32d:

677 }

678 return false;

679}

680

684

685

686

687

689 const unsigned NameIndices = M68kInstrNameIndices[MI->getOpcode()];

690 StringRef InstrName(&M68kInstrNameData[NameIndices]);

691 const unsigned OperandNo = MO.getOperandNo();

692

693

694

695 if (OperandNo == 1)

696 return Regex("[A-Z]+(8|16|32)k[a-z](_TC)?$").match(InstrName);

697

698

699

700 if (OperandNo == MI->getNumExplicitOperands() - 1)

701 return Regex("[A-Z]+(8|16|32)[a-z]k(_TC)?$").match(InstrName);

702

703 return false;

704}

705

709 Register SrcReg, bool KillSrc,

710 bool RenamableDest, bool RenamableSrc) const {

711 unsigned Opc = 0;

712

713

714 if (M68k::XR32RegClass.contains(DstReg, SrcReg))

715 Opc = M68k::MOV32rr;

716 else if (M68k::XR16RegClass.contains(DstReg, SrcReg))

717 Opc = M68k::MOV16rr;

718 else if (M68k::DR8RegClass.contains(DstReg, SrcReg))

719 Opc = M68k::MOV8dd;

720

721 if (Opc) {

724 return;

725 }

726

727

728

729

730

731

732

734 if (M68k::DR8RegClass.contains(SrcReg)) {

735 if (M68k::XR16RegClass.contains(DstReg))

736 Opc = M68k::MOVXd16d8;

737 else if (M68k::XR32RegClass.contains(DstReg))

738 Opc = M68k::MOVXd32d8;

739 } else if (M68k::XR16RegClass.contains(SrcReg) &&

740 M68k::XR32RegClass.contains(DstReg))

741 Opc = M68k::MOVXd32d16;

742

743 if (Opc) {

746 return;

747 }

748

749 bool FromCCR = SrcReg == M68k::CCR;

750 bool FromSR = SrcReg == M68k::SR;

751 bool ToCCR = DstReg == M68k::CCR;

752 bool ToSR = DstReg == M68k::SR;

753

754 if (FromCCR) {

755 if (M68k::DR8RegClass.contains(DstReg)) {

756 Opc = M68k::MOV8dc;

757 } else if (M68k::DR16RegClass.contains(DstReg)) {

758 Opc = M68k::MOV16dc;

759 } else if (M68k::DR32RegClass.contains(DstReg)) {

760 Opc = M68k::MOV16dc;

761 } else {

762 LLVM_DEBUG(dbgs() << "Cannot copy CCR to " << RI.getName(DstReg) << '\n');

764 }

765 } else if (ToCCR) {

766 if (M68k::DR8RegClass.contains(SrcReg)) {

767 Opc = M68k::MOV8cd;

768 } else if (M68k::DR16RegClass.contains(SrcReg)) {

769 Opc = M68k::MOV16cd;

770 } else if (M68k::DR32RegClass.contains(SrcReg)) {

771 Opc = M68k::MOV16cd;

772 } else {

773 LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to CCR\n");

775 }

776 } else if (FromSR || ToSR)

778

779 if (Opc) {

782 return;

783 }

784

785 LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "

786 << RI.getName(DstReg) << '\n');

788}

789

790namespace {

794 switch (TRI->getSpillSize(*RC)) {

795 default:

797 dbgs() << "Cannot determine appropriate opcode for load/store to/from "

798 << TRI->getName(Reg) << " of class " << TRI->getRegClassName(RC)

799 << " with spill size " << TRI->getSpillSize(*RC) << '\n');

801 case 2:

802 if (M68k::XR16RegClass.hasSubClassEq(RC))

803 return load ? M68k::MOVM16mp_P : M68k::MOVM16pm_P;

804 if (M68k::DR8RegClass.hasSubClassEq(RC))

805 return load ? M68k::MOVM16mp_P : M68k::MOVM16pm_P;

806 if (M68k::CCRCRegClass.hasSubClassEq(RC))

807 return load ? M68k::MOVM16mp_P : M68k::MOVM16pm_P;

809 case 4:

810 if (M68k::XR32RegClass.hasSubClassEq(RC))

811 return load ? M68k::MOVM32mp_P : M68k::MOVM32pm_P;

813 }

814}

815

820}

821

826}

827}

828

830 unsigned SubIdx, unsigned &Size,

833

836 return true;

837}

838

845 "Stack slot is too small to store");

846 (void)MFI;

847

850

853}

854

857 Register DstReg, int FrameIndex,

863 "Stack slot is too small to load");

864 (void)MFI;

865

869}

870

871

872

873

874

875

879 if (GlobalBaseReg != 0)

880 return GlobalBaseReg;

881

882

883

884

885

886

887

888

889

890

892 GlobalBaseReg = RegInfo.createVirtualRegister(&M68k::AR32_NOSPRegClass);

894 return GlobalBaseReg;

895}

896

897std::pair<unsigned, unsigned>

899 return std::make_pair(TF, 0u);

900}

901

904 using namespace M68kII;

905 static const std::pair<unsigned, const char *> TargetFlags[] = {

906 {MO_ABSOLUTE_ADDRESS, "m68k-absolute"},

907 {MO_PC_RELATIVE_ADDRESS, "m68k-pcrel"},

908 {MO_GOT, "m68k-got"},

909 {MO_GOTOFF, "m68k-gotoff"},

910 {MO_GOTPCREL, "m68k-gotpcrel"},

911 {MO_PLT, "m68k-plt"},

912 {MO_TLSGD, "m68k-tlsgd"},

913 {MO_TLSLD, "m68k-tlsld"},

914 {MO_TLSLDM, "m68k-tlsldm"},

915 {MO_TLSIE, "m68k-tlsie"},

916 {MO_TLSLE, "m68k-tlsle"}};

917 return ArrayRef(TargetFlags);

918}

919

920#undef DEBUG_TYPE

921#define DEBUG_TYPE "m68k-create-global-base-reg"

922

923#define PASS_NAME "M68k PIC Global Base Reg Initialization"

924

925namespace {

926

928 static char ID;

930

931 bool runOnMachineFunction(MachineFunction &MF) override {

934

935 unsigned GlobalBaseReg = MxFI->getGlobalBaseReg();

936

937

938 if (GlobalBaseReg == 0)

939 return false;

940

941

946

947

948 BuildMI(FirstMBB, MBBI, DL, TII->get(M68k::LEA32q), GlobalBaseReg)

950

951 return true;

952 }

953

954 void getAnalysisUsage(AnalysisUsage &AU) const override {

957 }

958};

959char M68kGlobalBaseReg::ID = 0;

960}

961

963

965 return new M68kGlobalBaseReg();

966}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

AMDGPU Mark last scratch load

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

MachineBasicBlock MachineBasicBlock::iterator MBBI

This file implements the LivePhysRegs utility for tracking liveness of physical registers.

This file exposes functions that may be used with BuildMI from the MachineInstrBuilder....

static M68k::CondCode getCondFromBranchOpc(unsigned BrOpc)

Definition M68kInstrInfo.cpp:50

static bool Expand2AddrUndef(MachineInstrBuilder &MIB, const MCInstrDesc &Desc)

Expand a single-def pseudo instruction to a two-addr instruction with two undef reads of the register...

Definition M68kInstrInfo.cpp:639

This file contains the M68k implementation of the TargetInstrInfo class.

This file contains the declarations for the code emitter which are useful outside of the emitter itse...

This file declares the M68k specific subclass of MachineFunctionInfo.

This file declares the M68k specific subclass of TargetMachine.

Promote Memory to Register

#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)

This file defines the make_scope_exit function, which executes user-defined cleanup logic at scope ex...

static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)

static unsigned getStoreRegOpcode(Register SrcReg, const TargetRegisterClass *RC, bool IsStackAligned, const X86Subtarget &STI)

static unsigned getLoadRegOpcode(Register DestReg, const TargetRegisterClass *RC, bool IsStackAligned, const X86Subtarget &STI)

static unsigned getLoadStoreRegOpcode(Register Reg, const TargetRegisterClass *RC, bool IsStackAligned, const X86Subtarget &STI, bool Load)

static unsigned GetCondBranchFromCond(XCore::CondCode CC)

GetCondBranchFromCond - Return the Branch instruction opcode that matches the cc.

Represent the analysis usage information of a pass.

LLVM_ABI void setPreservesCFG()

This function should be called by the pass, iff they do not:

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

FunctionPass class - This class is used to implement most global optimizations.

unsigned getGlobalBaseReg(MachineFunction *MF) const

Return a virtual register initialized with the global base register value.

Definition M68kInstrInfo.cpp:876

const M68kSubtarget & Subtarget

bool ExpandMOVI(MachineInstrBuilder &MIB, MVT MVTSize) const

Move immediate to register.

Definition M68kInstrInfo.cpp:353

bool ExpandMOVSZX_RR(MachineInstrBuilder &MIB, bool IsSigned, MVT MVTDst, MVT MVTSrc) const

Move from register and extend.

Definition M68kInstrInfo.cpp:472

const M68kRegisterInfo & getRegisterInfo() const

TargetInstrInfo is a superset of MRegister info.

const M68kRegisterInfo RI

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override

Definition M68kInstrInfo.cpp:251

ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override

Definition M68kInstrInfo.cpp:903

bool expandPostRAPseudo(MachineInstr &MI) const override

Definition M68kInstrInfo.cpp:654

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

Definition M68kInstrInfo.cpp:282

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

Definition M68kInstrInfo.cpp:706

std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override

Definition M68kInstrInfo.cpp:898

bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const

Definition M68kInstrInfo.cpp:85

bool isPCRelRegisterOperandLegal(const MachineOperand &MO) const override

Definition M68kInstrInfo.cpp:681

bool ExpandMOVX_RR(MachineInstrBuilder &MIB, MVT MVTDst, MVT MVTSrc) const

Move across register classes without extension.

Definition M68kInstrInfo.cpp:433

void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

Definition M68kInstrInfo.cpp:839

bool ExpandMOVEM(MachineInstrBuilder &MIB, const MCInstrDesc &Desc, bool IsRM) const

Expand all MOVEM pseudos into real MOVEMs.

Definition M68kInstrInfo.cpp:593

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

Definition M68kInstrInfo.cpp:855

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

Definition M68kInstrInfo.cpp:259

bool ExpandPUSH_POP(MachineInstrBuilder &MIB, const MCInstrDesc &Desc, bool IsPush) const

Push/Pop to/from stack.

Definition M68kInstrInfo.cpp:559

M68kInstrInfo(const M68kSubtarget &STI)

Definition M68kInstrInfo.cpp:45

void AddZExt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned Reg, MVT From, MVT To) const

Add appropriate ZExt nodes.

Definition M68kInstrInfo.cpp:332

bool ExpandCCR(MachineInstrBuilder &MIB, bool IsToCCR) const

Moves to/from CCR.

Definition M68kInstrInfo.cpp:575

bool ExpandMOVSZX_RM(MachineInstrBuilder &MIB, bool IsSigned, const MCInstrDesc &Desc, MVT MVTDst, MVT MVTSrc) const

Move from memory and extend.

Definition M68kInstrInfo.cpp:522

bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const override

Definition M68kInstrInfo.cpp:829

void AddSExt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned Reg, MVT From, MVT To) const

Add appropriate SExt nodes.

Definition M68kInstrInfo.cpp:315

void setGlobalBaseReg(unsigned Reg)

unsigned getGlobalBaseReg() const

const M68kInstrInfo * getInstrInfo() const override

Describe properties that are true of each instruction in the target description file.

LLVM_ABI DebugLoc findDebugLoc(instr_iterator MBBI)

Find the next valid DebugLoc starting at MBBI, skipping any debug instructions.

MachineInstrBundleIterator< MachineInstr > iterator

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

int64_t getObjectSize(int ObjectIdx) const

Return the size of the specified object.

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Ty * getInfo()

getInfo - Keep track of various per-function pieces of information for backends that would like to do...

const MachineBasicBlock & front() const

const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const

const MachineInstrBuilder & copyImplicitOps(const MachineInstr &OtherMI) const

Copy all the implicit operands from OtherMI onto this one.

MachineInstr * getInstr() const

If conversion operators fail, use this method to get the MachineInstr explicitly.

Representation of each machine instruction.

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

LLVM_ABI MachineInstr * removeFromParent()

Unlink 'this' from the containing basic block, and return it without deleting it.

const MachineBasicBlock * getParent() const

LLVM_ABI void setDesc(const MCInstrDesc &TID)

Replace the instruction descriptor (thus opcode) of the current instruction with a new one.

const DebugLoc & getDebugLoc() const

Returns the debug location id of this MachineInstr.

LLVM_ABI void eraseFromParent()

Unlink 'this' from the containing basic block and delete it.

const MachineOperand & getOperand(unsigned i) const

MachineOperand class - Representation of each machine instruction operand.

LLVM_ABI unsigned getOperandNo() const

Returns the index of this operand in the instruction that it belongs to.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

LLVM_ABI void setReg(Register Reg)

Change the register this operand corresponds to.

MachineInstr * getParent()

getParent - Return the instruction that this operand belongs to.

static MachineOperand CreateImm(int64_t Val)

getReg - Returns the register number.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

LLVM_ABI bool match(StringRef String, SmallVectorImpl< StringRef > *Matches=nullptr, std::string *Error=nullptr) const

matches - Match the regex against a given String.

Wrapper class representing virtual and physical registers.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

StringRef - Represent a constant reference to a string, i.e.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

This namespace holds all of the target specific flags that instruction info tracks.

@ MO_GOTPCREL

On a symbol operand this indicates that the immediate is offset to the GOT entry for the symbol name ...

Define some predicates that are used for node matching.

static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0)

addFrameReference - This function is used to add a reference to the base of an abstract object on the...

static M68k::CondCode GetCondFromBranchOpc(unsigned Opcode)

@ Implicit

Not emitted register (e.g. carry, or temporary result).

@ Undef

Value of the register doesn't matter.

This is an optimization pass for GlobalISel generic memory operations.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

detail::scope_exit< std::decay_t< Callable > > make_scope_exit(Callable &&F)

FunctionPass * createM68kGlobalBaseRegPass()

This pass initializes a global base register for PIC on M68k.

Definition M68kInstrInfo.cpp:964

MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)

decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

FunctionAddr VTableAddr Count

constexpr bool isUInt(uint64_t x)

Checks if an unsigned integer fits into the given bit width.

@ Ref

The access may reference the value stored in memory.

unsigned getKillRegState(bool B)

ArrayRef(const T &OneElt) -> ArrayRef< T >