Scheduler.h Source File (original) (raw)

14#ifndef LLVM_MCA_HARDWAREUNITS_SCHEDULER_H

15#define LLVM_MCA_HARDWAREUNITS_SCHEDULER_H

25namespace llvm {

26namespace mca {

29public:

38};

44 int computeRank(const InstRef &Lhs) const {

46 }

48public:

53 int LhsRank = computeRank(Lhs);

54 int RhsRank = computeRank(Rhs);

58 if (LhsRank == RhsRank)

60 return LhsRank < RhsRank;

61 }

62};

75 std::unique_ptr Strategy;

78 std::unique_ptr Resources;

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112 std::vector WaitSet;

113 std::vector PendingSet;

114 std::vector ReadySet;

115 std::vector IssuedSet;

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126 unsigned NumDispatchedToThePendingSet;

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130 bool HadTokenStall;

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135 LLVM_ABI void initializeStrategy(std::unique_ptr S);

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138 void issueInstructionImpl(

140 SmallVectorImpl<std::pair<ResourceRef, ReleaseAtCycles>> &Pipes);

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157public:

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162 std::unique_ptr SelectStrategy)

164 std::move(SelectStrategy)) {}

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167 std::unique_ptr SelectStrategy)

168 : LSU(Lsu), Resources(std::move(RM)), BusyResourceUnits(0),

169 NumDispatchedToThePendingSet(0), HadTokenStall(false) {

170 initializeStrategy(std::move(SelectStrategy));

171 }

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206 SmallVectorImpl<std::pair<ResourceRef, ReleaseAtCycles>> &Used,

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235 return Resources->resolveResourceMask(Mask);

236 }

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263#ifndef NDEBUG

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265 void dump() const;

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275#endif

276};

277}

278}

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280#endif

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

This file defines a base class for describing a simulated hardware unit.

A Load/Store unit class that models load/store queues and that implements a simple weak memory consis...

Legalize the Machine IR a function s Machine IR

The classes here represent processor resource units and their management strategy.

This file defines the SmallVector class.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

DefaultSchedulerStrategy()=default

bool compare(const InstRef &Lhs, const InstRef &Rhs) const override

Returns true if Lhs should take priority over Rhs.

Definition Scheduler.h:52

~DefaultSchedulerStrategy() override

An InstRef contains both a SourceMgr index and Instruction pair.

Instruction * getInstruction()

unsigned getSourceIndex() const

unsigned getNumUsers() const

Abstract base interface for LS (load/store) units in llvm-mca.

SchedulerStrategy()=default

virtual ~SchedulerStrategy()

virtual bool compare(const InstRef &Lhs, const InstRef &Rhs) const =0

Returns true if Lhs should take priority over Rhs.

Status

Definition Scheduler.h:174

@ SC_LOAD_QUEUE_FULL

Definition Scheduler.h:176

@ SC_AVAILABLE

Definition Scheduler.h:175

@ SC_STORE_QUEUE_FULL

Definition Scheduler.h:177

@ SC_DISPATCH_GROUP_STALL

Definition Scheduler.h:179

@ SC_BUFFERS_FULL

Definition Scheduler.h:178

LLVM_ABI InstRef select()

Select the next instruction to issue from the ReadySet.

unsigned getResourceID(uint64_t Mask) const

Convert a resource mask into a valid llvm processor resource identifier.

Definition Scheduler.h:234

LLVM_ABI void issueInstruction(InstRef &IR, SmallVectorImpl< std::pair< ResourceRef, ReleaseAtCycles > > &Used, SmallVectorImpl< InstRef > &Pending, SmallVectorImpl< InstRef > &Ready)

Issue an instruction and populates a vector of used pipeline resources, and a vector of instructions ...

Scheduler(std::unique_ptr< ResourceManager > RM, LSUnitBase &Lsu, std::unique_ptr< SchedulerStrategy > SelectStrategy)

Definition Scheduler.h:166

LLVM_ABI Status isAvailable(const InstRef &IR)

Check if the instruction in 'IR' can be dispatched during this cycle.

LLVM_ABI void analyzeDataDependencies(SmallVectorImpl< InstRef > &RegDeps, SmallVectorImpl< InstRef > &MemDeps)

This method is called by the ExecuteStage at the end of each cycle to identify bottlenecks caused by ...

Scheduler(const MCSchedModel &Model, LSUnitBase &Lsu, std::unique_ptr< SchedulerStrategy > SelectStrategy)

Definition Scheduler.h:161

LLVM_ABI bool dispatch(InstRef &IR)

Reserves buffer and LSUnit queue resources that are necessary to issue this instruction.

LLVM_ABI void cycleEvent(SmallVectorImpl< ResourceRef > &Freed, SmallVectorImpl< InstRef > &Executed, SmallVectorImpl< InstRef > &Pending, SmallVectorImpl< InstRef > &Ready)

This routine notifies the Scheduler that a new cycle just started.

LLVM_ABI bool mustIssueImmediately(const InstRef &IR) const

Returns true if IR has to be issued immediately, or if IR is a zero latency instruction.

LLVM_ABI uint64_t analyzeResourcePressure(SmallVectorImpl< InstRef > &Insts)

Returns a mask of busy resources, and populates vector Insts with instructions that could not be issu...

bool isReadySetEmpty() const

Definition Scheduler.h:243

void instructionCheck(const InstRef &IR) const

Definition Scheduler.h:270

Scheduler(const MCSchedModel &Model, LSUnitBase &Lsu)

Definition Scheduler.h:158

bool hadTokenStall() const