MCInstrDesc.h Source File (original) (raw)

14#ifndef LLVM_MC_MCINSTRDESC_H

15#define LLVM_MC_MCINSTRDESC_H

21namespace llvm {

22class MCRegisterInfo;

24class MCInst;

30namespace MCOI {

36 TIED_TO = 0,

37 EARLY_CLOBBER

41#define MCOI_TIED_TO(op) \

42 ((1 << MCOI::TIED_TO) | ((op) << (4 + MCOI::TIED_TO * 4)))

44#define MCOI_EARLY_CLOBBER \

45 (1 << MCOI::EARLY_CLOBBER)

79};

81}

86public:

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134 assert(isGenericImm() && "non-generic immediates don't have an index");

136 }

137};

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143namespace MCID {

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190};

191}

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199public:

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205 unsigned short Opcode;

206 unsigned short NumOperands;

207 unsigned char NumDefs;

208 unsigned char Size;

209 unsigned short SchedClass;

212 unsigned short ImplicitOffset;

213 unsigned short OpInfoOffset;

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222 (operands()[OpNum].Constraints & (1 << Constraint))) {

223 unsigned ValuePos = 4 + Constraint * 4;

224 return (int)(operands()[OpNum].Constraints >> ValuePos) & 0x0f;

225 }

226 return -1;

227 }

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240 auto OpInfo = reinterpret_cast<const MCOperandInfo *>(this + Opcode + 1);

242 }

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566 auto ImplicitOps =

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580 auto ImplicitOps =

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611 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)

612 if (operands()[i].isPredicate())

613 return i;

614 }

615 return -1;

616 }

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622};

623

624}

625

626#endif

unsigned const MachineRegisterInfo * MRI

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Instances of this class represent a single low-level machine instruction.

Describe properties that are true of each instruction in the target description file.

unsigned char NumImplicitUses

unsigned getSchedClass() const

Return the scheduling class for this instruction.

uint64_t getFlags() const

Return flags of this instruction.

unsigned getNumOperands() const

Return the number of declared MachineOperands for this MachineInstruction.

unsigned char NumImplicitDefs

ArrayRef< MCOperandInfo > operands() const

bool isInsertSubregLike() const

Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions.

bool mayStore() const

Return true if this instruction could possibly modify memory.

bool isBitcast() const

Return true if this instruction is a bitcast instruction.

bool isIndirectBranch() const

Return true if this is an indirect branch, such as a branch through a register.

int findFirstPredOperandIdx() const

Find the index of the first operand in the operand list that is used to represent the predicate.

unsigned short ImplicitOffset

bool usesCustomInsertionHook() const

Return true if this instruction requires custom insertion support when the DAG scheduler is inserting...

bool isBarrier() const

Returns true if the specified instruction stops control flow from executing the instruction immediate...

bool isSelect() const

Return true if this is a select instruction.

bool isAsCheapAsAMove() const

Returns true if this instruction has the same cost (or less) than a move instruction.

bool mayLoad() const

Return true if this instruction could possibly read memory.

bool hasOptionalDef() const

Set if this instruction has an optional definition, e.g.

unsigned getNumDefs() const

Return the number of MachineOperands that are register definitions.

bool isConvergent() const

Return true if this instruction is convergent.

bool canFoldAsLoad() const

Return true for instructions that can be folded as memory operands in other instructions.

bool isMoveReg() const

Return true if the instruction is a register to register move.

bool hasDefOfPhysReg(const MCInst &MI, MCRegister Reg, const MCRegisterInfo &RI) const

Return true if this instruction defines the specified physical register, either explicitly or implici...

unsigned short NumOperands

bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const

Return true if this is a branch or an instruction which directly writes to the program counter.

bool isRematerializable() const

Returns true if this instruction is a candidate for remat.

bool isCompare() const

Return true if this instruction is a comparison.

bool isMetaInstruction() const

Return true if this is a meta instruction that doesn't produce any output in the form of executable i...

bool isBranch() const

Returns true if this is a conditional, unconditional, or indirect branch.

bool variadicOpsAreDefs() const

Return true if variadic operands of this instruction are definitions.

int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const

Returns the value of the specified operand constraint if it is present.

bool hasExtraDefRegAllocReq() const

Returns true if this instruction def operands have special register allocation requirements that are ...

bool mayRaiseFPException() const

Return true if this instruction may raise a floating-point exception.

ArrayRef< MCPhysReg > implicit_defs() const

Return a list of registers that are potentially written by any instance of this machine instruction.

bool isUnconditionalBranch() const

Return true if this is a branch which always transfers control flow to some other block.

bool isPredicable() const

Return true if this instruction has a predicate operand that controls execution.

bool isCommutable() const

Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z,...

bool isNotDuplicable() const

Return true if this instruction cannot be safely duplicated.

bool hasUnmodeledSideEffects() const

Return true if this instruction has side effects that are not modeled by other flags.

bool hasPostISelHook() const

Return true if this instruction requires adjustment after instruction selection by calling a target h...

bool isExtractSubregLike() const

Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions.

bool isCall() const

Return true if the instruction is a call.

bool isConvertibleTo3Addr() const

Return true if this is a 2-address instruction which can be changed into a 3-address instruction if n...

unsigned short SchedClass

bool isTerminator() const

Returns true if this instruction part of the terminator for a basic block.

bool hasDelaySlot() const

Returns true if the specified instruction has a delay slot which must be filled by the code generator...

bool isReturn() const

Return true if the instruction is a return.

unsigned getSize() const

Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot b...

bool isAdd() const

Return true if the instruction is an add instruction.

bool isVariadic() const

Return true if this instruction can have a variable number of operands.

bool isTrap() const

Return true if this instruction is a trap.

bool hasImplicitUseOfPhysReg(MCRegister Reg) const

Return true if this instruction implicitly uses the specified physical register.

bool isMoveImmediate() const

Return true if this instruction is a move immediate (including conditional moves) instruction.

bool isPreISelOpcode() const

bool isConditionalBranch() const

Return true if this is a branch which may fall through to the next instruction or may transfer contro...

ArrayRef< MCPhysReg > implicit_uses() const

Return a list of registers that are potentially read by any instance of this machine instruction.

bool isAuthenticated() const

Return true if this instruction authenticates a pointer (e.g.

unsigned getOpcode() const

Return the opcode number for this descriptor.

bool isPseudo() const

Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.

unsigned short OpInfoOffset

bool isRegSequenceLike() const

Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions.

bool hasExtraSrcRegAllocReq() const

Returns true if this instruction source operands have special register allocation requirements that a...

bool hasImplicitDefOfPhysReg(MCRegister Reg, const MCRegisterInfo *MRI=nullptr) const

Return true if this instruction implicitly defines the specified physical register.

This holds information about one operand of a machine instruction, indicating the register class for ...

unsigned getGenericTypeIndex() const

bool isOptionalDef() const

Set if this operand is a optional def.

unsigned getGenericImmIndex() const

bool isBranchTarget() const

Set if this operand is a branch target.

uint16_t Constraints

Operand constraints (see OperandConstraint enum).

uint8_t OperandType

Information about the type of the operand.

bool isLookupPtrRegClass() const

Set if this operand is a pointer value and it requires a callback to look up its register class.

uint8_t Flags

These are flags from the MCOI::OperandFlags enum.

bool isGenericImm() const

int16_t RegClass

This specifies the register class enumeration of the operand if the operand is a register.

bool isGenericType() const

bool isPredicate() const

Set if this is one of the operands that made up of the predicate operand that controls an isPredicabl...

MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...

Wrapper class representing physical registers. Should be passed by value.

This provides a very simple, boring adaptor for a begin and end iterator into a range type.

Flag

These should be considered private to the implementation of the MCInstrDesc class.

OperandFlags

These are flags set on operands, but should be considered private, all access should go through the M...

OperandConstraint

Operand constraints.

OperandType

Operands are tagged with one of the values of this enum.

@ OPERAND_FIRST_GENERIC_IMM

@ OPERAND_LAST_GENERIC_IMM

This is an optimization pass for GlobalISel generic memory operations.

bool is_contained(R &&Range, const E &Element)

Returns true if Element is found in Range.