LLVM: llvm::MCInstrDesc Class Reference (original) (raw)
Describe properties that are true of each instruction in the target description file. More...
#include "[llvm/MC/MCInstrDesc.h](MCInstrDesc%5F8h%5Fsource.html)"
| Public Member Functions | |
|---|---|
| int | getOperandConstraint (unsigned OpNum, MCOI::OperandConstraint Constraint) const |
| Returns the value of the specified operand constraint if it is present. | |
| unsigned | getOpcode () const |
| Return the opcode number for this descriptor. | |
| unsigned | getNumOperands () const |
| Return the number of declared MachineOperands for this MachineInstruction. | |
| ArrayRef< MCOperandInfo > | operands () const |
| unsigned | getNumDefs () const |
| Return the number of MachineOperands that are register definitions. | |
| uint64_t | getFlags () const |
| Return flags of this instruction. | |
| bool | isPreISelOpcode () const |
| bool | isVariadic () const |
| Return true if this instruction can have a variable number of operands. | |
| bool | hasOptionalDef () const |
| Set if this instruction has an optional definition, e.g. | |
| bool | isPseudo () const |
| Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction. | |
| bool | isMetaInstruction () const |
| Return true if this is a meta instruction that doesn't produce any output in the form of executable instructions. | |
| bool | isReturn () const |
| Return true if the instruction is a return. | |
| bool | isAdd () const |
| Return true if the instruction is an add instruction. | |
| bool | isTrap () const |
| Return true if this instruction is a trap. | |
| bool | isMoveReg () const |
| Return true if the instruction is a register to register move. | |
| bool | isCall () const |
| Return true if the instruction is a call. | |
| bool | isBarrier () const |
| Returns true if the specified instruction stops control flow from executing the instruction immediately following it. | |
| bool | isTerminator () const |
| Returns true if this instruction part of the terminator for a basic block. | |
| bool | isBranch () const |
| Returns true if this is a conditional, unconditional, or indirect branch. | |
| bool | isIndirectBranch () const |
| Return true if this is an indirect branch, such as a branch through a register. | |
| bool | isConditionalBranch () const |
| Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block. | |
| bool | isUnconditionalBranch () const |
| Return true if this is a branch which always transfers control flow to some other block. | |
| LLVM_ABI bool | mayAffectControlFlow (const MCInst &MI, const MCRegisterInfo &RI) const |
| Return true if this is a branch or an instruction which directly writes to the program counter. | |
| bool | isPredicable () const |
| Return true if this instruction has a predicate operand that controls execution. | |
| bool | isCompare () const |
| Return true if this instruction is a comparison. | |
| bool | isMoveImmediate () const |
| Return true if this instruction is a move immediate (including conditional moves) instruction. | |
| bool | isBitcast () const |
| Return true if this instruction is a bitcast instruction. | |
| bool | isSelect () const |
| Return true if this is a select instruction. | |
| bool | isNotDuplicable () const |
| Return true if this instruction cannot be safely duplicated. | |
| bool | hasDelaySlot () const |
| Returns true if the specified instruction has a delay slot which must be filled by the code generator. | |
| bool | canFoldAsLoad () const |
| Return true for instructions that can be folded as memory operands in other instructions. | |
| bool | isRegSequenceLike () const |
| Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions. | |
| bool | isExtractSubregLike () const |
| Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions. | |
| bool | isInsertSubregLike () const |
| Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions. | |
| bool | isConvergent () const |
| Return true if this instruction is convergent. | |
| bool | variadicOpsAreDefs () const |
| Return true if variadic operands of this instruction are definitions. | |
| bool | isAuthenticated () const |
| Return true if this instruction authenticates a pointer (e.g. | |
| bool | mayLoad () const |
| Return true if this instruction could possibly read memory. | |
| bool | mayStore () const |
| Return true if this instruction could possibly modify memory. | |
| bool | mayRaiseFPException () const |
| Return true if this instruction may raise a floating-point exception. | |
| bool | hasUnmodeledSideEffects () const |
| Return true if this instruction has side effects that are not modeled by other flags. | |
| bool | isCommutable () const |
| Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged. | |
| bool | isConvertibleTo3Addr () const |
| Return true if this is a 2-address instruction which can be changed into a 3-address instruction if needed. | |
| bool | usesCustomInsertionHook () const |
| Return true if this instruction requires custom insertion support when the DAG scheduler is inserting it into a machine basic block. | |
| bool | hasPostISelHook () const |
| Return true if this instruction requires adjustment after instruction selection by calling a target hook. | |
| bool | isRematerializable () const |
| Returns true if this instruction is a candidate for remat. | |
| bool | isAsCheapAsAMove () const |
| Returns true if this instruction has the same cost (or less) than a move instruction. | |
| bool | hasExtraSrcRegAllocReq () const |
| Returns true if this instruction source operands have special register allocation requirements that are not captured by the operand register classes. | |
| bool | hasExtraDefRegAllocReq () const |
| Returns true if this instruction def operands have special register allocation requirements that are not captured by the operand register classes. | |
| ArrayRef< MCPhysReg > | implicit_uses () const |
| Return a list of registers that are potentially read by any instance of this machine instruction. | |
| ArrayRef< MCPhysReg > | implicit_defs () const |
| Return a list of registers that are potentially written by any instance of this machine instruction. | |
| bool | hasImplicitUseOfPhysReg (MCRegister Reg) const |
| Return true if this instruction implicitly uses the specified physical register. | |
| LLVM_ABI bool | hasImplicitDefOfPhysReg (MCRegister Reg, const MCRegisterInfo *MRI=nullptr) const |
| Return true if this instruction implicitly defines the specified physical register. | |
| unsigned | getSchedClass () const |
| Return the scheduling class for this instruction. | |
| unsigned | getSize () const |
| Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot be known from the opcode. | |
| int | findFirstPredOperandIdx () const |
| Find the index of the first operand in the operand list that is used to represent the predicate. | |
| LLVM_ABI bool | hasDefOfPhysReg (const MCInst &MI, MCRegister Reg, const MCRegisterInfo &RI) const |
| Return true if this instruction defines the specified physical register, either explicitly or implicitly. |
| Public Attributes | |
|---|---|
| unsigned short | Opcode |
| unsigned short | NumOperands |
| unsigned char | NumDefs |
| unsigned char | Size |
| unsigned short | SchedClass |
| unsigned char | NumImplicitUses |
| unsigned char | NumImplicitDefs |
| unsigned short | OpInfoOffset |
| unsigned int | ImplicitOffset |
| uint64_t | Flags |
| uint64_t | TSFlags |
Describe properties that are true of each instruction in the target description file.
This captures information about side effects, register use and many other things. There is one instance of this struct for each target instruction class, and the MachineInstr class points to this struct directly to describe itself.
Definition at line 199 of file MCInstrDesc.h.
◆ canFoldAsLoad()
| bool llvm::MCInstrDesc::canFoldAsLoad ( ) const | inline |
|---|
Return true for instructions that can be folded as memory operands in other instructions.
The most common use for this is instructions that are simple loads from memory that don't modify the loaded value in any way, but it can also be used for instructions that can be expressed as constant-pool loads, such as V_SETALLONES on x86, to allow them to be folded when it is beneficial. This should only be set on instructions that return a value in their only virtual register definition.
Definition at line 371 of file MCInstrDesc.h.
References Flags, and llvm::MCID::FoldableAsLoad.
◆ findFirstPredOperandIdx()
| int llvm::MCInstrDesc::findFirstPredOperandIdx ( ) const | inline |
|---|
◆ getFlags()
| uint64_t llvm::MCInstrDesc::getFlags ( ) const | inline |
|---|
◆ getNumDefs()
| unsigned llvm::MCInstrDesc::getNumDefs ( ) const | inline |
|---|
◆ getNumOperands()
| unsigned llvm::MCInstrDesc::getNumOperands ( ) const | inline |
|---|
Return the number of declared MachineOperands for this MachineInstruction.
Note that variadic (isVariadic() returns true) instructions may have additional operands at the end of the list, and note that the machine instruction may include implicit register def/uses as well.
Definition at line 238 of file MCInstrDesc.h.
References NumOperands.
Referenced by llvm::ScheduleDAGInstrs::addPhysRegDataDeps(), llvm::ScheduleDAGInstrs::addSchedBarrierDeps(), llvm::AMDGPU::VOPD::ComponentProps::ComponentProps(), llvm::SIInstrInfo::expandPostRAPseudo(), findFirstPredOperandIdx(), llvm::ARMBaseInstrInfo::foldImmediate(), getTargetMBB(), hasType(), lowerRISCVVMachineInstrToMCInst(), llvm::PPCInstrInfo::onlyFoldImmediate(), llvm::ARMBaseInstrInfo::optimizeSelect(), llvm::LanaiInstrInfo::optimizeSelect(), llvm::RISCVInstrInfo::optimizeSelect(), llvm::SPIRVInstPrinter::printInst(), llvm::SPIRVInstPrinter::printOpDecorate(), llvm::SPIRVInstPrinter::printOpExtInst(), llvm::SPIRVInstPrinter::printUnknownType(), and llvm::mca::verifyOperands().
◆ getOpcode()
| unsigned llvm::MCInstrDesc::getOpcode ( ) const | inline |
|---|
◆ getOperandConstraint()
◆ getSchedClass()
| unsigned llvm::MCInstrDesc::getSchedClass ( ) const | inline |
|---|
Return the scheduling class for this instruction.
The scheduling class is an index into the InstrItineraryData table. This returns zero if there is no known scheduling information for the instruction.
Definition at line 603 of file MCInstrDesc.h.
References SchedClass.
Referenced by llvm::DFAPacketizer::canReserveResources(), llvm::MCSchedModel::computeInstrLatency(), llvm::HexagonInstrInfo::genAllInsnTimingClasses(), llvm::HexagonMCInstrInfo::getCVIResources(), llvm::TargetInstrInfo::getInstrLatency(), llvm::ARMBaseInstrInfo::getOperandLatency(), llvm::TargetInstrInfo::getOperandLatency(), llvm::HexagonMCInstrInfo::getOtherReservedSlots(), llvm::MCSchedModel::getReciprocalThroughput(), llvm::HexagonMCInstrInfo::getUnits(), llvm::HexagonPacketizerList::ignorePseudoInstruction(), and llvm::DFAPacketizer::reserveResources().
◆ getSize()
| unsigned llvm::MCInstrDesc::getSize ( ) const | inline |
|---|
◆ hasDefOfPhysReg()
◆ hasDelaySlot()
| bool llvm::MCInstrDesc::hasDelaySlot ( ) const | inline |
|---|
◆ hasExtraDefRegAllocReq()
| bool llvm::MCInstrDesc::hasExtraDefRegAllocReq ( ) const | inline |
|---|
Returns true if this instruction def operands have special register allocation requirements that are not captured by the operand register classes.
e.g. ARM::LDRD's two def registers must be an even / odd pair, ARM::LDM registers have to be in ascending order. Post-register allocation passes should not attempt to change allocations for definitions of instructions with this flag.
Definition at line 557 of file MCInstrDesc.h.
References llvm::MCID::ExtraDefRegAllocReq, and Flags.
◆ hasExtraSrcRegAllocReq()
| bool llvm::MCInstrDesc::hasExtraSrcRegAllocReq ( ) const | inline |
|---|
Returns true if this instruction source operands have special register allocation requirements that are not captured by the operand register classes.
e.g. ARM::STRD's two source registers must be an even / odd pair, ARM::STM registers have to be in ascending order. Post-register allocation passes should not attempt to change allocations for sources of instructions with this flag.
Definition at line 547 of file MCInstrDesc.h.
References llvm::MCID::ExtraSrcRegAllocReq, and Flags.
◆ hasImplicitDefOfPhysReg()
◆ hasImplicitUseOfPhysReg()
| bool llvm::MCInstrDesc::hasImplicitUseOfPhysReg ( MCRegister Reg) const | inline |
|---|
◆ hasOptionalDef()
| bool llvm::MCInstrDesc::hasOptionalDef ( ) const | inline |
|---|
◆ hasPostISelHook()
| bool llvm::MCInstrDesc::hasPostISelHook ( ) const | inline |
|---|
Return true if this instruction requires adjustment after instruction selection by calling a target hook.
For example, this can be used to fill in ARM 's' optional operand depending on whether the conditional flag register is used.
Definition at line 519 of file MCInstrDesc.h.
References Flags, and llvm::MCID::HasPostISelHook.
◆ hasUnmodeledSideEffects()
| bool llvm::MCInstrDesc::hasUnmodeledSideEffects ( ) const | inline |
|---|
Return true if this instruction has side effects that are not modeled by other flags.
This does not return true for instructions whose effects are captured by:
- Their operand list and implicit definition/use list. Register use/def info is explicit for instructions.
- Memory accesses. Use mayLoad/mayStore.
- Calling, branching, returning: use isCall/isReturn/isBranch.
Examples of side effects would be modifying 'invisible' machine state like a control register, flushing a cache, modifying a register invisible to LLVM, etc.
Definition at line 465 of file MCInstrDesc.h.
References Flags, and llvm::MCID::UnmodeledSideEffects.
Referenced by llvm::mca::InstrBuilder::createInstruction().
◆ implicit_defs()
Return a list of registers that are potentially written by any instance of this machine instruction.
For example, on X86, many instructions implicitly set the flags register. In this case, they are marked as setting the FLAGS. Likewise, many instructions always deposit their result in a physical register. For example, the X86 divide instruction always deposits the quotient and remainder in the EAX/EDX registers. For that instruction, this will return a list containing the EAX/EDX/EFLAGS registers.
Definition at line 581 of file MCInstrDesc.h.
References ImplicitOffset, NumImplicitDefs, NumImplicitUses, and Opcode.
Referenced by hasImplicitDefOfPhysReg(), llvm::PPCInstrInfo::optimizeCompareInstr(), and llvm::DWARFCFIAnalysis::update().
◆ implicit_uses()
Return a list of registers that are potentially read by any instance of this machine instruction.
For example, on X86, the "adc" instruction adds two register operands and adds the carry bit in from the flags register. In this case, the instruction is marked as implicitly reading the flags. Likewise, the variable shift instruction on X86 is marked as implicitly reading the 'CL' register, which it always does.
Definition at line 567 of file MCInstrDesc.h.
References ImplicitOffset, NumImplicitUses, and Opcode.
Referenced by llvm::SIInstrInfo::expandPostRAPseudo(), hasImplicitUseOfPhysReg(), llvm::PPCInstrInfo::optimizeCompareInstr(), and llvm::DWARFCFIAnalysis::update().
◆ isAdd()
| bool llvm::MCInstrDesc::isAdd ( ) const | inline |
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◆ isAsCheapAsAMove()
| bool llvm::MCInstrDesc::isAsCheapAsAMove ( ) const | inline |
|---|
Returns true if this instruction has the same cost (or less) than a move instruction.
This is useful during certain types of optimizations (e.g., remat during two-address conversion or machine licm) where we would like to remat or hoist the instruction, but not if it costs more than moving the instruction into the appropriate register. Note, we are not marking copies from and to the same register class with this flag.
This method could be called by interface TargetInstrInfo::isAsCheapAsAMove for different subtargets.
Definition at line 539 of file MCInstrDesc.h.
References llvm::MCID::CheapAsAMove, and Flags.
◆ isAuthenticated()
| bool llvm::MCInstrDesc::isAuthenticated ( ) const | inline |
|---|
Return true if this instruction authenticates a pointer (e.g.
LDRAx/BRAx from ARMv8.3, which perform loads/branches with authentication).
An authenticated instruction may fail in an ABI-defined manner when operating on an invalid signed pointer.
Definition at line 429 of file MCInstrDesc.h.
References llvm::MCID::Authenticated, and Flags.
◆ isBarrier()
| bool llvm::MCInstrDesc::isBarrier ( ) const | inline |
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◆ isBitcast()
| bool llvm::MCInstrDesc::isBitcast ( ) const | inline |
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◆ isBranch()
| bool llvm::MCInstrDesc::isBranch ( ) const | inline |
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◆ isCall()
| bool llvm::MCInstrDesc::isCall ( ) const | inline |
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◆ isCommutable()
| bool llvm::MCInstrDesc::isCommutable ( ) const | inline |
|---|
Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged.
If this flag is set, then the TargetInstrInfo::commuteInstruction method may be used to hack on the instruction.
Note that this flag may be set on instructions that are only commutable sometimes. In these cases, the call to commuteInstruction will fail. Also note that some instructions require non-trivial modification to commute them.
Definition at line 483 of file MCInstrDesc.h.
References llvm::MCID::Commutable, and Flags.
◆ isCompare()
| bool llvm::MCInstrDesc::isCompare ( ) const | inline |
|---|
◆ isConditionalBranch()
| bool llvm::MCInstrDesc::isConditionalBranch ( ) const | inline |
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◆ isConvergent()
| bool llvm::MCInstrDesc::isConvergent ( ) const | inline |
|---|
Return true if this instruction is convergent.
Convergent instructions may not be made control-dependent on any additional values.
Definition at line 417 of file MCInstrDesc.h.
References llvm::MCID::Convergent, and Flags.
◆ isConvertibleTo3Addr()
| bool llvm::MCInstrDesc::isConvertibleTo3Addr ( ) const | inline |
|---|
Return true if this is a 2-address instruction which can be changed into a 3-address instruction if needed.
Doing this transformation can be profitable in the register allocator, because it means that the instruction can use a 2-address form if possible, but degrade into a less efficient form if the source and dest register cannot be assigned to the same register. For example, this allows the x86 backend to turn a "shl reg, 3" instruction into an LEA instruction, which is the same speed as the shift but has bigger code size.
If this returns true, then the target must implement the TargetInstrInfo::convertToThreeAddress method for this instruction, which is allowed to fail if the transformation isn't valid for this specific instruction (e.g. shl reg, 4 on x86).
Definition at line 499 of file MCInstrDesc.h.
References llvm::MCID::ConvertibleTo3Addr, and Flags.
◆ isExtractSubregLike()
| bool llvm::MCInstrDesc::isExtractSubregLike ( ) const | inline |
|---|
Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions.
E.g., on ARM, rX, rY VMOVRRD dZ is equivalent to two EXTRACT_SUBREG: rX = EXTRACT_SUBREG dZ, ssub_0 rY = EXTRACT_SUBREG dZ, ssub_1
Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getExtractSubregLikeInputs has to be override accordingly.
Definition at line 396 of file MCInstrDesc.h.
References llvm::MCID::ExtractSubreg, and Flags.
◆ isIndirectBranch()
| bool llvm::MCInstrDesc::isIndirectBranch ( ) const | inline |
|---|
◆ isInsertSubregLike()
| bool llvm::MCInstrDesc::isInsertSubregLike ( ) const | inline |
|---|
Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions.
E.g., on ARM, dX = VSETLNi32 dY, rZ, Imm is equivalent to a INSERT_SUBREG: dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getInsertSubregLikeInputs has to be override accordingly.
Definition at line 410 of file MCInstrDesc.h.
References Flags, and llvm::MCID::InsertSubreg.
◆ isMetaInstruction()
| bool llvm::MCInstrDesc::isMetaInstruction ( ) const | inline |
|---|
Return true if this is a meta instruction that doesn't produce any output in the form of executable instructions.
Definition at line 274 of file MCInstrDesc.h.
References Flags, and llvm::MCID::Meta.
◆ isMoveImmediate()
| bool llvm::MCInstrDesc::isMoveImmediate ( ) const | inline |
|---|
◆ isMoveReg()
| bool llvm::MCInstrDesc::isMoveReg ( ) const | inline |
|---|
◆ isNotDuplicable()
| bool llvm::MCInstrDesc::isNotDuplicable ( ) const | inline |
|---|
Return true if this instruction cannot be safely duplicated.
For example, if the instruction has a unique labels attached to it, duplicating it would cause multiple definition errors.
Definition at line 358 of file MCInstrDesc.h.
References Flags, and llvm::MCID::NotDuplicable.
◆ isPredicable()
| bool llvm::MCInstrDesc::isPredicable ( ) const | inline |
|---|
◆ isPreISelOpcode()
| bool llvm::MCInstrDesc::isPreISelOpcode ( ) const | inline |
|---|
◆ isPseudo()
| bool llvm::MCInstrDesc::isPseudo ( ) const | inline |
|---|
◆ isRegSequenceLike()
| bool llvm::MCInstrDesc::isRegSequenceLike ( ) const | inline |
|---|
◆ isRematerializable()
| bool llvm::MCInstrDesc::isRematerializable ( ) const | inline |
|---|
Returns true if this instruction is a candidate for remat.
This flag is only used in TargetInstrInfo method isTriviallyRematerializable.
If this flag is set, the isReMaterializableImpl() method is called to verify the instruction is really rematerializable.
Definition at line 526 of file MCInstrDesc.h.
References Flags, and llvm::MCID::Rematerializable.
◆ isReturn()
| bool llvm::MCInstrDesc::isReturn ( ) const | inline |
|---|
◆ isSelect()
| bool llvm::MCInstrDesc::isSelect ( ) const | inline |
|---|
◆ isTerminator()
| bool llvm::MCInstrDesc::isTerminator ( ) const | inline |
|---|
Returns true if this instruction part of the terminator for a basic block.
Typically this is things like return and branch instructions.
Various passes use this to insert code into the bottom of a basic block, but before control flow occurs.
Definition at line 302 of file MCInstrDesc.h.
References Flags, and llvm::MCID::Terminator.
◆ isTrap()
| bool llvm::MCInstrDesc::isTrap ( ) const | inline |
|---|
◆ isUnconditionalBranch()
| bool llvm::MCInstrDesc::isUnconditionalBranch ( ) const | inline |
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◆ isVariadic()
| bool llvm::MCInstrDesc::isVariadic ( ) const | inline |
|---|
◆ mayAffectControlFlow()
◆ mayLoad()
| bool llvm::MCInstrDesc::mayLoad ( ) const | inline |
|---|
◆ mayRaiseFPException()
| bool llvm::MCInstrDesc::mayRaiseFPException ( ) const | inline |
|---|
◆ mayStore()
| bool llvm::MCInstrDesc::mayStore ( ) const | inline |
|---|
◆ operands()
Definition at line 240 of file MCInstrDesc.h.
References llvm::ArrayRef(), NumOperands, Opcode, and OpInfoOffset.
Referenced by llvm::AMDGPU::VOPD::ComponentProps::ComponentProps(), findFirstPredOperandIdx(), llvm::SIInstrInfo::foldImmediate(), getOperandConstraint(), llvm::MachineInstr::getTypeToPrint(), llvm::AMDGPU::hasAny64BitVGPROperands(), hasType(), llvm::SIInstrInfo::isImmOperandLegal(), llvm::SIInstrInfo::isImmOperandLegal(), llvm::SIInstrInfo::isLegalToSwap(), llvm::SIInstrInfo::isOperandLegal(), llvm::SIInstrInfo::legalizeOperandsVOP2(), lowerRISCVVMachineInstrToMCInst(), llvm::PPCInstrInfo::onlyFoldImmediate(), llvm::ARMBaseInstrInfo::optimizeSelect(), llvm::LanaiInstrInfo::optimizeSelect(), and llvm::SPIRVInstPrinter::printInst().
◆ usesCustomInsertionHook()
| bool llvm::MCInstrDesc::usesCustomInsertionHook ( ) const | inline |
|---|
Return true if this instruction requires custom insertion support when the DAG scheduler is inserting it into a machine basic block.
If this is true for the instruction, it basically means that it is a pseudo instruction used at SelectionDAG time that is expanded out into magic code by the target when MachineInstrs are formed.
If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method is used to insert this into the MachineBasicBlock.
Definition at line 511 of file MCInstrDesc.h.
References Flags, and llvm::MCID::UsesCustomInserter.
◆ variadicOpsAreDefs()
| bool llvm::MCInstrDesc::variadicOpsAreDefs ( ) const | inline |
|---|
◆ Flags
Definition at line 215 of file MCInstrDesc.h.
Referenced by canFoldAsLoad(), getFlags(), hasDelaySlot(), hasExtraDefRegAllocReq(), hasExtraSrcRegAllocReq(), hasOptionalDef(), hasPostISelHook(), hasUnmodeledSideEffects(), isAdd(), isAsCheapAsAMove(), isAuthenticated(), isBarrier(), isBitcast(), isBranch(), isCall(), isCommutable(), isCompare(), isConvergent(), isConvertibleTo3Addr(), isExtractSubregLike(), isIndirectBranch(), isInsertSubregLike(), isMetaInstruction(), isMoveImmediate(), isMoveReg(), isNotDuplicable(), isPredicable(), isPreISelOpcode(), isPseudo(), isRegSequenceLike(), isRematerializable(), isReturn(), isSelect(), isTerminator(), isTrap(), isVariadic(), mayLoad(), mayRaiseFPException(), mayStore(), usesCustomInsertionHook(), and variadicOpsAreDefs().
◆ ImplicitOffset
unsigned int llvm::MCInstrDesc::ImplicitOffset
◆ NumDefs
◆ NumImplicitDefs
◆ NumImplicitUses
◆ NumOperands
unsigned short llvm::MCInstrDesc::NumOperands
◆ Opcode
unsigned short llvm::MCInstrDesc::Opcode
◆ OpInfoOffset
unsigned short llvm::MCInstrDesc::OpInfoOffset
◆ SchedClass
unsigned short llvm::MCInstrDesc::SchedClass
◆ Size
◆ TSFlags
Definition at line 216 of file MCInstrDesc.h.
Referenced by llvm::AMDGPU::VOPD::ComponentProps::ComponentProps(), CompressEVEXImpl(), llvm::ARM_MC::evaluateBranchTarget(), llvm::SystemZInstrInfo::foldMemoryOperandImpl(), llvm::HexagonMCInstrInfo::getAddrMode(), getAddrOffset(), llvm::HexagonMCInstrInfo::getExtendableOp(), llvm::HexagonMCInstrInfo::getExtentAlignment(), llvm::HexagonMCInstrInfo::getExtentBits(), llvm::ARMHazardRecognizerFPMLx::getHazardType(), llvm::HexagonMCInstrInfo::getMemAccessSize(), llvm::HexagonMCInstrInfo::getNewValueOp(), llvm::HexagonMCInstrInfo::getNewValueOp2(), llvm::AMDGPU::getTemporalHintType(), llvm::HexagonMCInstrInfo::getType(), llvm::HexagonMCInstrInfo::hasHvxTmp(), llvm::HexagonMCInstrInfo::hasNewValue(), llvm::HexagonMCInstrInfo::hasNewValue2(), llvm::HexagonMCInstrInfo::isAccumulator(), llvm::HexagonMCInstrInfo::isCofMax1(), llvm::HexagonMCInstrInfo::isCofRelax1(), llvm::HexagonMCInstrInfo::isCofRelax2(), llvm::HexagonMCInstrInfo::isCVINew(), llvm::HexagonInstrInfo::isExtendable(), llvm::HexagonMCInstrInfo::isExtendable(), llvm::HexagonMCInstrInfo::isExtended(), llvm::HexagonMCInstrInfo::isExtentSigned(), llvm::HexagonMCInstrInfo::isFloat(), llvm::HexagonMCInstrInfo::isNewValue(), llvm::HexagonMCInstrInfo::isNewValueStore(), llvm::ARCInstrInfo::isPostIncrement(), llvm::HexagonMCInstrInfo::isPredicated(), llvm::HexagonMCInstrInfo::isPredicatedNew(), llvm::HexagonMCInstrInfo::isPredicatedTrue(), llvm::HexagonMCInstrInfo::isPredicateLate(), isPrefix(), llvm::ARCInstrInfo::isPreIncrement(), llvm::HexagonMCInstrInfo::isRestrictNoSlot1Store(), llvm::HexagonMCInstrInfo::isRestrictSlot1AOK(), llvm::HexagonMCInstrInfo::isSolo(), llvm::HexagonMCInstrInfo::isSoloAX(), llvm::HexagonMCInstrInfo::isVector(), llvm::HexagonMCInstrInfo::prefersSlot3(), and llvm::AMDGPU::supportsScaleOffset().
The documentation for this class was generated from the following files:
- include/llvm/MC/MCInstrDesc.h
- lib/MC/MCInstrDesc.cpp