MCSchedule.h Source File (original) (raw)

14#ifndef LLVM_MC_MCSCHEDULE_H

15#define LLVM_MC_MCSCHEDULE_H

22#include

23#include

25namespace llvm {

27template class ArrayRef;

38 unsigned NumUnits;

39 unsigned SuperIdx;

64};

84};

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127#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

129#endif

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344 "No extra information available for this model");

346 }

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374#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

376#else

377 return "";

378#endif

379 }

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386 unsigned SClass) const;

387

390 const MCInst &Inst) const;

391

396 const MCInstOrMachineInstr &Inst,

398 ResolveVariantSchedClass =

399 [](const MCSchedClassDesc *SCDesc) { return SCDesc; }) const;

400

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404 const MCSchedClassDesc &SCDesc);

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410 const MCInstrInfo &MCII,

411 const MCInst &Inst) const;

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417 unsigned WriteResourceIdx = 0);

418

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421 const MCSchedClassDesc &SCDesc);

422

423

425};

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435 const MCInstOrMachineInstr &Inst,

437 ResolveVariantSchedClass) const {

438 static const int NoInformationAvailable = -1;

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447 if (CPU.empty())

448 return NoInformationAvailable;

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454 unsigned SCClass = Desc.getSchedClass();

455

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458 for (unsigned Idx = 0, IdxEnd = Inst.getNumOperands(); Idx != IdxEnd; ++Idx)

459 if (std::optional OperCycle = IID.getOperandCycle(SCClass, Idx))

461

463 }

464

465 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass();

467 SCDesc = ResolveVariantSchedClass(SCDesc);

468

469 if (!SCDesc || !SCDesc->isValid())

470 return NoInformationAvailable;

471

473}

474

475}

476

477#endif

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Itinerary data supplied by a subtarget to be used by a target.

std::optional< unsigned > getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const

Return the cycle for the given class and operand.

Instances of this class represent a single low-level machine instruction.

Describe properties that are true of each instruction in the target description file.

unsigned getSchedClass() const

Return the scheduling class for this instruction.

Interface to description of machine instruction set.

const MCInstrDesc & get(unsigned Opcode) const

Return the machine instruction descriptor that corresponds to the specified instruction opcode.

Generic base class for all target subtargets.

InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const

Get scheduling itinerary of a CPU.

StringRef - Represent a constant reference to a string, i.e.

A table of densely packed, null-terminated strings indexed by offset.

An efficient, type-erasing, non-owning reference to a callable.

This is an optimization pass for GlobalISel generic memory operations.

ArrayRef(const T &OneElt) -> ArrayRef< T >

An itinerary represents the scheduling information for an instruction.

Define a kind of processor resource that will be modeled by the scheduler.

Definition MCSchedule.h:36

int BufferSize

Definition MCSchedule.h:53

const char * Name

Definition MCSchedule.h:37

bool operator==(const MCProcResourceDesc &Other) const

Definition MCSchedule.h:60

const unsigned * SubUnitsIdxBegin

Definition MCSchedule.h:58

unsigned SuperIdx

Definition MCSchedule.h:39

unsigned NumUnits

Definition MCSchedule.h:38

Specify the number of cycles allowed after instruction issue before a particular use operand reads it...

Definition MCSchedule.h:108

int Cycles

Definition MCSchedule.h:111

unsigned WriteResourceID

Definition MCSchedule.h:110

bool operator==(const MCReadAdvanceEntry &Other) const

Definition MCSchedule.h:113

unsigned UseIdx

Definition MCSchedule.h:109

Specify the cost of a register definition in terms of number of physical register allocated at regist...

Definition MCSchedule.h:156

unsigned RegisterClassID

Definition MCSchedule.h:157

unsigned Cost

Definition MCSchedule.h:158

bool AllowMoveElimination

Definition MCSchedule.h:159

A register file descriptor.

Definition MCSchedule.h:171

const char * Name

Definition MCSchedule.h:172

uint16_t NumRegisterCostEntries

Definition MCSchedule.h:174

bool AllowZeroMoveEliminationOnly

Definition MCSchedule.h:182

uint16_t RegisterCostEntryIdx

Definition MCSchedule.h:176

uint16_t MaxMovesEliminatedPerCycle

Definition MCSchedule.h:179

uint16_t NumPhysRegs

Definition MCSchedule.h:173

Summarize the scheduling resources required for an instruction of a particular scheduling class.

Definition MCSchedule.h:123

uint32_t NameOff

Definition MCSchedule.h:128

bool isValid() const

Definition MCSchedule.h:141

uint16_t ReadAdvanceIdx

Definition MCSchedule.h:138

bool isVariant() const

Definition MCSchedule.h:144

static const unsigned short InvalidNumMicroOps

Definition MCSchedule.h:124

uint16_t NumWriteLatencyEntries

Definition MCSchedule.h:137

uint16_t BeginGroup

Definition MCSchedule.h:131

uint16_t WriteProcResIdx

Definition MCSchedule.h:134

uint16_t WriteLatencyIdx

Definition MCSchedule.h:136

uint16_t EndGroup

Definition MCSchedule.h:132

uint16_t RetireOOO

Definition MCSchedule.h:133

uint16_t NumReadAdvanceEntries

Definition MCSchedule.h:139

uint16_t NumMicroOps

Definition MCSchedule.h:130

uint16_t NumWriteProcResEntries

Definition MCSchedule.h:135

static const unsigned short VariantNumMicroOps

Definition MCSchedule.h:125

Machine model for scheduling, bundling, and heuristics.

Definition MCSchedule.h:258

unsigned LoadLatency

Definition MCSchedule.h:299

static LLVM_ABI const MCSchedModel Default

Returns the default initialized model.

Definition MCSchedule.h:424

bool isOutOfOrder() const

Return true if machine supports out of order execution.

Definition MCSchedule.h:353

bool hasExtraProcessorInfo() const

Definition MCSchedule.h:335

bool PostRAScheduler

Definition MCSchedule.h:314

unsigned HighLatency

Definition MCSchedule.h:306

static LLVM_ABI unsigned getForwardingDelayCycles(ArrayRef< MCReadAdvanceEntry > Entries, unsigned WriteResourceIdx=0)

Returns the maximum forwarding delay for register reads dependent on writes of scheduling class Write...

static const unsigned DefaultLoopMicroOpBufferSize

Definition MCSchedule.h:296

const InstrItinerary * InstrItineraries

Definition MCSchedule.h:331

static const unsigned DefaultHighLatency

Definition MCSchedule.h:307

const MCSchedClassDesc * getSchedClassDesc(unsigned SchedClassIdx) const

Definition MCSchedule.h:366

unsigned getProcessorID() const

Definition MCSchedule.h:337

const MCExtraProcessorInfo & getExtraProcessorInfo() const

Definition MCSchedule.h:342

unsigned getNumProcResourceKinds() const

Definition MCSchedule.h:355

bool hasInstrSchedModel() const

Does this machine model include instruction-level scheduling.

Definition MCSchedule.h:340

unsigned ProcID

Definition MCSchedule.h:323

static const unsigned DefaultLoadLatency

Definition MCSchedule.h:300

unsigned LoopMicroOpBufferSize

Definition MCSchedule.h:295

static LLVM_ABI int computeInstrLatency(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)

Returns the latency value for the scheduling class.

static const unsigned DefaultMicroOpBufferSize

Definition MCSchedule.h:288

friend class InstrItineraryData

Definition MCSchedule.h:330

const StringTable * SchedClassNames

Definition MCSchedule.h:328

const MCSchedClassDesc * SchedClassTable

Definition MCSchedule.h:325

const MCProcResourceDesc * ProcResourceTable

Definition MCSchedule.h:324

static const unsigned DefaultMispredictPenalty

Definition MCSchedule.h:312

unsigned MicroOpBufferSize

Definition MCSchedule.h:287

unsigned NumSchedClasses

Definition MCSchedule.h:327

bool CompleteModel

Definition MCSchedule.h:316

unsigned IssueWidth

Definition MCSchedule.h:270

const MCExtraProcessorInfo * ExtraProcessorInfo

Definition MCSchedule.h:333

const MCProcResourceDesc * getProcResource(unsigned ProcResourceIdx) const

Definition MCSchedule.h:359

static LLVM_ABI unsigned getBypassDelayCycles(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)

Returns the bypass delay cycle for the maximum latency write cycle.

static LLVM_ABI double getReciprocalThroughput(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)

StringRef getSchedClassName(unsigned SchedClassIdx) const

Definition MCSchedule.h:373

bool EnableIntervals

Definition MCSchedule.h:321

static const unsigned DefaultIssueWidth

Definition MCSchedule.h:271

unsigned NumProcResourceKinds

Definition MCSchedule.h:326

bool isComplete() const

Return true if this machine model data for all instructions with a scheduling class (itinerary class ...

Definition MCSchedule.h:350

unsigned MispredictPenalty

Definition MCSchedule.h:311

Specify the latency in cpu cycles for a particular scheduling class and def index.

Definition MCSchedule.h:91

uint16_t WriteResourceID

Definition MCSchedule.h:93

bool operator==(const MCWriteLatencyEntry &Other) const

Definition MCSchedule.h:95

int16_t Cycles

Definition MCSchedule.h:92

Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...

Definition MCSchedule.h:68

bool operator==(const MCWriteProcResEntry &Other) const

Definition MCSchedule.h:79

uint16_t ProcResourceIdx

Definition MCSchedule.h:69

uint16_t AcquireAtCycle

Cycle at which the resource will be aquired by an instruction, relatively to the cycle in which the i...

Definition MCSchedule.h:77

uint16_t ReleaseAtCycle

Cycle at which the resource will be released by an instruction, relatively to the cycle in which the ...

Definition MCSchedule.h:73