MCSubtargetInfo.h Source File (original) (raw)

13#ifndef LLVM_MC_MCSUBTARGETINFO_H

14#define LLVM_MC_MCSUBTARGETINFO_H

24#include

25#include

26#include

27#include

29namespace llvm {

57 const char *Key;

71};

79 std::string CPU;

80 std::string TuneCPU;

91 const InstrStage *Stages;

92 const unsigned *OperandCycles;

93 const unsigned *ForwardingPaths;

94 FeatureBitset FeatureBits;

95 std::string FeatureString;

97public:

105 const unsigned *OC, const unsigned *FP);

110

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117 FeatureBits = FeatureBits_;

118 }

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123 return FeatureBits[Feature];

124 }

125

126protected:

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160 bool checkFeatures(StringRef FS) const;

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180 unsigned DefIdx) const {

181 assert(DefIdx < SC->NumWriteLatencyEntries &&

182 "MachineModel does not specify a WriteResource for DefIdx");

183

185 }

186

188 unsigned WriteResID) const {

189

190

191

194 if (I->UseIdx < UseIdx)

195 continue;

196 if (I->UseIdx > UseIdx)

197 break;

198

199 if (->WriteResourceID || I->WriteResourceID == WriteResID) {

200 return I->Cycles;

201 }

202 }

203 return 0;

204 }

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226 unsigned CPUID) const {

227 return 0;

228 }

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233 return Found != ProcDesc.end() && StringRef(Found->Key) == CPU;

234 }

235

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238 return ProcDesc;

239 }

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243 return ProcFeatures;

244 }

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247 std::vector getEnabledProcessorFeatures() const;

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280 virtual std::optional getCacheSize(unsigned Level) const;

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286 virtual std::optional getCacheAssociativity(unsigned Level) const;

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290 virtual std::optional getCacheLineSize(unsigned Level) const;

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301 return *Size;

302

303 return 0;

304 }

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308 virtual unsigned getPrefetchDistance() const;

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313 virtual unsigned getMaxPrefetchIterationsAhead() const;

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317 virtual bool enableWritePrefetching() const;

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322 virtual unsigned getMinPrefetchStride(unsigned NumMemAccesses,

323 unsigned NumStridedMemAccesses,

324 unsigned NumPrefetches,

325 bool HasCall) const;

326

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328 virtual bool shouldPrefetchAddressSpace(unsigned AS) const;

329};

330

331}

332

333#endif

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")

static void ApplyFeatureFlag(FeatureBitset &Bits, StringRef Feature, ArrayRef< SubtargetFeatureKV > FeatureTable)

SI optimize exec mask operations pre RA

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Class used to store the subtarget bits in the tables created by tablegen.

Container class for subtarget features.

Itinerary data supplied by a subtarget to be used by a target.

Instances of this class represent a single low-level machine instruction.

Interface to description of machine instruction set.

virtual unsigned getCacheLineSize() const

Return the target cache line size in bytes.

Definition MCSubtargetInfo.h:298

const MCWriteProcResEntry * getWriteProcResEnd(const MCSchedClassDesc *SC) const

Definition MCSubtargetInfo.h:174

bool hasFeature(unsigned Feature) const

Definition MCSubtargetInfo.h:122

int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const

Definition MCSubtargetInfo.h:187

StringRef getFeatureString() const

Definition MCSubtargetInfo.h:120

void setFeatureBits(const FeatureBitset &FeatureBits_)

Definition MCSubtargetInfo.h:116

virtual unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const

Resolve a variant scheduling class for the given MCInst and CPU.

Definition MCSubtargetInfo.h:223

const Triple & getTargetTriple() const

Definition MCSubtargetInfo.h:111

ArrayRef< SubtargetSubTypeKV > getAllProcessorDescriptions() const

Return processor descriptions.

Definition MCSubtargetInfo.h:237

ArrayRef< MCReadAdvanceEntry > getReadAdvanceEntries(const MCSchedClassDesc &SC) const

Return the set of ReadAdvance entries declared by the scheduling class descriptor in input.

Definition MCSubtargetInfo.h:209

const MCWriteLatencyEntry * getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const

Definition MCSubtargetInfo.h:179

MCSubtargetInfo & operator=(const MCSubtargetInfo &)=delete

MCSubtargetInfo & operator=(MCSubtargetInfo &&)=delete

const FeatureBitset & getFeatureBits() const

Definition MCSubtargetInfo.h:115

HwModeType

HwMode IDs are stored and accessed in a bit set format, enabling users to efficiently retrieve specif...

Definition MCSubtargetInfo.h:257

@ HwMode_Default

Definition MCSubtargetInfo.h:258

@ HwMode_ValueType

Definition MCSubtargetInfo.h:259

@ HwMode_RegInfo

Definition MCSubtargetInfo.h:260

@ HwMode_EncodingInfo

Definition MCSubtargetInfo.h:262

StringRef getCPU() const

Definition MCSubtargetInfo.h:112

ArrayRef< SubtargetFeatureKV > getAllProcessorFeatures() const

Return processor features.

Definition MCSubtargetInfo.h:242

virtual ~MCSubtargetInfo()=default

StringRef getTuneCPU() const

Definition MCSubtargetInfo.h:113

virtual std::optional< unsigned > getCacheLineSize(unsigned Level) const

Return the target cache line size in bytes at a given level.

MCSubtargetInfo(const MCSubtargetInfo &)=default

virtual bool isCPUStringValid(StringRef CPU) const

Check whether the CPU string is valid.

Definition MCSubtargetInfo.h:231

virtual unsigned getHwModeSet() const

Return a bit set containing all HwMode IDs of the current subtarget.

Definition MCSubtargetInfo.h:266

const MCWriteProcResEntry * getWriteProcResBegin(const MCSchedClassDesc *SC) const

Return an iterator at the first process resource consumed by the given scheduling class.

Definition MCSubtargetInfo.h:170

virtual unsigned getHwMode(enum HwModeType type=HwMode_Default) const

HwMode ID corresponding to the 'type' parameter is retrieved from the HwMode bit set of the current s...

Definition MCSubtargetInfo.h:272

const MCSchedModel & getSchedModel() const

Get the machine model for this subtarget's CPU.

Definition MCSubtargetInfo.h:166

StringRef - Represent a constant reference to a string, i.e.

Triple - Helper class for working with autoconf configuration names.

This is an optimization pass for GlobalISel generic memory operations.

auto lower_bound(R &&Range, T &&Value)

Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...

These values represent a non-pipelined step in the execution of an instruction.

Specify the number of cycles allowed after instruction issue before a particular use operand reads it...

Summarize the scheduling resources required for an instruction of a particular scheduling class.

uint16_t NumReadAdvanceEntries

uint16_t NumWriteProcResEntries

Machine model for scheduling, bundling, and heuristics.

Specify the latency in cpu cycles for a particular scheduling class and def index.

Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...

Used to provide key value pairs for feature and CPU bit flags.

Definition MCSubtargetInfo.h:36

bool operator<(StringRef S) const

Compare routine for std::lower_bound.

Definition MCSubtargetInfo.h:43

bool operator<(const SubtargetFeatureKV &Other) const

Compare routine for std::is_sorted.

Definition MCSubtargetInfo.h:48

unsigned Value

K-V integer value.

Definition MCSubtargetInfo.h:39

const char * Key

K-V key string.

Definition MCSubtargetInfo.h:37

const char * Desc

Help descriptor.

Definition MCSubtargetInfo.h:38

FeatureBitArray Implies

K-V bit mask.

Definition MCSubtargetInfo.h:40

Used to provide key value pairs for feature and CPU bit flags.

Definition MCSubtargetInfo.h:56

const MCSchedModel * SchedModel

Definition MCSubtargetInfo.h:60

FeatureBitArray Implies

K-V bit mask.

Definition MCSubtargetInfo.h:58

const char * Key

K-V key string.

Definition MCSubtargetInfo.h:57

FeatureBitArray TuneImplies

K-V bit mask.

Definition MCSubtargetInfo.h:59

bool operator<(const SubtargetSubTypeKV &Other) const

Compare routine for std::is_sorted.

Definition MCSubtargetInfo.h:68

bool operator<(StringRef S) const

Compare routine for std::lower_bound.

Definition MCSubtargetInfo.h:63