LLVM: lib/Target/AArch64/AArch64ISelDAGToDAG.cpp File Reference (original) (raw)

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Macros
#define DEBUG_TYPE "aarch64-isel"
#define PASS_NAME "AArch64 Instruction Selection"
Enumerations
enum class SelectTypeKind { Int1 = 0 , Int = 1 , FP = 2 , AnyType = 3 }
Functions
static bool isIntImmediate (const SDNode *N, uint64_t &Imm)
isIntImmediate - This method tests to see if the node is a constant operand.
static bool isIntImmediate (SDValue N, uint64_t &Imm)
static bool isOpcWithIntImmediate (const SDNode *N, unsigned Opc, uint64_t &Imm)
static bool isIntImmediateEq (SDValue N, const uint64_t ImmExpected)
static AArch64_AM::ShiftExtendType getShiftTypeForNode (SDValue N)
getShiftTypeForNode - Translate a shift node to the corresponding ShiftType value.
static bool isMemOpOrPrefetch (SDNode *N)
static bool isWorthFoldingSHL (SDValue V)
Determine whether it is worth it to fold SHL into the addressing mode.
static AArch64_AM::ShiftExtendType getExtendTypeForNode (SDValue N, bool IsLoadStore=false)
getExtendTypeForNode - Translate an extend node to the corresponding ExtendType value.
static SDValue narrowIfNeeded (SelectionDAG *CurDAG, SDValue N)
Instructions that accept extend modifiers like UXTW expect the register being extended to be a GPR32, but the incoming DAG might be acting on a GPR64 (either via SEXT_INREG or AND).
static bool isWorthFoldingADDlow (SDValue N)
If there's a use of this ADDlow that's not itself a load/store then we'll need to create a real ADD instruction from it anyway and there's no point in folding it into the mem op.
static bool isValidAsScaledImmediate (int64_t Offset, unsigned Range, unsigned Size)
Check if the immediate offset is valid as a scaled immediate.
static SDValue Widen (SelectionDAG *CurDAG, SDValue N)
static bool isPreferredADD (int64_t ImmOff)
static std::tuple< SDValue, SDValue > extractPtrauthBlendDiscriminators (SDValue Disc, SelectionDAG *DAG)
template<SelectTypeKind Kind>
static unsigned SelectOpcodeFromVT (EVT VT, ArrayRef< unsigned > Opcodes)
This function selects an opcode from a list of opcodes, which is expected to be the opcode for { 8-bit, 16-bit, 32-bit, 64-bit } element types, in this order.
bool SelectSMETile (unsigned &BaseReg, unsigned TileNum)
static SDValue NarrowVector (SDValue V128Reg, SelectionDAG &DAG)
NarrowVector - Given a value in the V128 register class, produce the equivalent value in the V64 register class.
static bool isBitfieldExtractOpFromAnd (SelectionDAG *CurDAG, SDNode *N, unsigned &Opc, SDValue &Opd0, unsigned &LSB, unsigned &MSB, unsigned NumberOfIgnoredLowBits, bool BiggerPattern)
static bool isBitfieldExtractOpFromSExtInReg (SDNode *N, unsigned &Opc, SDValue &Opd0, unsigned &Immr, unsigned &Imms)
static bool isSeveralBitsExtractOpFromShr (SDNode *N, unsigned &Opc, SDValue &Opd0, unsigned &LSB, unsigned &MSB)
static bool isBitfieldExtractOpFromShr (SDNode *N, unsigned &Opc, SDValue &Opd0, unsigned &Immr, unsigned &Imms, bool BiggerPattern)
static bool isBitfieldExtractOp (SelectionDAG *CurDAG, SDNode *N, unsigned &Opc, SDValue &Opd0, unsigned &Immr, unsigned &Imms, unsigned NumberOfIgnoredLowBits=0, bool BiggerPattern=false)
static bool isBitfieldDstMask (uint64_t DstMask, const APInt &BitsToBeInserted, unsigned NumberOfIgnoredHighBits, EVT VT)
Does DstMask form a complementary pair with the mask provided by BitsToBeInserted, suitable for use in a BFI instruction.
static void getUsefulBits (SDValue Op, APInt &UsefulBits, unsigned Depth=0)
static void getUsefulBitsFromAndWithImmediate (SDValue Op, APInt &UsefulBits, unsigned Depth)
static void getUsefulBitsFromBitfieldMoveOpd (SDValue Op, APInt &UsefulBits, uint64_t Imm, uint64_t MSB, unsigned Depth)
static void getUsefulBitsFromUBFM (SDValue Op, APInt &UsefulBits, unsigned Depth)
static void getUsefulBitsFromOrWithShiftedReg (SDValue Op, APInt &UsefulBits, unsigned Depth)
static void getUsefulBitsFromBFM (SDValue Op, SDValue Orig, APInt &UsefulBits, unsigned Depth)
static void getUsefulBitsForUse (SDNode *UserNode, APInt &UsefulBits, SDValue Orig, unsigned Depth)
static SDValue getLeftShift (SelectionDAG *CurDAG, SDValue Op, int ShlAmount)
Create a machine node performing a notional SHL of Op by ShlAmount.
static bool isBitfieldPositioningOpFromAnd (SelectionDAG *CurDAG, SDValue Op, bool BiggerPattern, const uint64_t NonZeroBits, SDValue &Src, int &DstLSB, int &Width)
static bool isBitfieldPositioningOpFromShl (SelectionDAG *CurDAG, SDValue Op, bool BiggerPattern, const uint64_t NonZeroBits, SDValue &Src, int &DstLSB, int &Width)
static bool isBitfieldPositioningOp (SelectionDAG *CurDAG, SDValue Op, bool BiggerPattern, SDValue &Src, int &DstLSB, int &Width)
Does this tree qualify as an attempt to move a bitfield into position, essentially "(and (shl VAL, N), Mask)" or (shl VAL, N).
static bool isSeveralBitsPositioningOpFromShl (const uint64_t ShlImm, SDValue Op, SDValue &Src, int &DstLSB, int &Width)
static bool isShiftedMask (uint64_t Mask, EVT VT)
static bool tryBitfieldInsertOpFromOrAndImm (SDNode *N, SelectionDAG *CurDAG)
static bool isWorthFoldingIntoOrrWithShift (SDValue Dst, SelectionDAG *CurDAG, SDValue &ShiftedOperand, uint64_t &EncodedShiftImm)
static bool tryOrrWithShift (SDNode *N, SDValue OrOpd0, SDValue OrOpd1, SDValue Src, SDValue Dst, SelectionDAG *CurDAG, const bool BiggerPattern)
static bool tryBitfieldInsertOpFromOr (SDNode *N, const APInt &UsefulBits, SelectionDAG *CurDAG)
static bool checkCVTFixedPointOperandWithFBits (SelectionDAG *CurDAG, SDValue N, SDValue &FixedPos, unsigned RegWidth, bool isReciprocal)
static int getIntOperandFromRegisterString (StringRef RegString)
static EVT getPackedVectorTypeFromPredicateType (LLVMContext &Ctx, EVT PredVT, unsigned NumVec)
When PredVT is a scalable vector predicate in the form MVT::nxxi1, it builds the correspondent scalable vector of integers MVT::nxxi s.t.
static EVT getMemVTFromNode (LLVMContext &Ctx, SDNode *Root)
Return the EVT of the data associated to a memory operation in Root.

◆ DEBUG_TYPE

#define DEBUG_TYPE "aarch64-isel"

◆ PASS_NAME

◆ SelectTypeKind

enum class SelectTypeKind strong

◆ checkCVTFixedPointOperandWithFBits()

◆ extractPtrauthBlendDiscriminators()

◆ getExtendTypeForNode()

getExtendTypeForNode - Translate an extend node to the corresponding ExtendType value.

Definition at line 816 of file AArch64ISelDAGToDAG.cpp.

References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::cast(), llvm::dyn_cast(), llvm::ConstantSDNode::getZExtValue(), llvm::AArch64_AM::InvalidShiftExtend, N, llvm::ISD::SIGN_EXTEND, llvm::ISD::SIGN_EXTEND_INREG, llvm::AArch64_AM::SXTB, llvm::AArch64_AM::SXTH, llvm::AArch64_AM::SXTW, llvm::AArch64_AM::UXTB, llvm::AArch64_AM::UXTH, llvm::AArch64_AM::UXTW, and llvm::ISD::ZERO_EXTEND.

◆ getIntOperandFromRegisterString()

int getIntOperandFromRegisterString ( StringRef RegString) static

◆ getLeftShift()

◆ getMemVTFromNode()

Return the EVT of the data associated to a memory operation in Root.

If such EVT cannot be retrieved, it returns an invalid EVT.

Definition at line 7437 of file AArch64ISelDAGToDAG.cpp.

References llvm::cast(), llvm::EVT::changeVectorElementType(), llvm::dyn_cast(), llvm::SDNode::getConstantOperandVal(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), getPackedVectorTypeFromPredicateType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorElementType(), llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::isa(), and llvm_unreachable.

◆ getPackedVectorTypeFromPredicateType()

◆ getShiftTypeForNode()

◆ getUsefulBits()

◆ getUsefulBitsForUse()

◆ getUsefulBitsFromAndWithImmediate()

◆ getUsefulBitsFromBFM()

◆ getUsefulBitsFromBitfieldMoveOpd()

◆ getUsefulBitsFromOrWithShiftedReg()

◆ getUsefulBitsFromUBFM()

◆ isBitfieldDstMask()

◆ isBitfieldExtractOp()

◆ isBitfieldExtractOpFromAnd()

Definition at line 2566 of file AArch64ISelDAGToDAG.cpp.

References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::countr_one(), llvm::dbgs(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), isOpcWithIntImmediate(), LLVM_DEBUG, llvm::maskTrailingOnes(), N, Opc, llvm::ISD::SRL, llvm::ISD::TRUNCATE, and Widen().

Referenced by isBitfieldExtractOp().

◆ isBitfieldExtractOpFromSExtInReg()

Definition at line 2660 of file AArch64ISelDAGToDAG.cpp.

References assert(), llvm::BitWidth, llvm::cast(), llvm::EVT::getSizeInBits(), isOpcWithIntImmediate(), N, Opc, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRA, llvm::ISD::SRL, and llvm::ISD::TRUNCATE.

Referenced by isBitfieldExtractOp().

◆ isBitfieldExtractOpFromShr()

Definition at line 2733 of file AArch64ISelDAGToDAG.cpp.

References assert(), llvm::dbgs(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::SDValue::getValueType(), isIntImmediate(), isOpcWithIntImmediate(), isSeveralBitsExtractOpFromShr(), LLVM_DEBUG, N, Opc, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, and llvm::ISD::TRUNCATE.

Referenced by isBitfieldExtractOp().

◆ isBitfieldPositioningOp()

Does this tree qualify as an attempt to move a bitfield into position, essentially "(and (shl VAL, N), Mask)" or (shl VAL, N).

Definition at line 3177 of file AArch64ISelDAGToDAG.cpp.

References llvm::ISD::AND, assert(), llvm::BitWidth, llvm::SelectionDAG::computeKnownBits(), llvm::EVT::getSizeInBits(), isBitfieldPositioningOpFromAnd(), isBitfieldPositioningOpFromShl(), llvm::isShiftedMask_64(), and llvm::ISD::SHL.

Referenced by tryBitfieldInsertOpFromOr().

◆ isBitfieldPositioningOpFromAnd()

Definition at line 3207 of file AArch64ISelDAGToDAG.cpp.

References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::countr_one(), llvm::countr_zero(), llvm::dbgs(), getLeftShift(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), isOpcWithIntImmediate(), llvm::isShiftedMask_64(), LLVM_DEBUG, llvm::ISD::SHL, and Widen().

Referenced by isBitfieldPositioningOp().

◆ isBitfieldPositioningOpFromShl()

◆ isIntImmediate() [1/2]

isIntImmediate - This method tests to see if the node is a constant operand.

If so Imm will receive the 32-bit value.

Definition at line 537 of file AArch64ISelDAGToDAG.cpp.

References llvm::CallingConv::C, const, llvm::dyn_cast(), isIntImmediate(), and N.

Referenced by isBitfieldExtractOpFromShr(), isIntImmediate(), isIntImmediate(), isIntImmediateEq(), isOpcWithIntImmediate(), isOpcWithIntImmediate(), and isSeveralBitsExtractOpFromShr().

◆ isIntImmediate() [2/2]

◆ isIntImmediateEq()

◆ isMemOpOrPrefetch()

◆ isOpcWithIntImmediate()

Definition at line 554 of file AArch64ISelDAGToDAG.cpp.

References isIntImmediate(), N, and Opc.

Referenced by isBitfieldExtractOpFromAnd(), isBitfieldExtractOpFromSExtInReg(), isBitfieldExtractOpFromShr(), isBitfieldPositioningOpFromAnd(), isBitfieldPositioningOpFromShl(), isSeveralBitsExtractOpFromShr(), isSeveralBitsPositioningOpFromShl(), isWorthFoldingIntoOrrWithShift(), performAddCombineForShiftedOperands(), tryBitfieldInsertOpFromOr(), tryBitfieldInsertOpFromOrAndImm(), and tryOrrWithShift().

◆ isPreferredADD()

bool isPreferredADD ( int64_t ImmOff) static

◆ isSeveralBitsExtractOpFromShr()

◆ isSeveralBitsPositioningOpFromShl()

◆ isShiftedMask()

◆ isValidAsScaledImmediate()

◆ isWorthFoldingADDlow()

If there's a use of this ADDlow that's not itself a load/store then we'll need to create a real ADD instruction from it anyway and there's no point in folding it into the mem op.

Theoretically, it shouldn't matter, but there's a single pseudo-instruction for an ADRP/ADD pair so over-aggressive folding leads to duplicated ADRP instructions.

Definition at line 1044 of file AArch64ISelDAGToDAG.cpp.

References llvm::cast(), llvm::isStrongerThanMonotonic(), and N.

◆ isWorthFoldingIntoOrrWithShift()

Definition at line 3458 of file AArch64ISelDAGToDAG.cpp.

References llvm::ISD::AND, assert(), llvm::countr_one(), llvm::countr_zero(), DL, llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getNode(), llvm::SDValue::getOperand(), llvm::AArch64_AM::getShifterImm(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::hasOneUse(), isOpcWithIntImmediate(), llvm::isShiftedMask_64(), llvm::AArch64_AM::LSL, llvm::AArch64_AM::LSR, SDValue(), llvm::ISD::SHL, and llvm::ISD::SRL.

Referenced by tryOrrWithShift().

◆ isWorthFoldingSHL()

◆ narrowIfNeeded()

Instructions that accept extend modifiers like UXTW expect the register being extended to be a GPR32, but the incoming DAG might be acting on a GPR64 (either via SEXT_INREG or AND).

Extract the appropriate low bits if this is the case.

Definition at line 921 of file AArch64ISelDAGToDAG.cpp.

References llvm::SelectionDAG::getTargetExtractSubreg(), and N.

◆ NarrowVector()

◆ SelectOpcodeFromVT()

template<SelectTypeKind Kind>

This function selects an opcode from a list of opcodes, which is expected to be the opcode for { 8-bit, 16-bit, 32-bit, 64-bit } element types, in this order.

Definition at line 1850 of file AArch64ISelDAGToDAG.cpp.

References AnyType, FP, llvm::EVT::getVectorElementType(), llvm::EVT::getVectorMinNumElements(), llvm::InnerAnalysisManagerProxy< AnalysisManagerT, IRUnitT, ExtraArgTs... >::Key, Int, Int1, llvm::EVT::isScalableVector(), llvm::Offset, and llvm::ArrayRef< T >::size().

◆ SelectSMETile()

◆ tryBitfieldInsertOpFromOr()

Definition at line 3633 of file AArch64ISelDAGToDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::AND, assert(), llvm::BitWidth, llvm::SelectionDAG::computeKnownBits(), llvm::APInt::countl_zero(), llvm::APInt::countr_zero(), llvm::countr_zero(), DL, llvm::APInt::getBitsSet(), llvm::KnownBits::getBitWidth(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getNode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::SDValue::hasOneUse(), I, isBitfieldDstMask(), isBitfieldExtractOp(), isBitfieldPositioningOp(), isOpcWithIntImmediate(), isShiftedMask(), N, Opc, llvm::ISD::OR, llvm::APInt::popcount(), SDValue(), llvm::SelectionDAG::SelectNodeTo(), llvm::ISD::SRL, std::swap(), tryOrrWithShift(), and llvm::KnownBits::Zero.

◆ tryBitfieldInsertOpFromOrAndImm()

Definition at line 3370 of file AArch64ISelDAGToDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::AND, assert(), llvm::BitWidth, llvm::SelectionDAG::computeKnownBits(), llvm::countr_one(), DL, llvm::SelectionDAG::getMachineNode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::APInt::getZExtValue(), llvm::AArch64_AM::isLogicalImmediate(), isOpcWithIntImmediate(), isShiftedMask(), N, Opc, llvm::ISD::OR, llvm::APInt::popcount(), SDValue(), llvm::SelectionDAG::SelectNodeTo(), and llvm::KnownBits::Zero.

◆ tryOrrWithShift()

Definition at line 3533 of file AArch64ISelDAGToDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::AND, assert(), DL, llvm::SDValue::getNode(), llvm::SDValue::getOperand(), llvm::AArch64_AM::getShifterImm(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::hasOneUse(), llvm::isMask_64(), isOpcWithIntImmediate(), isWorthFoldingIntoOrrWithShift(), llvm::AArch64_AM::LSL, llvm::AArch64_AM::LSR, N, llvm::ISD::OR, llvm::SelectionDAG::SelectNodeTo(), llvm::ISD::SHL, and llvm::ISD::SRL.

Referenced by tryBitfieldInsertOpFromOr().

◆ Widen()