MSP430ISelLowering.cpp Source File (original) (raw)

34using namespace llvm;

36#define DEBUG_TYPE "msp430-lower"

39 "msp430-no-legal-immediate", cl::Hidden,

40 cl::desc("Enable non legal immediates (for testing purposes only)"),

69 }

102

109

116

118

119

130

143

144

150

154}

155

158 switch (Op.getOpcode()) {

159 case ISD::SHL:

173 default:

175 }

176}

177

178

180 unsigned Amount) const {

181 return !(Amount == 8 || Amount == 9 || Amount<=2);

182}

183

184

185

188 return Immed >= -32 && Immed < 32;

190}

191

192

193

194

195

196

197

200 if (Constraint.size() == 1) {

201 switch (Constraint[0]) {

202 case 'r':

204 default:

205 break;

206 }

207 }

209}

210

211std::pair<unsigned, const TargetRegisterClass *>

214 if (Constraint.size() == 1) {

215

216 switch (Constraint[0]) {

217 default: break;

218 case 'r':

219 if (VT == MVT::i8)

220 return std::make_pair(0U, &MSP430::GR8RegClass);

221

222 return std::make_pair(0U, &MSP430::GR16RegClass);

223 }

224 }

225

227}

228

229

230

231

232

233#include "MSP430GenCallingConv.inc"

234

235

236

237template

240 unsigned CurrentArgIndex;

241

242 if (Args.empty())

243 return;

244

245 CurrentArgIndex = Args[0].OrigArgIndex;

247

248 for (auto &Arg : Args) {

249 if (CurrentArgIndex == Arg.OrigArgIndex) {

250 Out.back() += 1;

251 } else {

253 CurrentArgIndex = Arg.OrigArgIndex;

254 }

255 }

256}

257

260 State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack);

261}

262

265 State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack);

266}

267

268

269

270

271

272template

276 static const MCPhysReg CRegList[] = {

277 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15

278 };

279 static const unsigned CNbRegs = std::size(CRegList);

280 static const MCPhysReg BuiltinRegList[] = {

281 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,

282 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15

283 };

284 static const unsigned BuiltinNbRegs = std::size(BuiltinRegList);

285

287 unsigned NbRegs;

288

290 if (Builtin) {

291 RegList = BuiltinRegList;

292 NbRegs = BuiltinNbRegs;

293 } else {

294 RegList = CRegList;

295 NbRegs = CNbRegs;

296 }

297

298 if (State.isVarArg()) {

300 return;

301 }

302

305

306 if (Builtin) {

308 "Builtin calling convention requires two arguments");

309 }

310

311 unsigned RegsLeft = NbRegs;

312 bool UsedStack = false;

313 unsigned ValNo = 0;

314

315 for (unsigned i = 0, e = ArgsParts.size(); i != e; i++) {

316 MVT ArgVT = Args[ValNo].VT;

318 Type *OrigTy = Args[ValNo].OrigTy;

319 MVT LocVT = ArgVT;

321

322

323 if (LocVT == MVT::i8) {

324 LocVT = MVT::i16;

325 if (ArgFlags.isSExt())

327 else if (ArgFlags.isZExt())

329 else

331 }

332

333

334 if (ArgFlags.isByVal()) {

335 State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, Align(2), ArgFlags);

336 continue;

337 }

338

339 unsigned Parts = ArgsParts[i];

340

341 if (Builtin) {

343 "Builtin calling convention requires 64-bit arguments");

344 }

345

346 if (!UsedStack && Parts == 2 && RegsLeft == 1) {

347

350 RegsLeft -= 1;

351

352 UsedStack = true;

353 CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, OrigTy,

354 State);

355 } else if (Parts <= RegsLeft) {

356 for (unsigned j = 0; j < Parts; j++) {

359 RegsLeft--;

360 }

361 } else {

362 UsedStack = true;

363 for (unsigned j = 0; j < Parts; j++)

364 CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, OrigTy,

365 State);

366 }

367 }

368}

369

372 State.AnalyzeCallResult(Ins, RetCC_MSP430);

373}

374

377 State.AnalyzeReturn(Outs, RetCC_MSP430);

378}

379

380template

386

387SDValue MSP430TargetLowering::LowerFormalArguments(

391

392 switch (CallConv) {

393 default:

397 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);

400 return Chain;

402 }

403}

404

408 SelectionDAG &DAG = CLI.DAG;

409 SDLoc &dl = CLI.DL;

410 SmallVectorImplISD::OutputArg &Outs = CLI.Outs;

411 SmallVectorImpl &OutVals = CLI.OutVals;

412 SmallVectorImplISD::InputArg &Ins = CLI.Ins;

417 bool isVarArg = CLI.IsVarArg;

418

419

420 isTailCall = false;

421

422 switch (CallConv) {

423 default:

428 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,

429 Outs, OutVals, Ins, dl, DAG, InVals);

432 }

433}

434

435

436

437

438SDValue MSP430TargetLowering::LowerCCCArguments(

444 MachineRegisterInfo &RegInfo = MF.getRegInfo();

445 MSP430MachineFunctionInfo *FuncInfo = MF.getInfo();

446

447

449 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,

452

453

454 if (isVarArg) {

455 unsigned Offset = CCInfo.getStackSize();

457 }

458

459 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {

460 CCValAssign &VA = ArgLocs[i];

462

465 default:

466 {

467#ifndef NDEBUG

468 errs() << "LowerFormalArguments Unhandled argument type: "

469 << RegVT << "\n";

470#endif

472 }

473 case MVT::i16:

477

478

479

480

487

490

492 }

493 } else {

494

496

498 ISD::ArgFlagsTy Flags = Ins[i].Flags;

499

500 if (Flags.isByVal()) {

505 } else {

506

508 if (ObjSize > 2) {

509 errs() << "LowerFormalArguments Unhandled argument type: "

511 }

512

514

515

516

519 VA.getLocVT(), dl, Chain, FIN,

521 }

522

524 }

525 }

526

527 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {

528 if (Ins[i].Flags.isSRet()) {

530 if ( Reg ) {

534 }

537 }

538 }

539

540 return Chain;

541}

542

543bool

544MSP430TargetLowering::CanLowerReturn(CallingConv::ID CallConv,

546 bool IsVarArg,

549 const Type *RetTy) const {

551 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);

552 return CCInfo.CheckReturn(Outs, RetCC_MSP430);

553}

554

557 bool isVarArg,

561

563

564

566

567

570

571

574

575

577

580

581

582 for (unsigned i = 0; i != RVLocs.size(); ++i) {

583 CCValAssign &VA = RVLocs[i];

584 assert(VA.isRegLoc() && "Can only return in registers!");

585

587 OutVals[i], Glue);

588

589

590

593 }

594

596 MSP430MachineFunctionInfo *FuncInfo = MF.getInfo();

598

599 if ( Reg )

600 llvm_unreachable("sret virtual register not created in entry block");

601

605 unsigned R12 = MSP430::R12;

606

607 Chain = DAG.getCopyToReg(Chain, dl, R12, Val, Glue);

609 RetOps.push_back(DAG.getRegister(R12, PtrVT));

610 }

611

613 MSP430ISD::RETI_GLUE : MSP430ISD::RET_GLUE);

614

615 RetOps[0] = Chain;

616

617

619 RetOps.push_back(Glue);

620

621 return DAG.getNode(Opc, dl, MVT::Other, RetOps);

622}

623

624

625

626SDValue MSP430TargetLowering::LowerCCCCallTo(

632

634 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,

637

638

639 unsigned NumBytes = CCInfo.getStackSize();

641

643

647

648

649 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {

650 CCValAssign &VA = ArgLocs[i];

651

652 SDValue Arg = OutVals[i];

653

654

660 break;

663 break;

666 break;

667 }

668

669

670

673 } else {

675

678

682

684 ISD::ArgFlagsTy Flags = Outs[i].Flags;

685

686 if (Flags.isByVal()) {

688 MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode,

689 Flags.getNonZeroByValAlign(),

690 false,

691 true,

692 nullptr, std::nullopt,

693 MachinePointerInfo(), MachinePointerInfo());

694 } else {

695 MemOp = DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo());

696 }

697

699 }

700 }

701

702

703

704 if (!MemOpChains.empty())

706

707

708

709

711 for (const auto &[Reg, N] : RegsToPass) {

714 }

715

716

717

718

723

724

725 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);

727 Ops.push_back(Chain);

728 Ops.push_back(Callee);

729

730

731

732 for (const auto &[Reg, N] : RegsToPass)

734

736 Ops.push_back(InGlue);

737

738 Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, Ops);

740

741

742 Chain = DAG.getCALLSEQ_END(Chain, NumBytes, 0, InGlue, dl);

744

745

746

747 return LowerCallResult(Chain, InGlue, CallConv, isVarArg, Ins, dl,

748 DAG, InVals);

749}

750

751

752

753

754SDValue MSP430TargetLowering::LowerCallResult(

758

759

763

765

766

767 for (unsigned i = 0; i != RVLocs.size(); ++i) {

768 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),

769 RVLocs[i].getValVT(), InGlue).getValue(1);

772 }

773

774 return Chain;

775}

776

779 unsigned Opc = Op.getOpcode();

781 EVT VT = Op.getValueType();

783

784

786 return Op;

787

788 uint64_t ShiftAmount = N->getConstantOperandVal(1);

789

790

791 SDValue Victim = N->getOperand(0);

792

793 if (ShiftAmount >= 8) {

794 assert(VT == MVT::i16 && "Can not shift i8 by 8 and more");

795 switch(Opc) {

796 default:

799

802 break;

805

811 break;

812 }

813 ShiftAmount -= 8;

814 }

815

817

818

819 Victim = DAG.getNode(MSP430ISD::RRCL, dl, VT, Victim);

820 ShiftAmount -= 1;

821 }

822

823 while (ShiftAmount--)

824 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),

825 dl, VT, Victim);

826

827 return Victim;

828}

829

834 EVT PtrVT = Op.getValueType();

835

836

838 return DAG.getNode(MSP430ISD::Wrapper, SDLoc(Op), PtrVT, Result);

839}

840

845 EVT PtrVT = Op.getValueType();

847

848 return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result);

849}

850

855 EVT PtrVT = Op.getValueType();

857

858 return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result);

859}

860

863

864 assert( LHS .getValueType().isFloatingPoint() && "We don't handle FP yet");

865

866

868 switch (CC) {

872

873

876 break;

879

880

883 break;

886 [[fallthrough]];

888

889

892 RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));

894 break;

895 }

897 break;

900 [[fallthrough]];

902

903

906 RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));

908 break;

909 }

911 break;

914 [[fallthrough]];

916

917

920 RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));

922 break;

923 }

925 break;

928 [[fallthrough]];

930

931

934 RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));

936 break;

937 }

939 break;

940 }

941

942 TargetCC = DAG.getConstant(TCC, dl, MVT::i8);

943 return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS);

944}

945

946

948 SDValue Chain = Op.getOperand(0);

954

956 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);

957

958 return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),

959 Chain, Dest, TargetCC, Flag);

960}

961

966

967

968

969

970

971

972 bool andCC = isNullConstant(RHS) && LHS.hasOneUse() &&

973 (LHS.getOpcode() == ISD::AND ||

975 LHS.getOperand(0).getOpcode() == ISD::AND));

978 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);

979

980

981

982

983

984 bool Invert = false;

985 bool Shift = false;

986 bool Convert = true;

988 default:

989 Convert = false;

990 break;

992

993 break;

995

996 Invert = true;

997 break;

999 if (andCC) {

1000

1001 } else {

1002

1003 Shift = true;

1004 Invert = true;

1005 }

1006 break;

1008 Shift = true;

1009

1010

1011 break;

1012 }

1013 EVT VT = Op.getValueType();

1015 if (Convert) {

1017 MVT::i16, Flag);

1018 if (Shift)

1019

1022 if (Invert)

1024 return SR;

1025 } else {

1027 SDValue Ops[] = {One, Zero, TargetCC, Flag};

1028 return DAG.getNode(MSP430ISD::SELECT_CC, dl, Op.getValueType(), Ops);

1029 }

1030}

1031

1036 SDValue TrueV = Op.getOperand(2);

1037 SDValue FalseV = Op.getOperand(3);

1040

1042 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);

1043

1044 SDValue Ops[] = {TrueV, FalseV, TargetCC, Flag};

1045

1046 return DAG.getNode(MSP430ISD::SELECT_CC, dl, Op.getValueType(), Ops);

1047}

1048

1052 EVT VT = Op.getValueType();

1054

1055 assert(VT == MVT::i16 && "Only support i16 for now!");

1056

1060}

1061

1066 int ReturnAddrIndex = FuncInfo->getRAIndex();

1068

1069 if (ReturnAddrIndex == 0) {

1070

1073 true);

1074 FuncInfo->setRAIndex(ReturnAddrIndex);

1075 }

1076

1077 return DAG.getFrameIndex(ReturnAddrIndex, PtrVT);

1078}

1079

1084

1085 unsigned Depth = Op.getConstantOperandVal(0);

1087 EVT PtrVT = Op.getValueType();

1088

1089 if (Depth > 0) {

1096 }

1097

1098

1102}

1103

1108

1109 EVT VT = Op.getValueType();

1110 SDLoc dl(Op);

1111 unsigned Depth = Op.getConstantOperandVal(0);

1113 MSP430::R4, VT);

1117 return FrameAddr;

1118}

1119

1124

1126 EVT PtrVT = Ptr.getValueType();

1127

1128

1132

1133

1134 return DAG.getStore(Op.getOperand(0), SDLoc(Op), FrameIndex, Ptr,

1136}

1137

1141 EVT PtrVT = Op.getValueType();

1143 return DAG.getNode(MSP430ISD::Wrapper, SDLoc(JT), PtrVT, Result);

1144}

1145

1146

1147

1148

1149bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,

1154

1157 return false;

1158

1159 EVT VT = LD->getMemoryVT();

1160 if (VT != MVT::i8 && VT != MVT::i16)

1161 return false;

1162

1164 return false;

1165

1167 uint64_t RHSC = RHS->getZExtValue();

1168 if ((VT == MVT::i16 && RHSC != 2) ||

1169 (VT == MVT::i8 && RHSC != 1))

1170 return false;

1171

1172 Base = Op->getOperand(0);

1175 return true;

1176 }

1177

1178 return false;

1179}

1180

1182 Type *Ty2) const {

1184 return false;

1185

1188}

1189

1192 return false;

1193

1195}

1196

1201

1203

1204 return false && VT1 == MVT::i8 && VT2 == MVT::i16;

1205}

1206

1207

1208

1209

1210

1218

1219 unsigned Opc;

1220 bool ClearCarry = false;

1222 switch (MI.getOpcode()) {

1224 case MSP430::Shl8:

1225 Opc = MSP430::ADD8rr;

1226 RC = &MSP430::GR8RegClass;

1227 break;

1228 case MSP430::Shl16:

1229 Opc = MSP430::ADD16rr;

1230 RC = &MSP430::GR16RegClass;

1231 break;

1232 case MSP430::Sra8:

1233 Opc = MSP430::RRA8r;

1234 RC = &MSP430::GR8RegClass;

1235 break;

1236 case MSP430::Sra16:

1237 Opc = MSP430::RRA16r;

1238 RC = &MSP430::GR16RegClass;

1239 break;

1240 case MSP430::Srl8:

1241 ClearCarry = true;

1242 Opc = MSP430::RRC8r;

1243 RC = &MSP430::GR8RegClass;

1244 break;

1245 case MSP430::Srl16:

1246 ClearCarry = true;

1247 Opc = MSP430::RRC16r;

1248 RC = &MSP430::GR16RegClass;

1249 break;

1250 case MSP430::Rrcl8:

1251 case MSP430::Rrcl16: {

1252 BuildMI(*BB, MI, dl, TII.get(MSP430::BIC16rc), MSP430::SR)

1254 Register SrcReg = MI.getOperand(1).getReg();

1255 Register DstReg = MI.getOperand(0).getReg();

1256 unsigned RrcOpc = MI.getOpcode() == MSP430::Rrcl16

1257 ? MSP430::RRC16r : MSP430::RRC8r;

1258 BuildMI(*BB, MI, dl, TII.get(RrcOpc), DstReg)

1260 MI.eraseFromParent();

1261 return BB;

1262 }

1263 }

1264

1267

1268

1271

1272 F->insert(I, LoopBB);

1273 F->insert(I, RemBB);

1274

1275

1276

1278 BB->end());

1280

1281

1286

1291 Register ShiftAmtSrcReg = MI.getOperand(2).getReg();

1292 Register SrcReg = MI.getOperand(1).getReg();

1293 Register DstReg = MI.getOperand(0).getReg();

1294

1295

1296

1297

1298 BuildMI(BB, dl, TII.get(MSP430::CMP8ri))

1300 BuildMI(BB, dl, TII.get(MSP430::JCC))

1303

1304

1305

1306

1307

1308

1309 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)

1312 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)

1315 if (ClearCarry)

1316 BuildMI(LoopBB, dl, TII.get(MSP430::BIC16rc), MSP430::SR)

1318 if (Opc == MSP430::ADD8rr || Opc == MSP430::ADD16rr)

1322 else

1325 BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)

1327 BuildMI(LoopBB, dl, TII.get(MSP430::JCC))

1330

1331

1332

1333 BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)

1336

1337 MI.eraseFromParent();

1338 return RemBB;

1339}

1340

1344 unsigned Opc = MI.getOpcode();

1345

1346 if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||

1347 Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||

1348 Opc == MSP430::Srl8 || Opc == MSP430::Srl16 ||

1349 Opc == MSP430::Rrcl8 || Opc == MSP430::Rrcl16)

1351

1354

1355 assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&

1356 "Unexpected instr type to insert");

1357

1358

1359

1360

1361

1364

1365

1366

1367

1368

1369

1370

1375 F->insert(I, copy0MBB);

1376 F->insert(I, copy1MBB);

1377

1378

1382

1385

1386 BuildMI(BB, dl, TII.get(MSP430::JCC))

1388 .addImm(MI.getOperand(3).getImm());

1389

1390

1391

1392

1393 BB = copy0MBB;

1394

1395

1397

1398

1399

1400

1401 BB = copy1MBB;

1402 BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI), MI.getOperand(0).getReg())

1403 .addReg(MI.getOperand(2).getReg())

1405 .addReg(MI.getOperand(1).getReg())

1407

1408 MI.eraseFromParent();

1409 return BB;

1410}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

static void AnalyzeReturnValues(CCState &State, SmallVectorImpl< CCValAssign > &RVLocs, const SmallVectorImpl< ArgT > &Args)

Definition MSP430ISelLowering.cpp:381

static void AnalyzeVarArgs(CCState &State, const SmallVectorImpl< ISD::OutputArg > &Outs)

Definition MSP430ISelLowering.cpp:258

static void AnalyzeRetResult(CCState &State, const SmallVectorImpl< ISD::InputArg > &Ins)

Definition MSP430ISelLowering.cpp:370

static cl::opt< bool > MSP430NoLegalImmediate("msp430-no-legal-immediate", cl::Hidden, cl::desc("Enable non legal immediates (for testing purposes only)"), cl::init(false))

static void ParseFunctionArgs(const SmallVectorImpl< ArgT > &Args, SmallVectorImpl< unsigned > &Out)

For each argument in a function store the number of pieces it is composed of.

Definition MSP430ISelLowering.cpp:238

static void AnalyzeArguments(CCState &State, SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ArgT > &Args)

Analyze incoming and outgoing function arguments.

Definition MSP430ISelLowering.cpp:273

static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC, ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG)

Definition MSP430ISelLowering.cpp:861

Promote Memory to Register

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

LLVM Basic Block Representation.

The address of a basic block.

CCState - This class holds information needed while lowering arguments and return values.

LocInfo getLocInfo() const

static CCValAssign getReg(unsigned ValNo, MVT ValVT, MCRegister Reg, MVT LocVT, LocInfo HTP, bool IsCustom=false)

int64_t getLocMemOffset() const

bool hasStructRetAttr() const

Determine if the function returns a structure through first or second pointer argument.

This is an important class for using LLVM in a threaded context.

This class is used to represent ISD::LOAD nodes.

Wrapper class representing physical registers. Should be passed by value.

MSP430MachineFunctionInfo - This class is derived from MachineFunction and contains private MSP430 ta...

void setVarArgsFrameIndex(int Index)

void setRAIndex(int Index)

void setSRetReturnReg(Register Reg)

int getVarArgsFrameIndex() const

const MSP430RegisterInfo * getRegisterInfo() const override

SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const

Definition MSP430ISelLowering.cpp:1063

MSP430TargetLowering(const TargetMachine &TM, const MSP430Subtarget &STI)

Definition MSP430ISelLowering.cpp:43

std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override

Given a physical register constraint (e.g.

Definition MSP430ISelLowering.cpp:212

SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override

LowerOperation - Provide custom lowering hooks for some operations.

Definition MSP430ISelLowering.cpp:156

MachineBasicBlock * EmitShiftInstr(MachineInstr &MI, MachineBasicBlock *BB) const

Definition MSP430ISelLowering.cpp:1212

SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const

Definition MSP430ISelLowering.cpp:1138

SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const

Definition MSP430ISelLowering.cpp:1032

SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const

Definition MSP430ISelLowering.cpp:841

bool isTruncateFree(Type *Ty1, Type *Ty2) const override

isTruncateFree - Return true if it's free to truncate a value of type Ty1 to type Ty2.

Definition MSP430ISelLowering.cpp:1181

SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const

Definition MSP430ISelLowering.cpp:851

SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const

Definition MSP430ISelLowering.cpp:777

SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const

Definition MSP430ISelLowering.cpp:1104

SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const

Definition MSP430ISelLowering.cpp:830

SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const

Definition MSP430ISelLowering.cpp:1049

MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override

This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...

Definition MSP430ISelLowering.cpp:1342

SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const

Definition MSP430ISelLowering.cpp:1080

SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const

Definition MSP430ISelLowering.cpp:1120

SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const

Definition MSP430ISelLowering.cpp:962

SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const

Definition MSP430ISelLowering.cpp:947

bool shouldAvoidTransformToShift(EVT VT, unsigned Amount) const override

Return true if creating a shift of the type by the given amount is not profitable.

Definition MSP430ISelLowering.cpp:179

bool isZExtFree(Type *Ty1, Type *Ty2) const override

isZExtFree - Return true if any actual instruction that defines a value of type Ty1 implicit zero-ext...

Definition MSP430ISelLowering.cpp:1197

TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override

getConstraintType - Given a constraint letter, return the type of constraint it is for this target.

Definition MSP430ISelLowering.cpp:199

bool isLegalICmpImmediate(int64_t) const override

Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...

Definition MSP430ISelLowering.cpp:186

static auto integer_valuetypes()

TypeSize getSizeInBits() const

Returns the size of the specified MVT in bits.

TypeSize getStoreSize() const

Return the number of bytes overwritten by a store of the specified value type.

LLVM_ABI void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)

Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...

const BasicBlock * getBasicBlock() const

Return the LLVM basic block that this instance corresponded to originally.

LLVM_ABI void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())

Add Succ as a successor of this MachineBasicBlock.

const MachineFunction * getParent() const

Return the MachineFunction containing this basic block.

void splice(iterator Where, MachineBasicBlock *Other, iterator From)

Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...

MachineInstrBundleIterator< MachineInstr > iterator

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

LLVM_ABI int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)

Create a new object at a fixed location on the stack.

void setFrameAddressIsTaken(bool T)

void setReturnAddressIsTaken(bool s)

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

const DataLayout & getDataLayout() const

Return the DataLayout attached to the Module associated to this MF.

Function & getFunction()

Return the LLVM function that this machine code represents.

BasicBlockListType::iterator iterator

Ty * getInfo()

getInfo - Keep track of various per-function pieces of information for backends that would like to do...

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const

Representation of each machine instruction.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

LLVM_ABI Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")

createVirtualRegister - Create and return a new virtual register in the function with the specified r...

void addLiveIn(MCRegister Reg, Register vreg=Register())

addLiveIn - Add the specified register as a live-in.

Wrapper class representing virtual and physical registers.

Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...

Represents one node in the SelectionDAG.

uint64_t getAsZExtVal() const

Helper method returns the zero-extended integer value of a ConstantSDNode.

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.

SDNode * getNode() const

get the SDNode which holds the desired result

SDValue getValue(unsigned R) const

EVT getValueType() const

Return the ValueType of the referenced return value.

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...

SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)

SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, Register Reg, SDValue N)

LLVM_ABI SDVTList getVTList(EVT VT)

Return an SDVTList that represents the list of values specified.

LLVM_ABI SDValue getRegister(Register Reg, EVT VT)

LLVM_ABI SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)

Loads are not normal binary operators: their result type is not determined by their operands,...

LLVM_ABI SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, const CallInst *CI, std::optional< bool > OverrideTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), BatchAAResults *BatchAA=nullptr)

SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)

SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)

Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).

SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, Register Reg, EVT VT)

LLVM_ABI SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)

Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.

const DataLayout & getDataLayout() const

LLVM_ABI SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)

Create a ConstantSDNode wrapping a constant value.

LLVM_ABI SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())

Helper function to build ISD::STORE nodes.

SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)

Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...

LLVM_ABI SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)

LLVM_ABI SDValue getValueType(EVT)

LLVM_ABI SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)

Gets or creates the specified node.

SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)

MachineFunction & getMachineFunction() const

LLVM_ABI SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)

LLVMContext * getContext() const

LLVM_ABI SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)

SDValue getEntryNode() const

Return the token chain corresponding to the entry of the function.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StringRef - Represent a constant reference to a string, i.e.

constexpr size_t size() const

size - Get the string size.

TargetInstrInfo - Interface to description of machine instruction set.

void setBooleanVectorContents(BooleanContent Ty)

Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...

void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)

Indicate that the specified operation does not work with the specified type and indicate what to do a...

virtual bool isLegalICmpImmediate(int64_t) const

Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...

virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const

Return the register class that should be used for the specified value type.

void setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)

Indicate that the specified indexed load does or does not work with the specified type and indicate w...

void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)

Set the maximum atomic operation size supported by the backend.

void setMinFunctionAlignment(Align Alignment)

Set the target's minimum function alignment.

void setBooleanContents(BooleanContent Ty)

Specify how the target extends the result of integer and floating point boolean values from i1 to a w...

void computeRegisterProperties(const TargetRegisterInfo *TRI)

Once all of the register classes are added, this allows us to compute derived properties we expose.

void addRegisterClass(MVT VT, const TargetRegisterClass *RC)

Add the specified register class as an available regclass for the specified value type.

void setPrefFunctionAlignment(Align Alignment)

Set the target's preferred function alignment.

void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)

Indicate that the specified truncating store does not work with the specified type and indicate what ...

@ ZeroOrOneBooleanContent

void setStackPointerRegisterToSaveRestore(Register R)

If set to a physical register, this specifies the register that llvm.savestack/llvm....

void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)

Indicate that the specified load with extension does not work with the specified type and indicate wh...

MVT getFrameIndexTy(const DataLayout &DL) const

Return the type for frame index, which is determined by the alloca address space specified through th...

virtual ConstraintType getConstraintType(StringRef Constraint) const

Given a constraint, return the type of constraint it is for this target.

virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const

Given a physical register constraint (e.g.

TargetLowering(const TargetLowering &)=delete

Primary interface to the complete machine description for the target machine.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual const TargetInstrInfo * getInstrInfo() const

The instances of the Type class are immutable: once they are created, they are never changed.

LLVM_ABI TypeSize getPrimitiveSizeInBits() const LLVM_READONLY

Return the basic size of this type if it is a primitive type.

bool isIntegerTy() const

True if this is an instance of IntegerType.

LLVM Value Representation.

constexpr ScalarTy getFixedValue() const

self_iterator getIterator()

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ MSP430_BUILTIN

Used for special MSP430 rtlib functions which have an "optimized" convention using additional registe...

@ Fast

Attempts to make calls as fast as possible (e.g.

@ MSP430_INTR

Used for MSP430 interrupt routines.

@ C

The default llvm calling convention, compatible with C.

@ SETCC

SetCC operator - This evaluates to a true value iff the condition is true.

@ SMUL_LOHI

SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...

@ BSWAP

Byte Swap and Counting operators.

@ ADD

Simple integer binary arithmetic operators.

@ ANY_EXTEND

ANY_EXTEND - Used for integer types. The high bits are undefined.

@ SDIVREM

SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.

@ SIGN_EXTEND

Conversion operators.

@ SELECT

Select(COND, TRUEVAL, FALSEVAL).

@ MULHU

MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...

@ SHL

Shift and rotation operations.

@ ZERO_EXTEND

ZERO_EXTEND - Used for integer types, zeroing the new bits.

@ SELECT_CC

Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...

@ SIGN_EXTEND_INREG

SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...

@ FRAMEADDR

FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.

@ AND

Bitwise operators - logical and, logical or, logical xor.

@ TokenFactor

TokenFactor - This node takes multiple tokens as input and produces a single token result.

@ TRUNCATE

TRUNCATE - Completely drop the high bits.

@ SHL_PARTS

SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.

@ AssertSext

AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...

MemIndexedMode

MemIndexedMode enum - This enum defines the load / store indexed addressing modes.

CondCode

ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

LLVM_ABI bool isNullConstant(SDValue V)

Returns true if V is a constant integer zero.

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)

class LLVM_GSL_OWNER SmallVector

Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...

bool isa(const From &Val)

isa - Return true if the parameter to the template is an instance of one of the template type argu...

LLVM_ABI raw_fd_ostream & errs()

This returns a reference to a raw_ostream for standard error.

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

DWARFExpression::Operation Op

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)

Implement std::swap in terms of BitVector swap.

This struct is a compact representation of a valid (non-zero power of two) alignment.

TypeSize getStoreSize() const

Return the number of bytes overwritten by a store of the specified value type.

MVT getSimpleVT() const

Return the SimpleValueType held in the specified simple EVT.

uint64_t getFixedSizeInBits() const

Return the size of the specified fixed width value type in bits.

bool isInteger() const

Return true if this is an integer or a vector integer type.

This class contains a discriminated union of information about pointers in memory operands,...

static LLVM_ABI MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)

Return a MachinePointerInfo record that refers to the specified FrameIndex.

This structure contains all information that is necessary for lowering calls.

SmallVector< ISD::InputArg, 32 > Ins

SmallVector< ISD::OutputArg, 32 > Outs

SmallVector< SDValue, 32 > OutVals