MachineIRBuilder.cpp Source File (original) (raw)

22using namespace llvm;

25 State.MF = &MF;

26 State.MBB = nullptr;

30 State.PCSections = nullptr;

31 State.MMRA = nullptr;

33 State.Observer = nullptr;

34}

60 "Expected inlined-at fields to agree");

62 getTII().get(TargetOpcode::DBG_VALUE),

63 false, Reg, Variable, Expr));

64}

73 "Expected inlined-at fields to agree");

75 getTII().get(TargetOpcode::DBG_VALUE),

76 true, Reg, Variable, Expr));

77}

80 const MDNode *Variable,

86 "Expected inlined-at fields to agree");

88 .addFrameIndex(FI)

89 .addImm(0)

90 .addMetadata(Variable)

91 .addMetadata(Expr));

92}

95 const MDNode *Variable,

101 "Expected inlined-at fields to agree");

103

104 auto *NumericConstant = [&] () -> const Constant* {

106 if (CE->getOpcode() == Instruction::IntToPtr)

107 return CE->getOperand(0);

108 return &C;

109 }();

110

112 if (CI->getBitWidth() > 64)

113 MIB.addCImm(CI);

114 else if (CI->getBitWidth() == 1)

115 MIB.addImm(CI->getZExtValue());

116 else

117 MIB.addImm(CI->getSExtValue());

119 MIB.addFPImm(CFP);

121 MIB.addImm(0);

122 } else {

123

125 }

126

127 MIB.addImm(0).addMetadata(Variable).addMetadata(Expr);

129}

130

134 "Expected inlined-at fields to agree");

135 auto MIB = buildInstr(TargetOpcode::DBG_LABEL);

136

137 return MIB.addMetadata(Label);

138}

139

142 Align Alignment) {

144 auto MIB = buildInstr(TargetOpcode::G_DYN_STACKALLOC);

146 Size.addSrcToMIB(MIB);

147 MIB.addImm(Alignment.value());

148 return MIB;

149}

150

152 int Idx) {

154 auto MIB = buildInstr(TargetOpcode::G_FRAME_INDEX);

156 MIB.addFrameIndex(Idx);

157 return MIB;

158}

159

165 "address space mismatch");

166

167 auto MIB = buildInstr(TargetOpcode::G_GLOBAL_VALUE);

169 MIB.addGlobalAddress(GV);

170 return MIB;

171}

172

174 unsigned Idx) {

176 auto MIB = buildInstr(TargetOpcode::G_CONSTANT_POOL);

178 MIB.addConstantPoolIndex(Idx);

179 return MIB;

180}

181

183 unsigned JTI) {

184 return buildInstr(TargetOpcode::G_JUMP_TABLE, {PtrTy}, {})

185 .addJumpTableIndex(JTI);

186}

187

190 assert((Res == Op0) && "type mismatch");

191}

192

194 const LLT Op1) {

196 assert((Res == Op0 && Res == Op1) && "type mismatch");

197}

198

200 const LLT Op1) {

202 assert((Res == Op0) && "type mismatch");

203}

204

207 const SrcOp &Op1, std::optional Flags) {

210 assert(Op1.getLLTTy(*getMRI()).getScalarType().isScalar() && "invalid offset type");

211

212 return buildInstr(TargetOpcode::G_PTR_ADD, {Res}, {Op0, Op1}, Flags);

213}

214

216 const SrcOp &Op0,

217 const SrcOp &Op1) {

221}

222

223std::optional

226 std::optional Flags) {

227 assert(Res == 0 && "Res is a result argument");

228 assert(ValueTy.isScalar() && "invalid offset type");

229

230 if (Value == 0) {

231 Res = Op0;

232 return std::nullopt;

233 }

234

237 return buildPtrAdd(Res, Op0, Cst.getReg(0), Flags);

238}

239

246

248 const SrcOp &Op0,

255}

256

259 const SrcOp &Op0) {

262

264

268 "Different vector element types");

270 "Op0 has more elements");

272

273 for (auto Op : Unmerge.getInstr()->defs())

275 } else {

277 "Op0 has more size");

279 }

283 for (unsigned i = 0; i < NumberOfPadElts; ++i)

286}

287

290 const SrcOp &Op0) {

293

298 "Different vector element types");

301 "Op0 has fewer elements");

302

307 for (unsigned i = 0; i < ResTy.getNumElements(); ++i)

308 Regs.push_back(Unmerge.getReg(i));

310}

311

315

320

322 unsigned JTI,

325 "Table reg must be a pointer");

326 return buildInstr(TargetOpcode::G_BRJT)

330}

331

336

343 "creating constant with the wrong size");

344

345 assert(!Ty.isScalableVector() &&

346 "unexpected scalable vector in buildConstant");

347

348 if (Ty.isFixedVector()) {

349 auto Const = buildInstr(TargetOpcode::G_CONSTANT)

350 .addDef(getMRI()->createGenericVirtualRegister(EltTy))

353 }

354

355 auto Const = buildInstr(TargetOpcode::G_CONSTANT);

356 Const->setDebugLoc(DebugLoc());

358 Const.addCImm(&Val);

359 return Const;

360}

361

363 int64_t Val) {

366 ConstantInt *CI = ConstantInt::get(IntN, Val, true);

368}

369

375

378 "creating fconstant with the wrong size");

379

380 assert(!Ty.isPointer() && "invalid operand type");

381

382 assert(!Ty.isScalableVector() &&

383 "unexpected scalable vector in buildFConstant");

384

385 if (Ty.isFixedVector()) {

386 auto Const = buildInstr(TargetOpcode::G_FCONSTANT)

387 .addDef(getMRI()->createGenericVirtualRegister(EltTy))

389

391 }

392

393 auto Const = buildInstr(TargetOpcode::G_FCONSTANT);

394 Const->setDebugLoc(DebugLoc());

396 Const.addFPImm(&Val);

397 return Const;

398}

399

401 const APInt &Val) {

404}

405

407 double Val) {

410 auto *CFP =

413}

414

418 auto *CFP = ConstantFP::get(Ctx, Val);

420}

421

426 auto MIB = buildInstr(TargetOpcode::G_PTRAUTH_GLOBAL_VALUE);

428 MIB.addUse(Addr);

430 MIB.addUse(AddrDisc);

432 return MIB;

433}

434

438

439 auto MIB = buildInstr(TargetOpcode::G_BRCOND);

441 MIB.addMBB(&Dest);

442 return MIB;

443}

444

458

460 const DstOp &Res,

461 const SrcOp &Addr,

465

469 MIB.addMemOperand(&MMO);

470 return MIB;

471}

472

489

491 const SrcOp &Addr,

495

496 auto MIB = buildInstr(TargetOpcode::G_STORE);

499 MIB.addMemOperand(&MMO);

500 return MIB;

501}

502

516

519 return buildInstr(TargetOpcode::G_ANYEXT, Res, Op);

520}

521

526

529 std::optional Flags) {

530 return buildInstr(TargetOpcode::G_ZEXT, Res, Op, Flags);

531}

532

535 switch (TLI->getBooleanContents(IsVec, IsFP)) {

537 return TargetOpcode::G_SEXT;

539 return TargetOpcode::G_ZEXT;

540 default:

541 return TargetOpcode::G_ANYEXT;

542 }

543}

544

551

554 bool IsVector,

555 bool IsFP) {

557 switch (TLI->getBooleanContents(IsVector, IsFP)) {

564 }

565

567}

568

570 const DstOp &Res,

572 assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc ||

573 TargetOpcode::G_SEXT == ExtOpc) &&

574 "Expecting Extending Opc");

578 Op.getLLTTy(*getMRI()).isScalar());

579

580 unsigned Opcode = TargetOpcode::COPY;

582 Op.getLLTTy(*getMRI()).getSizeInBits())

583 Opcode = ExtOpc;

585 Op.getLLTTy(*getMRI()).getSizeInBits())

586 Opcode = TargetOpcode::G_TRUNC;

587 else

589

591}

592

597

602

607

610 int64_t ImmOp) {

615}

616

618 const SrcOp &Src) {

619 LLT SrcTy = Src.getLLTTy(*getMRI());

620 LLT DstTy = Dst.getLLTTy(*getMRI());

621 if (SrcTy == DstTy)

623

624 unsigned Opcode;

625 if (SrcTy.isPointerOrPointerVector())

626 Opcode = TargetOpcode::G_PTRTOINT;

628 Opcode = TargetOpcode::G_INTTOPTR;

629 else {

630 assert(!SrcTy.isPointerOrPointerVector() &&

632 Opcode = TargetOpcode::G_BITCAST;

633 }

634

636}

637

639 const SrcOp &Src,

641 LLT SrcTy = Src.getLLTTy(*getMRI());

642 LLT DstTy = Dst.getLLTTy(*getMRI());

643

644#ifndef NDEBUG

645 assert(SrcTy.isValid() && "invalid operand type");

646 assert(DstTy.isValid() && "invalid operand type");

648 "extracting off end of register");

649#endif

650

651 if (DstTy.getSizeInBits() == SrcTy.getSizeInBits()) {

652 assert(Index == 0 && "insertion past the end of a register");

654 }

655

656 auto Extract = buildInstr(TargetOpcode::G_EXTRACT);

657 Dst.addDefToMIB(*getMRI(), Extract);

658 Src.addSrcToMIB(Extract);

659 Extract.addImm(Index);

660 return Extract;

661}

662

664 return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {});

665}

666

669

670

671

674 return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);

675}

676

680

681

682

685 return buildInstr(getOpcodeForMerge(Res, TmpVec), Res, TmpVec);

686}

687

690 std::initializer_list Ops) {

693}

694

695unsigned MachineIRBuilder::getOpcodeForMerge(const DstOp &DstOp,

698 if (SrcOps[0].getLLTTy(*getMRI()).isVector())

699 return TargetOpcode::G_CONCAT_VECTORS;

700 return TargetOpcode::G_BUILD_VECTOR;

701 }

702

703 return TargetOpcode::G_MERGE_VALUES;

704}

705

708

709

710

713 return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);

714}

715

720 return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);

721}

722

727 unsigned NumRegs = OpTy.getSizeInBits() / Attrs.Ty.getSizeInBits();

729 return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);

730}

731

734

735

736

739 return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);

740}

741

744

745

746

748 return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);

749}

750

757 for (const auto &Op : Ops)

759 return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);

760}

761

763 const SrcOp &Src) {

765 return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);

766}

767

771

772

773

775 if (TmpVec[0].getLLTTy(*getMRI()).getSizeInBits() ==

776 Res.getLLTTy(*getMRI()).getElementType().getSizeInBits())

777 return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);

778 return buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC, Res, TmpVec);

779}

780

782 const SrcOp &Src) {

785 "Expected Src to match Dst elt ty");

791}

792

794 const SrcOp &Src) {

796 "Expected Src to match Dst elt ty");

797 return buildInstr(TargetOpcode::G_SPLAT_VECTOR, Res, Src);

798}

799

801 const SrcOp &Src1,

802 const SrcOp &Src2,

810 assert(DstElemTy == ElemTy1 && DstElemTy == ElemTy2);

811 assert(Mask.size() > 1 && "Scalar G_SHUFFLE_VECTOR are not supported");

812 (void)DstElemTy;

813 (void)ElemTy1;

814 (void)ElemTy2;

816 return buildInstr(TargetOpcode::G_SHUFFLE_VECTOR, {Res}, {Src1, Src2})

817 .addShuffleMask(MaskAlloc);

818}

819

822

823

824

826 return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);

827}

828

830 const SrcOp &Src,

832 unsigned Index) {

833 assert(Index + Op.getLLTTy(*getMRI()).getSizeInBits() <=

835 "insertion past the end of a register");

836

838 Op.getLLTTy(*getMRI()).getSizeInBits()) {

840 }

841

843}

844

846 unsigned Step) {

849 APInt(Bitwidth, Step));

850 auto StepVector = buildInstr(TargetOpcode::G_STEP_VECTOR);

851 StepVector->setDebugLoc(DebugLoc());

853 StepVector.addCImm(CI);

854 return StepVector;

855}

856

858 unsigned MinElts) {

859

862 ConstantInt *CI = ConstantInt::get(IntN, MinElts);

864}

865

868 auto VScale = buildInstr(TargetOpcode::G_VSCALE);

869 VScale->setDebugLoc(DebugLoc());

871 VScale.addCImm(&MinElts);

872 return VScale;

873}

874

876 const APInt &MinElts) {

880}

881

883 if (HasSideEffects && IsConvergent)

884 return TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS;

885 if (HasSideEffects)

886 return TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS;

887 if (IsConvergent)

888 return TargetOpcode::G_INTRINSIC_CONVERGENT;

889 return TargetOpcode::G_INTRINSIC;

890}

891

895 bool HasSideEffects, bool isConvergent) {

897 for (Register ResultReg : ResultRegs)

898 MIB.addDef(ResultReg);

899 MIB.addIntrinsicID(ID);

900 return MIB;

901}

902

907 bool HasSideEffects = !Attrs.getMemoryEffects().doesNotAccessMemory();

908 bool isConvergent = Attrs.hasAttribute(Attribute::Convergent);

909 return buildIntrinsic(ID, ResultRegs, HasSideEffects, isConvergent);

910}

911

914 bool HasSideEffects,

915 bool isConvergent) {

918 Result.addDefToMIB(*getMRI(), MIB);

919 MIB.addIntrinsicID(ID);

920 return MIB;

921}

922

926 bool HasSideEffects = !Attrs.getMemoryEffects().doesNotAccessMemory();

927 bool isConvergent = Attrs.hasAttribute(Attribute::Convergent);

929}

930

933 std::optional Flags) {

934 return buildInstr(TargetOpcode::G_TRUNC, Res, Op, Flags);

935}

936

939 std::optional Flags) {

940 return buildInstr(TargetOpcode::G_FPTRUNC, Res, Op, Flags);

941}

942

944 const DstOp &Res,

945 const SrcOp &Op0,

946 const SrcOp &Op1,

947 std::optional Flags) {

948 return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1}, Flags);

949}

950

952 const DstOp &Res,

953 const SrcOp &Op0,

954 const SrcOp &Op1,

955 std::optional Flags) {

956

957 return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1}, Flags);

958}

959

961 const SrcOp &Op0,

962 const SrcOp &Op1) {

963 return buildInstr(TargetOpcode::G_SCMP, Res, {Op0, Op1});

967 const SrcOp &Op0,

968 const SrcOp &Op1) {

969 return buildInstr(TargetOpcode::G_UCMP, Res, {Op0, Op1});

970}

971

975 std::optional Flags) {

976

977 return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1}, Flags);

978}

981 const SrcOp &Src0,

982 const SrcOp &Src1,

983 unsigned Idx) {

984 return buildInstr(TargetOpcode::G_INSERT_SUBVECTOR, Res,

985 {Src0, Src1, uint64_t(Idx)});

986}

987

989 const SrcOp &Src,

990 unsigned Idx) {

991 return buildInstr(TargetOpcode::G_EXTRACT_SUBVECTOR, Res,

993}

994

997 const SrcOp &Elt, const SrcOp &Idx) {

998 return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT, Res, {Val, Elt, Idx});

999}

1000

1003 const SrcOp &Idx) {

1004 return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT, Res, {Val, Idx});

1005}

1006

1008 const DstOp &OldValRes, const DstOp &SuccessRes, const SrcOp &Addr,

1010#ifndef NDEBUG

1016 assert(OldValResTy.isScalar() && "invalid operand type");

1017 assert(SuccessResTy.isScalar() && "invalid operand type");

1019 assert(CmpValTy.isValid() && "invalid operand type");

1020 assert(NewValTy.isValid() && "invalid operand type");

1021 assert(OldValResTy == CmpValTy && "type mismatch");

1022 assert(OldValResTy == NewValTy && "type mismatch");

1023#endif

1024

1025 auto MIB = buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS);

1031 MIB.addMemOperand(&MMO);

1032 return MIB;

1033}

1034

1037 const SrcOp &CmpVal, const SrcOp &NewVal,

1039#ifndef NDEBUG

1044 assert(OldValResTy.isScalar() && "invalid operand type");

1046 assert(CmpValTy.isValid() && "invalid operand type");

1047 assert(NewValTy.isValid() && "invalid operand type");

1048 assert(OldValResTy == CmpValTy && "type mismatch");

1049 assert(OldValResTy == NewValTy && "type mismatch");

1050#endif

1051

1052 auto MIB = buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG);

1057 MIB.addMemOperand(&MMO);

1058 return MIB;

1059}

1060

1062 unsigned Opcode, const DstOp &OldValRes,

1063 const SrcOp &Addr, const SrcOp &Val,

1065

1066#ifndef NDEBUG

1071 assert(ValTy.isValid() && "invalid operand type");

1072 assert(OldValResTy == ValTy && "type mismatch");

1074#endif

1075

1080 MIB.addMemOperand(&MMO);

1081 return MIB;

1082}

1083

1087 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XCHG, OldValRes, Addr, Val,

1088 MMO);

1089}

1093 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_ADD, OldValRes, Addr, Val,

1094 MMO);

1095}

1099 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_SUB, OldValRes, Addr, Val,

1100 MMO);

1101}

1105 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_AND, OldValRes, Addr, Val,

1106 MMO);

1107}

1111 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_NAND, OldValRes, Addr, Val,

1112 MMO);

1113}

1118 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_OR, OldValRes, Addr, Val,

1119 MMO);

1120}

1124 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XOR, OldValRes, Addr, Val,

1125 MMO);

1126}

1130 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MAX, OldValRes, Addr, Val,

1131 MMO);

1132}

1136 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MIN, OldValRes, Addr, Val,

1137 MMO);

1138}

1142 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMAX, OldValRes, Addr, Val,

1143 MMO);

1144}

1148 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMIN, OldValRes, Addr, Val,

1149 MMO);

1150}

1151

1154 const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,

1156 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FADD, OldValRes, Addr, Val,

1157 MMO);

1158}

1159

1163 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FSUB, OldValRes, Addr, Val,

1164 MMO);

1165}

1166

1170 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FMAX, OldValRes, Addr, Val,

1171 MMO);

1172}

1173

1177 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FMIN, OldValRes, Addr, Val,

1178 MMO);

1179}

1180

1183 const SrcOp &Addr, const SrcOp &Val,

1185 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FMAXIMUM, OldValRes, Addr,

1186 Val, MMO);

1187}

1188

1191 const SrcOp &Addr, const SrcOp &Val,

1193 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FMINIMUM, OldValRes, Addr,

1194 Val, MMO);

1195}

1196

1199 return buildInstr(TargetOpcode::G_FENCE)

1202}

1203

1205 unsigned RW,

1206 unsigned Locality,

1207 unsigned CacheType,

1209 auto MIB = buildInstr(TargetOpcode::G_PREFETCH);

1211 MIB.addImm(RW).addImm(Locality).addImm(CacheType);

1212 MIB.addMemOperand(&MMO);

1213 return MIB;

1214}

1215

1218#ifndef NDEBUG

1220#endif

1221

1223}

1224

1226 bool IsExtend) {

1227#ifndef NDEBUG

1229 assert(SrcTy.isVector() && "mismatched cast between vector and non-vector");

1231 "different number of elements in a trunc/ext");

1232 } else

1233 assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");

1234

1235 if (IsExtend)

1237 "invalid narrowing extend");

1238 else

1240 "invalid widening trunc");

1241#endif

1242}

1243

1245 const LLT Op0Ty, const LLT Op1Ty) {

1246#ifndef NDEBUG

1248 "invalid operand type");

1249 assert((ResTy == Op0Ty && ResTy == Op1Ty) && "type mismatch");

1252 else

1256 "type mismatch");

1257#endif

1258}

1259

1263 std::optional Flags) {

1264 switch (Opc) {

1265 default:

1266 break;

1267 case TargetOpcode::G_SELECT: {

1268 assert(DstOps.size() == 1 && "Invalid select");

1269 assert(SrcOps.size() == 3 && "Invalid select");

1271 DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getLLTTy(*getMRI()),

1272 SrcOps[1].getLLTTy(*getMRI()), SrcOps[2].getLLTTy(*getMRI()));

1273 break;

1274 }

1275 case TargetOpcode::G_FNEG:

1276 case TargetOpcode::G_ABS:

1277

1278 assert(DstOps.size() == 1 && "Invalid Dst");

1279 assert(SrcOps.size() == 1 && "Invalid Srcs");

1281 SrcOps[0].getLLTTy(*getMRI()));

1282 break;

1283 case TargetOpcode::G_ADD:

1284 case TargetOpcode::G_AND:

1285 case TargetOpcode::G_MUL:

1286 case TargetOpcode::G_OR:

1287 case TargetOpcode::G_SUB:

1288 case TargetOpcode::G_XOR:

1289 case TargetOpcode::G_UDIV:

1290 case TargetOpcode::G_SDIV:

1291 case TargetOpcode::G_UREM:

1292 case TargetOpcode::G_SREM:

1293 case TargetOpcode::G_SMIN:

1294 case TargetOpcode::G_SMAX:

1295 case TargetOpcode::G_UMIN:

1296 case TargetOpcode::G_UMAX:

1297 case TargetOpcode::G_UADDSAT:

1298 case TargetOpcode::G_SADDSAT:

1299 case TargetOpcode::G_USUBSAT:

1300 case TargetOpcode::G_SSUBSAT: {

1301

1302 assert(DstOps.size() == 1 && "Invalid Dst");

1303 assert(SrcOps.size() == 2 && "Invalid Srcs");

1305 SrcOps[0].getLLTTy(*getMRI()),

1306 SrcOps[1].getLLTTy(*getMRI()));

1307 break;

1308 }

1309 case TargetOpcode::G_SHL:

1310 case TargetOpcode::G_ASHR:

1311 case TargetOpcode::G_LSHR:

1312 case TargetOpcode::G_USHLSAT:

1313 case TargetOpcode::G_SSHLSAT: {

1314 assert(DstOps.size() == 1 && "Invalid Dst");

1315 assert(SrcOps.size() == 2 && "Invalid Srcs");

1317 SrcOps[0].getLLTTy(*getMRI()),

1318 SrcOps[1].getLLTTy(*getMRI()));

1319 break;

1320 }

1321 case TargetOpcode::G_SEXT:

1322 case TargetOpcode::G_ZEXT:

1323 case TargetOpcode::G_ANYEXT:

1324 assert(DstOps.size() == 1 && "Invalid Dst");

1325 assert(SrcOps.size() == 1 && "Invalid Srcs");

1327 SrcOps[0].getLLTTy(*getMRI()), true);

1328 break;

1329 case TargetOpcode::G_TRUNC:

1330 case TargetOpcode::G_FPTRUNC: {

1331 assert(DstOps.size() == 1 && "Invalid Dst");

1332 assert(SrcOps.size() == 1 && "Invalid Srcs");

1334 SrcOps[0].getLLTTy(*getMRI()), false);

1335 break;

1336 }

1337 case TargetOpcode::G_BITCAST: {

1338 assert(DstOps.size() == 1 && "Invalid Dst");

1339 assert(SrcOps.size() == 1 && "Invalid Srcs");

1340 assert(DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==

1341 SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() && "invalid bitcast");

1342 break;

1343 }

1344 case TargetOpcode::COPY:

1345 assert(DstOps.size() == 1 && "Invalid Dst");

1346

1347

1348 break;

1349 case TargetOpcode::G_FCMP:

1350 case TargetOpcode::G_ICMP: {

1351 assert(DstOps.size() == 1 && "Invalid Dst Operands");

1352 assert(SrcOps.size() == 3 && "Invalid Src Operands");

1353

1354

1356 "Expecting predicate");

1357 assert([&]() -> bool {

1361 }() && "Invalid predicate");

1362 assert(SrcOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&

1363 "Type mismatch");

1364 assert([&]() -> bool {

1365 LLT Op0Ty = SrcOps[1].getLLTTy(*getMRI());

1366 LLT DstTy = DstOps[0].getLLTTy(*getMRI());

1369 else

1372 }() && "Type Mismatch");

1373 break;

1374 }

1375 case TargetOpcode::G_UNMERGE_VALUES: {

1376 assert(!DstOps.empty() && "Invalid trivial sequence");

1377 assert(SrcOps.size() == 1 && "Invalid src for Unmerge");

1379 [&, this](const DstOp &Op) {

1380 return Op.getLLTTy(*getMRI()) ==

1381 DstOps[0].getLLTTy(*getMRI());

1382 }) &&

1383 "type mismatch in output list");

1385 DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==

1386 SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() &&

1387 "input operands do not cover output register");

1388 break;

1389 }

1390 case TargetOpcode::G_MERGE_VALUES: {

1391 assert(SrcOps.size() >= 2 && "invalid trivial sequence");

1392 assert(DstOps.size() == 1 && "Invalid Dst");

1394 [&, this](const SrcOp &Op) {

1395 return Op.getLLTTy(*getMRI()) ==

1396 SrcOps[0].getLLTTy(*getMRI());

1397 }) &&

1398 "type mismatch in input list");

1400 SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==

1401 DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&

1402 "input operands do not cover output register");

1403 assert(!DstOps[0].getLLTTy(*getMRI()).isVector() &&

1404 "vectors should be built with G_CONCAT_VECTOR or G_BUILD_VECTOR");

1405 break;

1406 }

1407 case TargetOpcode::G_EXTRACT_VECTOR_ELT: {

1408 assert(DstOps.size() == 1 && "Invalid Dst size");

1409 assert(SrcOps.size() == 2 && "Invalid Src size");

1410 assert(SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");

1411 assert((DstOps[0].getLLTTy(*getMRI()).isScalar() ||

1412 DstOps[0].getLLTTy(*getMRI()).isPointer()) &&

1413 "Invalid operand type");

1414 assert(SrcOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand type");

1415 assert(SrcOps[0].getLLTTy(*getMRI()).getElementType() ==

1416 DstOps[0].getLLTTy(*getMRI()) &&

1417 "Type mismatch");

1418 break;

1419 }

1420 case TargetOpcode::G_INSERT_VECTOR_ELT: {

1421 assert(DstOps.size() == 1 && "Invalid dst size");

1422 assert(SrcOps.size() == 3 && "Invalid src size");

1423 assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&

1424 SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");

1425 assert(DstOps[0].getLLTTy(*getMRI()).getElementType() ==

1426 SrcOps[1].getLLTTy(*getMRI()) &&

1427 "Type mismatch");

1428 assert(SrcOps[2].getLLTTy(*getMRI()).isScalar() && "Invalid index");

1429 assert(DstOps[0].getLLTTy(*getMRI()).getElementCount() ==

1430 SrcOps[0].getLLTTy(*getMRI()).getElementCount() &&

1431 "Type mismatch");

1432 break;

1433 }

1434 case TargetOpcode::G_BUILD_VECTOR: {

1436 "Must have at least 2 operands");

1437 assert(DstOps.size() == 1 && "Invalid DstOps");

1438 assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&

1439 "Res type must be a vector");

1441 [&, this](const SrcOp &Op) {

1442 return Op.getLLTTy(*getMRI()) ==

1443 SrcOps[0].getLLTTy(*getMRI());

1444 }) &&

1445 "type mismatch in input list");

1447 SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==

1448 DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&

1449 "input scalars do not exactly cover the output vector register");

1450 break;

1451 }

1452 case TargetOpcode::G_BUILD_VECTOR_TRUNC: {

1454 "Must have at least 2 operands");

1455 assert(DstOps.size() == 1 && "Invalid DstOps");

1456 assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&

1457 "Res type must be a vector");

1459 [&, this](const SrcOp &Op) {

1460 return Op.getLLTTy(*getMRI()) ==

1461 SrcOps[0].getLLTTy(*getMRI());

1462 }) &&

1463 "type mismatch in input list");

1464 break;

1465 }

1466 case TargetOpcode::G_CONCAT_VECTORS: {

1467 assert(DstOps.size() == 1 && "Invalid DstOps");

1469 "Must have at least 2 operands");

1471 [&, this](const SrcOp &Op) {

1472 return (Op.getLLTTy(*getMRI()).isVector() &&

1474 SrcOps[0].getLLTTy(*getMRI()));

1475 }) &&

1476 "type mismatch in input list");

1478 SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==

1479 DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&

1480 "input vectors do not exactly cover the output vector register");

1481 break;

1482 }

1483 case TargetOpcode::G_UADDE: {

1484 assert(DstOps.size() == 2 && "Invalid no of dst operands");

1485 assert(SrcOps.size() == 3 && "Invalid no of src operands");

1486 assert(DstOps[0].getLLTTy(*getMRI()).isScalar() && "Invalid operand");

1487 assert((DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI())) &&

1488 (DstOps[0].getLLTTy(*getMRI()) == SrcOps[1].getLLTTy(*getMRI())) &&

1489 "Invalid operand");

1490 assert(DstOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand");

1491 assert(DstOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&

1492 "type mismatch");

1493 break;

1494 }

1495 }

1496

1498 for (const DstOp &Op : DstOps)

1499 Op.addDefToMIB(*getMRI(), MIB);

1500 for (const SrcOp &Op : SrcOps)

1501 Op.addSrcToMIB(MIB);

1502 if (Flags)

1503 MIB->setFlags(*Flags);

1504 return MIB;

1505}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

Function Alias Analysis Results

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

static unsigned getIntrinsicOpcode(bool HasSideEffects, bool IsConvergent)

Definition MachineIRBuilder.cpp:882

This file declares the MachineIRBuilder class.

Promote Memory to Register

static unsigned getAddressSpace(const Value *V, unsigned MaxLookup)

static bool isValid(const char C)

Returns true if C is a valid mangled character: <0-9a-zA-Z_>.

static unsigned getNumElements(Type *Ty)

static unsigned getScalarSizeInBits(Type *Ty)

static SymbolRef::Type getType(const Symbol *Sym)

This file describes how to lower LLVM code to machine code.

static Function * getFunction(FunctionType *Ty, const Twine &Name, Module *M)

static LLVM_ABI unsigned getSizeInBits(const fltSemantics &Sem)

Returns the size of the floating point number (in bits) in the given semantics.

const fltSemantics & getSemantics() const

Class for arbitrary precision integers.

static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)

Constructs an APInt value that has the bottom loBitsSet bits set.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

size_t size() const

size - Get the array size.

bool empty() const

empty - Check if the array is empty.

This class holds the attributes for a particular argument, parameter, function, or return value.

The address of a basic block.

Predicate

This enumeration lists the possible predicates for CmpInst subclasses.

bool isFPPredicate() const

bool isIntPredicate() const

ConstantFP - Floating Point Values [float, double].

const APFloat & getValueAPF() const

This is the shared class of boolean and integer constants.

unsigned getBitWidth() const

getBitWidth - Return the scalar bitwidth of this constant.

uint64_t getZExtValue() const

Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...

A signed pointer, in the ptrauth sense.

ConstantInt * getKey() const

The Key ID, an i32 constant.

ConstantInt * getDiscriminator() const

The integer discriminator, an i64 constant, or 0.

This is an important base class in LLVM.

void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const

LLT getLLTTy(const MachineRegisterInfo &MRI) const

LLVMContext & getContext() const

getContext - Return a reference to the LLVMContext associated with this function.

PointerType * getType() const

Global values are always pointers.

static LLVM_ABI IntegerType * get(LLVMContext &C, unsigned NumBits)

This static method is the primary way of constructing an IntegerType.

constexpr unsigned getScalarSizeInBits() const

constexpr bool isScalar() const

static constexpr LLT scalar(unsigned SizeInBits)

Get a low-level scalar or aggregate "bag of bits".

constexpr bool isValid() const

constexpr uint16_t getNumElements() const

Returns the number of elements in a vector LLT.

constexpr bool isVector() const

constexpr TypeSize getSizeInBits() const

Returns the total size of the type. Must only be called on sized types.

constexpr bool isPointer() const

constexpr LLT getElementType() const

Returns the vector's element type. Only valid for vector types.

constexpr ElementCount getElementCount() const

constexpr bool isPointerOrPointerVector() const

constexpr LLT getScalarType() const

const MCInstrDesc & get(unsigned Opcode) const

Return the machine instruction descriptor that corresponds to the specified instruction opcode.

LLVM_ABI instr_iterator insert(instr_iterator I, MachineInstr *M)

Insert MI into the instruction list before I, possibly inside a bundle.

MachineInstrBundleIterator< MachineInstr > iterator

ArrayRef< int > allocateShuffleMask(ArrayRef< int > Mask)

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)

getMachineMemOperand - Allocate a new MachineMemOperand.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Function & getFunction()

Return the LLVM function that this machine code represents.

MachineInstrBuilder buildLoadFromOffset(const DstOp &Dst, const SrcOp &BasePtr, MachineMemOperand &BaseMMO, int64_t Offset)

Helper to create a load from a constant offset given a base address.

Definition MachineIRBuilder.cpp:473

MachineInstrBuilder buildAtomicRMWFMin(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_FMIN Addr, Val, MMO.

Definition MachineIRBuilder.cpp:1175

MachineInstrBuilder buildBoolExtInReg(const DstOp &Res, const SrcOp &Op, bool IsVector, bool IsFP)

Definition MachineIRBuilder.cpp:552

MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)

Insert an existing instruction at the insertion point.

Definition MachineIRBuilder.cpp:47

MachineInstrBuilder buildAtomicRMWFMaximum(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_FMAXIMUM Addr, Val, MMO.

Definition MachineIRBuilder.cpp:1182

MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_XOR Addr, Val, MMO.

Definition MachineIRBuilder.cpp:1122

MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV)

Build and insert Res = G_GLOBAL_VALUE GV.

Definition MachineIRBuilder.cpp:160

MachineInstrBuilder buildBr(MachineBasicBlock &Dest)

Build and insert G_BR Dest.

Definition MachineIRBuilder.cpp:312

LLVMContext & getContext() const

MachineInstrBuilder buildUndef(const DstOp &Res)

Build and insert Res = IMPLICIT_DEF.

Definition MachineIRBuilder.cpp:663

Value * getDeactivationSymbol()

MachineInstrBuilder buildUCmp(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)

Build and insert a Res = G_UCMP Op0, Op1.

Definition MachineIRBuilder.cpp:966

MachineInstrBuilder buildConstantPool(const DstOp &Res, unsigned Idx)

Build and insert Res = G_CONSTANT_POOL Idx.

Definition MachineIRBuilder.cpp:173

MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI)

Build and insert Res = G_JUMP_TABLE JTI.

Definition MachineIRBuilder.cpp:182

MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op, bool IsFP)

Definition MachineIRBuilder.cpp:545

MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)

Build and insert Res0, ... = G_UNMERGE_VALUES Op.

Definition MachineIRBuilder.cpp:706

MachineInstrBuilder buildSCmp(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)

Build and insert a Res = G_SCMP Op0, Op1.

Definition MachineIRBuilder.cpp:960

MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope)

Build and insert G_FENCE Ordering, Scope.

Definition MachineIRBuilder.cpp:1198

MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)

Build and insert a Res = G_SELECT Tst, Op0, Op1.

Definition MachineIRBuilder.cpp:973

MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_AND Addr, Val, MMO.

Definition MachineIRBuilder.cpp:1103

MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)

Build and inserts Res = G_AND Op, LowBitsSet(ImmOp) Since there is no G_ZEXT_INREG like G_SEXT_INREG,...

Definition MachineIRBuilder.cpp:608

MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_MIN Addr, Val, MMO.

Definition MachineIRBuilder.cpp:1134

MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)

Build and insert Res0, ... = G_EXTRACT Src, Idx0.

Definition MachineIRBuilder.cpp:638

std::optional< MachineInstrBuilder > materializePtrAdd(Register &Res, Register Op0, const LLT ValueTy, uint64_t Value, std::optional< unsigned > Flags=std::nullopt)

Materialize and insert Res = G_PTR_ADD Op0, (G_CONSTANT Value)

Definition MachineIRBuilder.cpp:224

MachineInstrBuilder buildInsertSubvector(const DstOp &Res, const SrcOp &Src0, const SrcOp &Src1, unsigned Index)

Build and insert Res = G_INSERT_SUBVECTOR Src0, Src1, Idx.

Definition MachineIRBuilder.cpp:980

MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)

Build and insert Res = G_AND Op0, Op1.

MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src)

Build and insert an appropriate cast between two registers of equal size.

Definition MachineIRBuilder.cpp:617

const TargetInstrInfo & getTII()

MachineInstrBuilder buildAtomicRMWFAdd(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_FADD Addr, Val, MMO.

Definition MachineIRBuilder.cpp:1153

MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_NAND Addr, Val, MMO.

Definition MachineIRBuilder.cpp:1109

MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)

Build and insert a Res = G_ICMP Pred, Op0, Op1.

Definition MachineIRBuilder.cpp:943

MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op)

Res = COPY Op depending on the differing sizes of Res and Op.

Definition MachineIRBuilder.cpp:603

MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op)

Build and insert Res = G_SEXT Op.

Definition MachineIRBuilder.cpp:522

MachineBasicBlock::iterator getInsertPt()

Current insertion point for new instructions.

MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op)

Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...

Definition MachineIRBuilder.cpp:593

MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src)

Build and insert a vector splat of a scalar Src using a G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idio...

Definition MachineIRBuilder.cpp:781

MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)

Build and insert Res = G_ZEXT Op.

Definition MachineIRBuilder.cpp:527

MachineInstrBuilder buildConcatVectors(const DstOp &Res, ArrayRef< Register > Ops)

Build and insert Res = G_CONCAT_VECTORS Op0, ...

Definition MachineIRBuilder.cpp:821

MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_ Addr, Val, MMO.

Definition MachineIRBuilder.cpp:1061

MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects, bool isConvergent)

Build and insert a G_INTRINSIC instruction.

Definition MachineIRBuilder.cpp:893

MDNode * getPCSections()

Get the current instruction's PC sections metadata.

MachineInstrBuilder buildVScale(const DstOp &Res, unsigned MinElts)

Build and insert Res = G_VSCALE MinElts.

Definition MachineIRBuilder.cpp:857

MachineInstrBuilder buildSplatBuildVector(const DstOp &Res, const SrcOp &Src)

Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.

Definition MachineIRBuilder.cpp:762

MachineInstrBuilder buildIndirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)

Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...

Definition MachineIRBuilder.cpp:67

unsigned getBoolExtOp(bool IsVec, bool IsFP) const

Definition MachineIRBuilder.cpp:533

MachineInstrBuilder buildObjectPtrOffset(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)

Build and insert an instruction with appropriate flags for addressing some offset of an object,...

Definition MachineIRBuilder.cpp:215

MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_UMAX Addr, Val, MMO.

Definition MachineIRBuilder.cpp:1140

MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops)

Build and insert Res = G_BUILD_VECTOR Op0, ...

Definition MachineIRBuilder.cpp:742

MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)

Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...

Definition MachineIRBuilder.cpp:94

void recordInsertion(MachineInstr *InsertedInstr) const

MachineInstrBuilder buildBrCond(const SrcOp &Tst, MachineBasicBlock &Dest)

Build and insert G_BRCOND Tst, Dest.

Definition MachineIRBuilder.cpp:435

std::optional< MachineInstrBuilder > materializeObjectPtrOffset(Register &Res, Register Op0, const LLT ValueTy, uint64_t Value)

Materialize and insert an instruction with appropriate flags for addressing some offset of an object,...

Definition MachineIRBuilder.cpp:240

MachineInstrBuilder buildMergeLikeInstr(const DstOp &Res, ArrayRef< Register > Ops)

Build and insert Res = G_MERGE_VALUES Op0, ... or Res = G_BUILD_VECTOR Op0, ... or Res = G_CONCAT_VEC...

Definition MachineIRBuilder.cpp:678

MachineInstrBuilder buildAtomicRMWFMinimum(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_FMINIMUM Addr, Val, MMO.

Definition MachineIRBuilder.cpp:1190

MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)

Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.

Definition MachineIRBuilder.cpp:1002

MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)

Build and insert Res = G_LOAD Addr, MMO.

MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)

Build and insert Res = G_PTR_ADD Op0, Op1.

Definition MachineIRBuilder.cpp:206

MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)

Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...

Definition MachineIRBuilder.cpp:598

MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res, ArrayRef< Register > Ops)

Build and insert Res = G_BUILD_VECTOR_TRUNC Op0, ...

Definition MachineIRBuilder.cpp:769

virtual MachineInstrBuilder buildFConstant(const DstOp &Res, const ConstantFP &Val)

Build and insert Res = G_FCONSTANT Val.

Definition MachineIRBuilder.cpp:370

MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)

Build and insert G_STORE Val, Addr, MMO.

Definition MachineIRBuilder.cpp:490

MachineInstrBuilder buildInstr(unsigned Opcode)

Build and insert = Opcode .

MachineInstrBuilder buildPadVectorWithUndefElements(const DstOp &Res, const SrcOp &Op0)

Build and insert a, b, ..., x = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a, b, .....

Definition MachineIRBuilder.cpp:258

void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty, const LLT Op1Ty)

Definition MachineIRBuilder.cpp:1244

MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)

Build and insert Res = G_FRAME_INDEX Idx.

Definition MachineIRBuilder.cpp:151

MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)

Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...

Definition MachineIRBuilder.cpp:54

const DebugLoc & getDL()

Getter for DebugLoc.

MachineInstrBuilder buildBuildVectorConstant(const DstOp &Res, ArrayRef< APInt > Ops)

Build and insert Res = G_BUILD_VECTOR Op0, ... where each OpN is built with G_CONSTANT.

Definition MachineIRBuilder.cpp:752

MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_UMIN Addr, Val, MMO.

Definition MachineIRBuilder.cpp:1146

void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1)

Definition MachineIRBuilder.cpp:193

void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1)

Definition MachineIRBuilder.cpp:199

MachineFunction & getMF()

Getter for the function we currently build.

MachineInstrBuilder buildDbgLabel(const MDNode *Label)

Build and insert a DBG_LABEL instructions specifying that Label is given.

Definition MachineIRBuilder.cpp:131

MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI, Register IndexReg)

Build and insert G_BRJT TablePtr, JTI, IndexReg.

Definition MachineIRBuilder.cpp:321

MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src, const SrcOp &Op, unsigned Index)

Definition MachineIRBuilder.cpp:829

MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size, Align Alignment)

Build and insert Res = G_DYN_STACKALLOC Size, Align.

Definition MachineIRBuilder.cpp:140

MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable, const MDNode *Expr)

Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in th...

Definition MachineIRBuilder.cpp:79

MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, const SrcOp &Op)

Build and insert Res = ExtOpc, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of...

Definition MachineIRBuilder.cpp:569

MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_SUB Addr, Val, MMO.

Definition MachineIRBuilder.cpp:1097

MachineInstrBuilder buildMergeValues(const DstOp &Res, ArrayRef< Register > Ops)

Build and insert Res = G_MERGE_VALUES Op0, ...

Definition MachineIRBuilder.cpp:667

MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)

Build and insert Res = G_TRUNC Op.

Definition MachineIRBuilder.cpp:932

MachineInstrBuilder buildAtomicRMWFMax(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_FMAX Addr, Val, MMO.

Definition MachineIRBuilder.cpp:1168

MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_OR Addr, Val, MMO.

Definition MachineIRBuilder.cpp:1114

const MachineBasicBlock & getMBB() const

Getter for the basic block we currently build.

MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)

Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.

Definition MachineIRBuilder.cpp:996

MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)

Build and insert Res = G_ANYEXT Op0.

Definition MachineIRBuilder.cpp:517

MachineInstrBuilder buildAtomicCmpXchgWithSuccess(const DstOp &OldValRes, const DstOp &SuccessRes, const SrcOp &Addr, const SrcOp &CmpVal, const SrcOp &NewVal, MachineMemOperand &MMO)

Build and insert OldValRes, SuccessRes = / G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr,...

Definition MachineIRBuilder.cpp:1007

MachineInstrBuilder buildDeleteTrailingVectorElements(const DstOp &Res, const SrcOp &Op0)

Build and insert a, b, ..., x, y, z = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a,...

Definition MachineIRBuilder.cpp:289

MachineRegisterInfo * getMRI()

Getter for MRI.

MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_ADD Addr, Val, MMO.

Definition MachineIRBuilder.cpp:1091

MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)

Build and insert Res = G_FPTRUNC Op.

Definition MachineIRBuilder.cpp:938

MachineInstrBuilder buildAtomicCmpXchg(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &CmpVal, const SrcOp &NewVal, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, / MMO.

Definition MachineIRBuilder.cpp:1036

MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1, const SrcOp &Src2, ArrayRef< int > Mask)

Build and insert Res = G_SHUFFLE_VECTOR Src1, Src2, Mask.

Definition MachineIRBuilder.cpp:800

void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend)

Definition MachineIRBuilder.cpp:1225

MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)

Build but don't insert = Opcode .

Definition MachineIRBuilder.cpp:40

MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)

Build and insert Res = G_PTRMASK Op0, Op1.

MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)

Build and insert Res = COPY Op.

Definition MachineIRBuilder.cpp:332

void validateUnaryOp(const LLT Res, const LLT Op0)

Definition MachineIRBuilder.cpp:188

MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA)

Build and insert Res = G_BLOCK_ADDR BA.

Definition MachineIRBuilder.cpp:1217

MDNode * getMMRAMetadata()

Get the current instruction's MMRA metadata.

MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_MAX Addr, Val, MMO.

Definition MachineIRBuilder.cpp:1128

MachineInstrBuilder buildPrefetch(const SrcOp &Addr, unsigned RW, unsigned Locality, unsigned CacheType, MachineMemOperand &MMO)

Build and insert G_PREFETCH Addr, RW, Locality, CacheType.

Definition MachineIRBuilder.cpp:1204

MachineInstrBuilder buildExtractSubvector(const DstOp &Res, const SrcOp &Src, unsigned Index)

Build and insert Res = G_EXTRACT_SUBVECTOR Src, Idx0.

Definition MachineIRBuilder.cpp:988

MachineInstrBuilder buildBrIndirect(Register Tgt)

Build and insert G_BRINDIRECT Tgt.

Definition MachineIRBuilder.cpp:316

MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Val)

Build and insert Res = G_SPLAT_VECTOR Val.

Definition MachineIRBuilder.cpp:793

MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)

Build and insert Res = Addr, MMO.

Definition MachineIRBuilder.cpp:459

void setMF(MachineFunction &MF)

Definition MachineIRBuilder.cpp:24

MachineInstrBuilder buildStepVector(const DstOp &Res, unsigned Step)

Build and insert Res = G_STEP_VECTOR Step.

Definition MachineIRBuilder.cpp:845

MachineInstrBuilder buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_FSUB Addr, Val, MMO.

Definition MachineIRBuilder.cpp:1161

MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_XCHG Addr, Val, MMO.

Definition MachineIRBuilder.cpp:1085

MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0, uint32_t NumBits)

Build and insert Res = G_PTRMASK Op0, G_CONSTANT (1 << NumBits) - 1.

Definition MachineIRBuilder.cpp:247

virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)

Build and insert Res = G_CONSTANT Val.

Definition MachineIRBuilder.cpp:337

MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)

Build and insert a Res = G_FCMP PredOp0, Op1.

Definition MachineIRBuilder.cpp:951

MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)

Build and insert Res = G_SEXT_INREG Op, ImmOp.

MachineInstrBuilder buildConstantPtrAuth(const DstOp &Res, const ConstantPtrAuth *CPA, Register Addr, Register AddrDisc)

Build and insert G_PTRAUTH_GLOBAL_VALUE.

Definition MachineIRBuilder.cpp:423

Get the register for the operand index.

const MachineInstrBuilder & addCImm(const ConstantInt *Val) const

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned TargetFlags=0) const

const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const

const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const

const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const

const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const

Add a virtual register use operand.

const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const

Add a virtual register definition operand.

A description of a memory reference used in the backend.

bool isAtomic() const

Returns true if this operation has an atomic ordering requirement of unordered or higher,...

Flags

Flags values. These may be or'd together.

@ MOLoad

The memory access reads data.

@ MOStore

The memory access writes data.

LLVM_ABI Register createGenericVirtualRegister(LLT Ty, StringRef Name="")

Create and return a new generic virtual register with low-level type Ty.

unsigned getAddressSpace() const

Return the address space of the Pointer type.

Wrapper class representing virtual and physical registers.

void reserve(size_type N)

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

LLT getLLTTy(const MachineRegisterInfo &MRI) const

void addSrcToMIB(MachineInstrBuilder &MIB) const

@ ZeroOrOneBooleanContent

@ UndefinedBooleanContent

@ ZeroOrNegativeOneBooleanContent

virtual const TargetInstrInfo * getInstrInfo() const

virtual const TargetLowering * getTargetLowering() const

LLVM Value Representation.

Type * getType() const

All values are typed, get the type of this value.

LLVM_ABI void addMetadata(unsigned KindID, MDNode &MD)

Add a metadata attachment.

static constexpr bool isKnownLT(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)

static constexpr bool isKnownGT(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ C

The default llvm calling convention, compatible with C.

LLVM_ABI AttributeSet getFnAttributes(LLVMContext &C, ID id)

Return the function attributes for an intrinsic.

This is an optimization pass for GlobalISel generic memory operations.

bool all_of(R &&range, UnaryPredicate P)

Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)

bool isa(const From &Val)

isa - Return true if the parameter to the template is an instance of one of the template type argu...

constexpr T maskTrailingZeros(unsigned N)

Create a bitmask with the N right-most bits set to 0, and all other bits set to 1.

DWARFExpression::Operation Op

LLVM_ABI APFloat getAPFloatFromSize(double Val, unsigned Size)

Returns an APFloat from Val converted to the appropriate size.

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

A collection of metadata nodes that might be associated with a memory access used by the alias-analys...

This struct is a compact representation of a valid (non-zero power of two) alignment.

constexpr uint64_t value() const

This is a hole in the type system and should not be abused.

This class contains a discriminated union of information about pointers in memory operands,...

All attributes(register class or bank and low-level type) a virtual register can have.