MachineIRBuilder.cpp Source File (original) (raw)

22using namespace llvm;

25 State.MF = &MF;

26 State.MBB = nullptr;

31 State.MMRA = nullptr;

34}

43}

48 return MIB;

49}

54 assert(isa(Variable) && "not a variable");

55 assert(cast(Expr)->isValid() && "not an expression");

57 cast(Variable)->isValidLocationForIntrinsic(getDL()) &&

58 "Expected inlined-at fields to agree");

60 getTII().get(TargetOpcode::DBG_VALUE),

61 false, Reg, Variable, Expr));

62}

67 assert(isa(Variable) && "not a variable");

68 assert(cast(Expr)->isValid() && "not an expression");

70 cast(Variable)->isValidLocationForIntrinsic(getDL()) &&

71 "Expected inlined-at fields to agree");

73 getTII().get(TargetOpcode::DBG_VALUE),

74 true, Reg, Variable, Expr));

75}

78 const MDNode *Variable,

80 assert(isa(Variable) && "not a variable");

81 assert(cast(Expr)->isValid() && "not an expression");

83 cast(Variable)->isValidLocationForIntrinsic(getDL()) &&

84 "Expected inlined-at fields to agree");

86 .addFrameIndex(FI)

87 .addImm(0)

88 .addMetadata(Variable)

89 .addMetadata(Expr));

90}

93 const MDNode *Variable,

95 assert(isa(Variable) && "not a variable");

96 assert(cast(Expr)->isValid() && "not an expression");

98 cast(Variable)->isValidLocationForIntrinsic(getDL()) &&

99 "Expected inlined-at fields to agree");

101

102 auto *NumericConstant = [&] () -> const Constant* {

103 if (const auto *CE = dyn_cast(&C))

104 if (CE->getOpcode() == Instruction::IntToPtr)

105 return CE->getOperand(0);

106 return &C;

107 }();

108

109 if (auto *CI = dyn_cast(NumericConstant)) {

110 if (CI->getBitWidth() > 64)

111 MIB.addCImm(CI);

112 else

113 MIB.addImm(CI->getZExtValue());

114 } else if (auto *CFP = dyn_cast(NumericConstant)) {

115 MIB.addFPImm(CFP);

116 } else if (isa(NumericConstant)) {

117 MIB.addImm(0);

118 } else {

119

121 }

122

123 MIB.addImm(0).addMetadata(Variable).addMetadata(Expr);

125}

126

128 assert(isa(Label) && "not a label");

129 assert(cast(Label)->isValidLocationForIntrinsic(State.DL) &&

130 "Expected inlined-at fields to agree");

131 auto MIB = buildInstr(TargetOpcode::DBG_LABEL);

132

133 return MIB.addMetadata(Label);

134}

135

138 Align Alignment) {

140 auto MIB = buildInstr(TargetOpcode::G_DYN_STACKALLOC);

142 Size.addSrcToMIB(MIB);

143 MIB.addImm(Alignment.value());

144 return MIB;

145}

146

148 int Idx) {

150 auto MIB = buildInstr(TargetOpcode::G_FRAME_INDEX);

152 MIB.addFrameIndex(Idx);

153 return MIB;

154}

155

161 "address space mismatch");

162

163 auto MIB = buildInstr(TargetOpcode::G_GLOBAL_VALUE);

165 MIB.addGlobalAddress(GV);

166 return MIB;

167}

168

170 unsigned Idx) {

172 auto MIB = buildInstr(TargetOpcode::G_CONSTANT_POOL);

174 MIB.addConstantPoolIndex(Idx);

175 return MIB;

176}

177

179 unsigned JTI) {

180 return buildInstr(TargetOpcode::G_JUMP_TABLE, {PtrTy}, {})

181 .addJumpTableIndex(JTI);

182}

183

186 assert((Res == Op0) && "type mismatch");

187}

188

190 const LLT Op1) {

192 assert((Res == Op0 && Res == Op1) && "type mismatch");

193}

194

196 const LLT Op1) {

198 assert((Res == Op0) && "type mismatch");

199}

200

203 const SrcOp &Op1, std::optional Flags) {

206 assert(Op1.getLLTTy(*getMRI()).getScalarType().isScalar() && "invalid offset type");

207

208 return buildInstr(TargetOpcode::G_PTR_ADD, {Res}, {Op0, Op1}, Flags);

209}

210

211std::optional

214 assert(Res == 0 && "Res is a result argument");

216

217 if (Value == 0) {

218 Res = Op0;

219 return std::nullopt;

220 }

221

224 return buildPtrAdd(Res, Op0, Cst.getReg(0));

225}

226

228 const SrcOp &Op0,

233 buildConstant(MaskReg, maskTrailingZeros<uint64_t>(NumBits));

235}

236

239 const SrcOp &Op0) {

242

244

248 "Different vector element types");

250 "Op0 has more elements");

252

253 for (auto Op : Unmerge.getInstr()->defs())

255 } else {

257 "Op0 has more size");

259 }

263 for (unsigned i = 0; i < NumberOfPadElts; ++i)

266}

267

270 const SrcOp &Op0) {

273

278 "Different vector element types");

281 "Op0 has fewer elements");

282

287 for (unsigned i = 0; i < ResTy.getNumElements(); ++i)

288 Regs.push_back(Unmerge.getReg(i));

290}

291

294}

295

297 assert(getMRI()->getType(Tgt).isPointer() && "invalid branch destination");

299}

300

302 unsigned JTI,

305 "Table reg must be a pointer");

306 return buildInstr(TargetOpcode::G_BRJT)

310}

311

314 return buildInstr(TargetOpcode::COPY, Res, Op);

315}

316

322 "creating constant with the wrong size");

323

325 "unexpected scalable vector in buildConstant");

326

328 auto Const = buildInstr(TargetOpcode::G_CONSTANT)

329 .addDef(getMRI()->createGenericVirtualRegister(EltTy))

332 }

333

334 auto Const = buildInstr(TargetOpcode::G_CONSTANT);

335 Const->setDebugLoc(DebugLoc());

337 Const.addCImm(&Val);

338 return Const;

339}

340

342 int64_t Val) {

345 ConstantInt *CI = ConstantInt::get(IntN, Val, true);

347}

348

353

356 "creating fconstant with the wrong size");

357

359

361 "unexpected scalable vector in buildFConstant");

362

364 auto Const = buildInstr(TargetOpcode::G_FCONSTANT)

365 .addDef(getMRI()->createGenericVirtualRegister(EltTy))

367

369 }

370

371 auto Const = buildInstr(TargetOpcode::G_FCONSTANT);

372 Const->setDebugLoc(DebugLoc());

374 Const.addFPImm(&Val);

375 return Const;

376}

377

379 const APInt &Val) {

382}

383

385 double Val) {

388 auto *CFP =

391}

392

396 auto *CFP = ConstantFP::get(Ctx, Val);

398}

399

404 auto MIB = buildInstr(TargetOpcode::G_PTRAUTH_GLOBAL_VALUE);

406 MIB.addUse(Addr);

408 MIB.addUse(AddrDisc);

410 return MIB;

411}

412

416

417 auto MIB = buildInstr(TargetOpcode::G_BRCOND);

419 MIB.addMBB(&Dest);

420 return MIB;

421}

422

430

431 LLT Ty = Dst.getLLTTy(*getMRI());

435}

436

438 const DstOp &Res,

442 assert(Addr.getLLTTy(*getMRI()).isPointer() && "invalid operand type");

443

446 Addr.addSrcToMIB(MIB);

447 MIB.addMemOperand(&MMO);

448 return MIB;

449}

450

452 const DstOp &Dst, const SrcOp &BasePtr,

454 LLT LoadTy = Dst.getLLTTy(*getMRI());

457

458 if (Offset == 0)

459 return buildLoad(Dst, BasePtr, *OffsetMMO);

460

461 LLT PtrTy = BasePtr.getLLTTy(*getMRI());

466}

467

472 assert(Addr.getLLTTy(*getMRI()).isPointer() && "invalid operand type");

473

474 auto MIB = buildInstr(TargetOpcode::G_STORE);

476 Addr.addSrcToMIB(MIB);

477 MIB.addMemOperand(&MMO);

478 return MIB;

479}

480

488

493}

494

497 return buildInstr(TargetOpcode::G_ANYEXT, Res, Op);

498}

499

502 return buildInstr(TargetOpcode::G_SEXT, Res, Op);

503}

504

507 std::optional Flags) {

508 return buildInstr(TargetOpcode::G_ZEXT, Res, Op, Flags);

509}

510

513 switch (TLI->getBooleanContents(IsVec, IsFP)) {

515 return TargetOpcode::G_SEXT;

517 return TargetOpcode::G_ZEXT;

518 default:

519 return TargetOpcode::G_ANYEXT;

520 }

521}

522

525 bool IsFP) {

528}

529

532 bool IsVector,

533 bool IsFP) {

535 switch (TLI->getBooleanContents(IsVector, IsFP)) {

542 }

543

545}

546

548 const DstOp &Res,

550 assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc ||

551 TargetOpcode::G_SEXT == ExtOpc) &&

552 "Expecting Extending Opc");

556 Op.getLLTTy(*getMRI()).isScalar());

557

558 unsigned Opcode = TargetOpcode::COPY;

560 Op.getLLTTy(*getMRI()).getSizeInBits())

561 Opcode = ExtOpc;

563 Op.getLLTTy(*getMRI()).getSizeInBits())

564 Opcode = TargetOpcode::G_TRUNC;

565 else

567

569}

570

574}

575

579}

580

584}

585

588 int64_t ImmOp) {

593}

594

596 const SrcOp &Src) {

597 LLT SrcTy = Src.getLLTTy(*getMRI());

598 LLT DstTy = Dst.getLLTTy(*getMRI());

599 if (SrcTy == DstTy)

601

602 unsigned Opcode;

604 Opcode = TargetOpcode::G_PTRTOINT;

606 Opcode = TargetOpcode::G_INTTOPTR;

607 else {

610 Opcode = TargetOpcode::G_BITCAST;

611 }

612

614}

615

617 const SrcOp &Src,

619 LLT SrcTy = Src.getLLTTy(*getMRI());

620 LLT DstTy = Dst.getLLTTy(*getMRI());

621

622#ifndef NDEBUG

623 assert(SrcTy.isValid() && "invalid operand type");

624 assert(DstTy.isValid() && "invalid operand type");

626 "extracting off end of register");

627#endif

628

630 assert(Index == 0 && "insertion past the end of a register");

632 }

633

634 auto Extract = buildInstr(TargetOpcode::G_EXTRACT);

635 Dst.addDefToMIB(*getMRI(), Extract);

636 Src.addSrcToMIB(Extract);

637 Extract.addImm(Index);

638 return Extract;

639}

640

642 return buildInstr(TargetOpcode::G_IMPLICIT_DEF, {Res}, {});

643}

644

647

648

649

652 return buildInstr(TargetOpcode::G_MERGE_VALUES, Res, TmpVec);

653}

654

658

659

660

663 return buildInstr(getOpcodeForMerge(Res, TmpVec), Res, TmpVec);

664}

665

668 std::initializer_list Ops) {

669 assert(Ops.size() > 1);

670 return buildInstr(getOpcodeForMerge(Res, Ops), Res, Ops);

671}

672

673unsigned MachineIRBuilder::getOpcodeForMerge(const DstOp &DstOp,

676 if (SrcOps[0].getLLTTy(*getMRI()).isVector())

677 return TargetOpcode::G_CONCAT_VECTORS;

678 return TargetOpcode::G_BUILD_VECTOR;

679 }

680

681 return TargetOpcode::G_MERGE_VALUES;

682}

683

686

687

688

691 return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);

692}

693

698 return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);

699}

700

703

704

705

708 return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op);

709}

710

713

714

715

717 return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);

718}

719

726 for (const auto &Op : Ops)

728 return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);

729}

730

732 const SrcOp &Src) {

734 return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);

735}

736

740

741

742

744 if (TmpVec[0].getLLTTy(*getMRI()).getSizeInBits() ==

745 Res.getLLTTy(*getMRI()).getElementType().getSizeInBits())

746 return buildInstr(TargetOpcode::G_BUILD_VECTOR, Res, TmpVec);

747 return buildInstr(TargetOpcode::G_BUILD_VECTOR_TRUNC, Res, TmpVec);

748}

749

751 const SrcOp &Src) {

754 "Expected Src to match Dst elt ty");

760}

761

763 const SrcOp &Src) {

765 "Expected Src to match Dst elt ty");

766 return buildInstr(TargetOpcode::G_SPLAT_VECTOR, Res, Src);

767}

768

770 const SrcOp &Src1,

771 const SrcOp &Src2,

779 assert(DstElemTy == ElemTy1 && DstElemTy == ElemTy2);

780 (void)DstElemTy;

781 (void)ElemTy1;

782 (void)ElemTy2;

784 return buildInstr(TargetOpcode::G_SHUFFLE_VECTOR, {Res}, {Src1, Src2})

785 .addShuffleMask(MaskAlloc);

786}

787

790

791

792

794 return buildInstr(TargetOpcode::G_CONCAT_VECTORS, Res, TmpVec);

795}

796

798 const SrcOp &Src,

800 unsigned Index) {

801 assert(Index + Op.getLLTTy(*getMRI()).getSizeInBits() <=

803 "insertion past the end of a register");

804

806 Op.getLLTTy(*getMRI()).getSizeInBits()) {

808 }

809

811}

812

814 unsigned Step) {

817 APInt(Bitwidth, Step));

818 auto StepVector = buildInstr(TargetOpcode::G_STEP_VECTOR);

819 StepVector->setDebugLoc(DebugLoc());

821 StepVector.addCImm(CI);

822 return StepVector;

823}

824

826 unsigned MinElts) {

827

830 ConstantInt *CI = ConstantInt::get(IntN, MinElts);

832}

833

836 auto VScale = buildInstr(TargetOpcode::G_VSCALE);

837 VScale->setDebugLoc(DebugLoc());

839 VScale.addCImm(&MinElts);

840 return VScale;

841}

842

844 const APInt &MinElts) {

848}

849

851 if (HasSideEffects && IsConvergent)

852 return TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS;

853 if (HasSideEffects)

854 return TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS;

855 if (IsConvergent)

856 return TargetOpcode::G_INTRINSIC_CONVERGENT;

857 return TargetOpcode::G_INTRINSIC;

858}

859

863 bool HasSideEffects, bool isConvergent) {

865 for (unsigned ResultReg : ResultRegs)

866 MIB.addDef(ResultReg);

867 MIB.addIntrinsicID(ID);

868 return MIB;

869}

870

875 bool HasSideEffects = !Attrs.getMemoryEffects().doesNotAccessMemory();

876 bool isConvergent = Attrs.hasFnAttr(Attribute::Convergent);

877 return buildIntrinsic(ID, ResultRegs, HasSideEffects, isConvergent);

878}

879

882 bool HasSideEffects,

883 bool isConvergent) {

886 Result.addDefToMIB(*getMRI(), MIB);

887 MIB.addIntrinsicID(ID);

888 return MIB;

889}

890

894 bool HasSideEffects = !Attrs.getMemoryEffects().doesNotAccessMemory();

895 bool isConvergent = Attrs.hasFnAttr(Attribute::Convergent);

901 std::optional Flags) {

902 return buildInstr(TargetOpcode::G_TRUNC, Res, Op, Flags);

903}

904

907 std::optional Flags) {

908 return buildInstr(TargetOpcode::G_FPTRUNC, Res, Op, Flags);

909}

910

912 const DstOp &Res,

913 const SrcOp &Op0,

914 const SrcOp &Op1,

915 std::optional Flags) {

916 return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1}, Flags);

917}

918

920 const DstOp &Res,

921 const SrcOp &Op0,

922 const SrcOp &Op1,

923 std::optional Flags) {

924

925 return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1}, Flags);

926}

927

929 const SrcOp &Op0,

930 const SrcOp &Op1) {

931 return buildInstr(TargetOpcode::G_SCMP, Res, {Op0, Op1});

932}

933

935 const SrcOp &Op0,

936 const SrcOp &Op1) {

937 return buildInstr(TargetOpcode::G_UCMP, Res, {Op0, Op1});

938}

939

943 std::optional Flags) {

944

945 return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1}, Flags);

946}

947

949 const SrcOp &Src0,

950 const SrcOp &Src1,

951 unsigned Idx) {

952 return buildInstr(TargetOpcode::G_INSERT_SUBVECTOR, Res,

954}

955

957 const SrcOp &Src,

958 unsigned Idx) {

959 return buildInstr(TargetOpcode::G_EXTRACT_SUBVECTOR, Res,

961}

962

966 return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT, Res, {Val, Elt, Idx});

967}

968

972 return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT, Res, {Val, Idx});

973}

974

978#ifndef NDEBUG

984 assert(OldValResTy.isScalar() && "invalid operand type");

985 assert(SuccessResTy.isScalar() && "invalid operand type");

987 assert(CmpValTy.isValid() && "invalid operand type");

988 assert(NewValTy.isValid() && "invalid operand type");

989 assert(OldValResTy == CmpValTy && "type mismatch");

990 assert(OldValResTy == NewValTy && "type mismatch");

991#endif

992

993 auto MIB = buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS);

996 Addr.addSrcToMIB(MIB);

999 MIB.addMemOperand(&MMO);

1000 return MIB;

1001}

1002

1005 const SrcOp &CmpVal, const SrcOp &NewVal,

1007#ifndef NDEBUG

1012 assert(OldValResTy.isScalar() && "invalid operand type");

1014 assert(CmpValTy.isValid() && "invalid operand type");

1015 assert(NewValTy.isValid() && "invalid operand type");

1016 assert(OldValResTy == CmpValTy && "type mismatch");

1017 assert(OldValResTy == NewValTy && "type mismatch");

1018#endif

1019

1020 auto MIB = buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG);

1022 Addr.addSrcToMIB(MIB);

1025 MIB.addMemOperand(&MMO);

1026 return MIB;

1027}

1028

1030 unsigned Opcode, const DstOp &OldValRes,

1033

1034#ifndef NDEBUG

1039 assert(ValTy.isValid() && "invalid operand type");

1040 assert(OldValResTy == ValTy && "type mismatch");

1042#endif

1043

1046 Addr.addSrcToMIB(MIB);

1048 MIB.addMemOperand(&MMO);

1049 return MIB;

1050}

1051

1055 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XCHG, OldValRes, Addr, Val,

1056 MMO);

1057}

1061 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_ADD, OldValRes, Addr, Val,

1062 MMO);

1063}

1067 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_SUB, OldValRes, Addr, Val,

1068 MMO);

1069}

1073 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_AND, OldValRes, Addr, Val,

1074 MMO);

1075}

1079 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_NAND, OldValRes, Addr, Val,

1080 MMO);

1081}

1086 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_OR, OldValRes, Addr, Val,

1087 MMO);

1088}

1092 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XOR, OldValRes, Addr, Val,

1093 MMO);

1094}

1098 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MAX, OldValRes, Addr, Val,

1099 MMO);

1100}

1104 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MIN, OldValRes, Addr, Val,

1105 MMO);

1106}

1110 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMAX, OldValRes, Addr, Val,

1111 MMO);

1112}

1116 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMIN, OldValRes, Addr, Val,

1117 MMO);

1118}

1119

1124 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FADD, OldValRes, Addr, Val,

1125 MMO);

1126}

1127

1131 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FSUB, OldValRes, Addr, Val,

1132 MMO);

1133}

1134

1138 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FMAX, OldValRes, Addr, Val,

1139 MMO);

1140}

1141

1145 return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FMIN, OldValRes, Addr, Val,

1146 MMO);

1147}

1148

1151 return buildInstr(TargetOpcode::G_FENCE)

1154}

1155

1157 unsigned RW,

1158 unsigned Locality,

1159 unsigned CacheType,

1161 auto MIB = buildInstr(TargetOpcode::G_PREFETCH);

1162 Addr.addSrcToMIB(MIB);

1163 MIB.addImm(RW).addImm(Locality).addImm(CacheType);

1164 MIB.addMemOperand(&MMO);

1165 return MIB;

1166}

1167

1170#ifndef NDEBUG

1172#endif

1173

1175}

1176

1178 bool IsExtend) {

1179#ifndef NDEBUG

1181 assert(SrcTy.isVector() && "mismatched cast between vector and non-vector");

1183 "different number of elements in a trunc/ext");

1184 } else

1186

1187 if (IsExtend)

1189 "invalid narrowing extend");

1190 else

1192 "invalid widening trunc");

1193#endif

1194}

1195

1197 const LLT Op0Ty, const LLT Op1Ty) {

1198#ifndef NDEBUG

1200 "invalid operand type");

1201 assert((ResTy == Op0Ty && ResTy == Op1Ty) && "type mismatch");

1204 else

1208 "type mismatch");

1209#endif

1210}

1211

1215 std::optional Flags) {

1216 switch (Opc) {

1217 default:

1218 break;

1219 case TargetOpcode::G_SELECT: {

1220 assert(DstOps.size() == 1 && "Invalid select");

1221 assert(SrcOps.size() == 3 && "Invalid select");

1223 DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getLLTTy(*getMRI()),

1224 SrcOps[1].getLLTTy(*getMRI()), SrcOps[2].getLLTTy(*getMRI()));

1225 break;

1226 }

1227 case TargetOpcode::G_FNEG:

1228 case TargetOpcode::G_ABS:

1229

1230 assert(DstOps.size() == 1 && "Invalid Dst");

1231 assert(SrcOps.size() == 1 && "Invalid Srcs");

1233 SrcOps[0].getLLTTy(*getMRI()));

1234 break;

1235 case TargetOpcode::G_ADD:

1236 case TargetOpcode::G_AND:

1237 case TargetOpcode::G_MUL:

1238 case TargetOpcode::G_OR:

1239 case TargetOpcode::G_SUB:

1240 case TargetOpcode::G_XOR:

1241 case TargetOpcode::G_UDIV:

1242 case TargetOpcode::G_SDIV:

1243 case TargetOpcode::G_UREM:

1244 case TargetOpcode::G_SREM:

1245 case TargetOpcode::G_SMIN:

1246 case TargetOpcode::G_SMAX:

1247 case TargetOpcode::G_UMIN:

1248 case TargetOpcode::G_UMAX:

1249 case TargetOpcode::G_UADDSAT:

1250 case TargetOpcode::G_SADDSAT:

1251 case TargetOpcode::G_USUBSAT:

1252 case TargetOpcode::G_SSUBSAT: {

1253

1254 assert(DstOps.size() == 1 && "Invalid Dst");

1255 assert(SrcOps.size() == 2 && "Invalid Srcs");

1257 SrcOps[0].getLLTTy(*getMRI()),

1258 SrcOps[1].getLLTTy(*getMRI()));

1259 break;

1260 }

1261 case TargetOpcode::G_SHL:

1262 case TargetOpcode::G_ASHR:

1263 case TargetOpcode::G_LSHR:

1264 case TargetOpcode::G_USHLSAT:

1265 case TargetOpcode::G_SSHLSAT: {

1266 assert(DstOps.size() == 1 && "Invalid Dst");

1267 assert(SrcOps.size() == 2 && "Invalid Srcs");

1269 SrcOps[0].getLLTTy(*getMRI()),

1270 SrcOps[1].getLLTTy(*getMRI()));

1271 break;

1272 }

1273 case TargetOpcode::G_SEXT:

1274 case TargetOpcode::G_ZEXT:

1275 case TargetOpcode::G_ANYEXT:

1276 assert(DstOps.size() == 1 && "Invalid Dst");

1277 assert(SrcOps.size() == 1 && "Invalid Srcs");

1279 SrcOps[0].getLLTTy(*getMRI()), true);

1280 break;

1281 case TargetOpcode::G_TRUNC:

1282 case TargetOpcode::G_FPTRUNC: {

1283 assert(DstOps.size() == 1 && "Invalid Dst");

1284 assert(SrcOps.size() == 1 && "Invalid Srcs");

1286 SrcOps[0].getLLTTy(*getMRI()), false);

1287 break;

1288 }

1289 case TargetOpcode::G_BITCAST: {

1290 assert(DstOps.size() == 1 && "Invalid Dst");

1291 assert(SrcOps.size() == 1 && "Invalid Srcs");

1292 assert(DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==

1293 SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() && "invalid bitcast");

1294 break;

1295 }

1296 case TargetOpcode::COPY:

1297 assert(DstOps.size() == 1 && "Invalid Dst");

1298

1299

1300 break;

1301 case TargetOpcode::G_FCMP:

1302 case TargetOpcode::G_ICMP: {

1303 assert(DstOps.size() == 1 && "Invalid Dst Operands");

1304 assert(SrcOps.size() == 3 && "Invalid Src Operands");

1305

1306

1308 "Expecting predicate");

1309 assert([&]() -> bool {

1313 }() && "Invalid predicate");

1314 assert(SrcOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&

1315 "Type mismatch");

1316 assert([&]() -> bool {

1317 LLT Op0Ty = SrcOps[1].getLLTTy(*getMRI());

1318 LLT DstTy = DstOps[0].getLLTTy(*getMRI());

1321 else

1324 }() && "Type Mismatch");

1325 break;

1326 }

1327 case TargetOpcode::G_UNMERGE_VALUES: {

1328 assert(!DstOps.empty() && "Invalid trivial sequence");

1329 assert(SrcOps.size() == 1 && "Invalid src for Unmerge");

1331 [&, this](const DstOp &Op) {

1332 return Op.getLLTTy(*getMRI()) ==

1333 DstOps[0].getLLTTy(*getMRI());

1334 }) &&

1335 "type mismatch in output list");

1337 DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==

1338 SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() &&

1339 "input operands do not cover output register");

1340 break;

1341 }

1342 case TargetOpcode::G_MERGE_VALUES: {

1343 assert(SrcOps.size() >= 2 && "invalid trivial sequence");

1344 assert(DstOps.size() == 1 && "Invalid Dst");

1346 [&, this](const SrcOp &Op) {

1347 return Op.getLLTTy(*getMRI()) ==

1348 SrcOps[0].getLLTTy(*getMRI());

1349 }) &&

1350 "type mismatch in input list");

1352 SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==

1353 DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&

1354 "input operands do not cover output register");

1355 assert(!DstOps[0].getLLTTy(*getMRI()).isVector() &&

1356 "vectors should be built with G_CONCAT_VECTOR or G_BUILD_VECTOR");

1357 break;

1358 }

1359 case TargetOpcode::G_EXTRACT_VECTOR_ELT: {

1360 assert(DstOps.size() == 1 && "Invalid Dst size");

1361 assert(SrcOps.size() == 2 && "Invalid Src size");

1362 assert(SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");

1363 assert((DstOps[0].getLLTTy(*getMRI()).isScalar() ||

1364 DstOps[0].getLLTTy(*getMRI()).isPointer()) &&

1365 "Invalid operand type");

1366 assert(SrcOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand type");

1367 assert(SrcOps[0].getLLTTy(*getMRI()).getElementType() ==

1368 DstOps[0].getLLTTy(*getMRI()) &&

1369 "Type mismatch");

1370 break;

1371 }

1372 case TargetOpcode::G_INSERT_VECTOR_ELT: {

1373 assert(DstOps.size() == 1 && "Invalid dst size");

1374 assert(SrcOps.size() == 3 && "Invalid src size");

1375 assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&

1376 SrcOps[0].getLLTTy(*getMRI()).isVector() && "Invalid operand type");

1377 assert(DstOps[0].getLLTTy(*getMRI()).getElementType() ==

1378 SrcOps[1].getLLTTy(*getMRI()) &&

1379 "Type mismatch");

1380 assert(SrcOps[2].getLLTTy(*getMRI()).isScalar() && "Invalid index");

1381 assert(DstOps[0].getLLTTy(*getMRI()).getElementCount() ==

1382 SrcOps[0].getLLTTy(*getMRI()).getElementCount() &&

1383 "Type mismatch");

1384 break;

1385 }

1386 case TargetOpcode::G_BUILD_VECTOR: {

1388 "Must have at least 2 operands");

1389 assert(DstOps.size() == 1 && "Invalid DstOps");

1390 assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&

1391 "Res type must be a vector");

1393 [&, this](const SrcOp &Op) {

1394 return Op.getLLTTy(*getMRI()) ==

1395 SrcOps[0].getLLTTy(*getMRI());

1396 }) &&

1397 "type mismatch in input list");

1399 SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==

1400 DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&

1401 "input scalars do not exactly cover the output vector register");

1402 break;

1403 }

1404 case TargetOpcode::G_BUILD_VECTOR_TRUNC: {

1406 "Must have at least 2 operands");

1407 assert(DstOps.size() == 1 && "Invalid DstOps");

1408 assert(DstOps[0].getLLTTy(*getMRI()).isVector() &&

1409 "Res type must be a vector");

1411 [&, this](const SrcOp &Op) {

1412 return Op.getLLTTy(*getMRI()) ==

1413 SrcOps[0].getLLTTy(*getMRI());

1414 }) &&

1415 "type mismatch in input list");

1416 break;

1417 }

1418 case TargetOpcode::G_CONCAT_VECTORS: {

1419 assert(DstOps.size() == 1 && "Invalid DstOps");

1421 "Must have at least 2 operands");

1423 [&, this](const SrcOp &Op) {

1424 return (Op.getLLTTy(*getMRI()).isVector() &&

1426 SrcOps[0].getLLTTy(*getMRI()));

1427 }) &&

1428 "type mismatch in input list");

1430 SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() ==

1431 DstOps[0].getLLTTy(*getMRI()).getSizeInBits() &&

1432 "input vectors do not exactly cover the output vector register");

1433 break;

1434 }

1435 case TargetOpcode::G_UADDE: {

1436 assert(DstOps.size() == 2 && "Invalid no of dst operands");

1437 assert(SrcOps.size() == 3 && "Invalid no of src operands");

1438 assert(DstOps[0].getLLTTy(*getMRI()).isScalar() && "Invalid operand");

1439 assert((DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI())) &&

1440 (DstOps[0].getLLTTy(*getMRI()) == SrcOps[1].getLLTTy(*getMRI())) &&

1441 "Invalid operand");

1442 assert(DstOps[1].getLLTTy(*getMRI()).isScalar() && "Invalid operand");

1443 assert(DstOps[1].getLLTTy(*getMRI()) == SrcOps[2].getLLTTy(*getMRI()) &&

1444 "type mismatch");

1445 break;

1446 }

1447 }

1448

1450 for (const DstOp &Op : DstOps)

1451 Op.addDefToMIB(*getMRI(), MIB);

1452 for (const SrcOp &Op : SrcOps)

1453 Op.addSrcToMIB(MIB);

1454 if (Flags)

1455 MIB->setFlags(*Flags);

1456 return MIB;

1457}

Function Alias Analysis Results

Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx

static Function * getFunction(Constant *C)

static unsigned getIntrinsicOpcode(bool HasSideEffects, bool IsConvergent)

This file declares the MachineIRBuilder class.

static unsigned getAddressSpace(const Value *V, unsigned MaxLookup)

static bool isValid(const char C)

Returns true if C is a valid mangled character: <0-9a-zA-Z_>.

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

static unsigned getNumElements(Type *Ty)

static unsigned getScalarSizeInBits(Type *Ty)

static SymbolRef::Type getType(const Symbol *Sym)

This file describes how to lower LLVM code to machine code.

const fltSemantics & getSemantics() const

Class for arbitrary precision integers.

static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)

Constructs an APInt value that has the bottom loBitsSet bits set.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

size_t size() const

size - Get the array size.

bool empty() const

empty - Check if the array is empty.

The address of a basic block.

Predicate

This enumeration lists the possible predicates for CmpInst subclasses.

bool isFPPredicate() const

bool isIntPredicate() const

ConstantFP - Floating Point Values [float, double].

const APFloat & getValueAPF() const

This is the shared class of boolean and integer constants.

unsigned getBitWidth() const

getBitWidth - Return the scalar bitwidth of this constant.

uint64_t getZExtValue() const

Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...

A signed pointer, in the ptrauth sense.

ConstantInt * getKey() const

The Key ID, an i32 constant.

ConstantInt * getDiscriminator() const

The integer discriminator, an i64 constant, or 0.

This is an important base class in LLVM.

This class represents an Operation in the Expression.

void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const

LLT getLLTTy(const MachineRegisterInfo &MRI) const

LLVMContext & getContext() const

getContext - Return a reference to the LLVMContext associated with this function.

PointerType * getType() const

Global values are always pointers.

static IntegerType * get(LLVMContext &C, unsigned NumBits)

This static method is the primary way of constructing an IntegerType.

constexpr bool isScalableVector() const

Returns true if the LLT is a scalable vector.

constexpr unsigned getScalarSizeInBits() const

constexpr bool isScalar() const

static constexpr LLT scalar(unsigned SizeInBits)

Get a low-level scalar or aggregate "bag of bits".

constexpr bool isValid() const

constexpr uint16_t getNumElements() const

Returns the number of elements in a vector LLT.

constexpr bool isVector() const

constexpr TypeSize getSizeInBits() const

Returns the total size of the type. Must only be called on sized types.

constexpr bool isPointer() const

constexpr LLT getElementType() const

Returns the vector's element type. Only valid for vector types.

constexpr ElementCount getElementCount() const

constexpr bool isPointerOrPointerVector() const

constexpr bool isFixedVector() const

Returns true if the LLT is a fixed vector.

constexpr LLT getScalarType() const

const MCInstrDesc & get(unsigned Opcode) const

Return the machine instruction descriptor that corresponds to the specified instruction opcode.

instr_iterator insert(instr_iterator I, MachineInstr *M)

Insert MI into the instruction list before I, possibly inside a bundle.

MachineInstrBundleIterator< MachineInstr > iterator

ArrayRef< int > allocateShuffleMask(ArrayRef< int > Mask)

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)

getMachineMemOperand - Allocate a new MachineMemOperand.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Function & getFunction()

Return the LLVM function that this machine code represents.

MachineInstrBuilder buildLoadFromOffset(const DstOp &Dst, const SrcOp &BasePtr, MachineMemOperand &BaseMMO, int64_t Offset)

Helper to create a load from a constant offset given a base address.

MachineInstrBuilder buildAtomicRMWFMin(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_FMIN Addr, Val, MMO.

MachineInstrBuilder buildBoolExtInReg(const DstOp &Res, const SrcOp &Op, bool IsVector, bool IsFP)

MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)

Insert an existing instruction at the insertion point.

MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_XOR Addr, Val, MMO.

MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV)

Build and insert Res = G_GLOBAL_VALUE GV.

MachineInstrBuilder buildBr(MachineBasicBlock &Dest)

Build and insert G_BR Dest.

std::optional< MachineInstrBuilder > materializePtrAdd(Register &Res, Register Op0, const LLT ValueTy, uint64_t Value)

Materialize and insert Res = G_PTR_ADD Op0, (G_CONSTANT Value)

LLVMContext & getContext() const

MachineInstrBuilder buildUndef(const DstOp &Res)

Build and insert Res = IMPLICIT_DEF.

MachineInstrBuilder buildUCmp(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)

Build and insert a Res = G_UCMP Op0, Op1.

MachineInstrBuilder buildConstantPool(const DstOp &Res, unsigned Idx)

Build and insert Res = G_CONSTANT_POOL Idx.

MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI)

Build and insert Res = G_JUMP_TABLE JTI.

MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op, bool IsFP)

MachineInstrBuilder buildUnmerge(ArrayRef< LLT > Res, const SrcOp &Op)

Build and insert Res0, ... = G_UNMERGE_VALUES Op.

MachineInstrBuilder buildSCmp(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)

Build and insert a Res = G_SCMP Op0, Op1.

MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope)

Build and insert G_FENCE Ordering, Scope.

MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)

Build and insert a Res = G_SELECT Tst, Op0, Op1.

MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_AND Addr, Val, MMO.

MachineInstrBuilder buildZExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)

Build and inserts Res = G_AND Op, LowBitsSet(ImmOp) Since there is no G_ZEXT_INREG like G_SEXT_INREG,...

MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_MIN Addr, Val, MMO.

MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index)

Build and insert Res0, ... = G_EXTRACT Src, Idx0.

MachineInstrBuilder buildInsertSubvector(const DstOp &Res, const SrcOp &Src0, const SrcOp &Src1, unsigned Index)

Build and insert Res = G_INSERT_SUBVECTOR Src0, Src1, Idx.

MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)

Build and insert Res = G_AND Op0, Op1.

MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src)

Build and insert an appropriate cast between two registers of equal size.

const TargetInstrInfo & getTII()

MachineInstrBuilder buildAtomicRMWFAdd(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_FADD Addr, Val, MMO.

MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_NAND Addr, Val, MMO.

MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)

Build and insert a Res = G_ICMP Pred, Op0, Op1.

MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op)

Res = COPY Op depending on the differing sizes of Res and Op.

MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op)

Build and insert Res = G_SEXT Op.

MachineBasicBlock::iterator getInsertPt()

Current insertion point for new instructions.

MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op)

Build and insert Res = G_SEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...

MachineInstrBuilder buildShuffleSplat(const DstOp &Res, const SrcOp &Src)

Build and insert a vector splat of a scalar Src using a G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idio...

MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)

Build and insert Res = G_ZEXT Op.

MachineInstrBuilder buildConcatVectors(const DstOp &Res, ArrayRef< Register > Ops)

Build and insert Res = G_CONCAT_VECTORS Op0, ...

MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_ Addr, Val, MMO.

MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects, bool isConvergent)

Build and insert a G_INTRINSIC instruction.

MDNode * getPCSections()

Get the current instruction's PC sections metadata.

MachineInstrBuilder buildVScale(const DstOp &Res, unsigned MinElts)

Build and insert Res = G_VSCALE MinElts.

MachineInstrBuilder buildSplatBuildVector(const DstOp &Res, const SrcOp &Src)

Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.

MachineInstrBuilder buildIndirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)

Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in me...

unsigned getBoolExtOp(bool IsVec, bool IsFP) const

MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_UMAX Addr, Val, MMO.

MachineInstrBuilder buildBuildVector(const DstOp &Res, ArrayRef< Register > Ops)

Build and insert Res = G_BUILD_VECTOR Op0, ...

MachineInstrBuilder buildConstDbgValue(const Constant &C, const MDNode *Variable, const MDNode *Expr)

Build and insert a DBG_VALUE instructions specifying that Variable is given by C (suitably modified b...

void recordInsertion(MachineInstr *InsertedInstr) const

MachineInstrBuilder buildBrCond(const SrcOp &Tst, MachineBasicBlock &Dest)

Build and insert G_BRCOND Tst, Dest.

MachineInstrBuilder buildMergeLikeInstr(const DstOp &Res, ArrayRef< Register > Ops)

Build and insert Res = G_MERGE_VALUES Op0, ... or Res = G_BUILD_VECTOR Op0, ... or Res = G_CONCAT_VEC...

MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)

Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.

MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)

Build and insert Res = G_LOAD Addr, MMO.

MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)

Build and insert Res = G_PTR_ADD Op0, Op1.

MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op)

Build and insert Res = G_ZEXT Op, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes...

MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res, ArrayRef< Register > Ops)

Build and insert Res = G_BUILD_VECTOR_TRUNC Op0, ...

virtual MachineInstrBuilder buildFConstant(const DstOp &Res, const ConstantFP &Val)

Build and insert Res = G_FCONSTANT Val.

MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)

Build and insert G_STORE Val, Addr, MMO.

MachineInstrBuilder buildInstr(unsigned Opcode)

Build and insert = Opcode .

MachineInstrBuilder buildPadVectorWithUndefElements(const DstOp &Res, const SrcOp &Op0)

Build and insert a, b, ..., x = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a, b, .....

void validateSelectOp(const LLT ResTy, const LLT TstTy, const LLT Op0Ty, const LLT Op1Ty)

MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)

Build and insert Res = G_FRAME_INDEX Idx.

MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable, const MDNode *Expr)

Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in Re...

const DebugLoc & getDL()

Getter for DebugLoc.

MachineInstrBuilder buildBuildVectorConstant(const DstOp &Res, ArrayRef< APInt > Ops)

Build and insert Res = G_BUILD_VECTOR Op0, ... where each OpN is built with G_CONSTANT.

MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_UMIN Addr, Val, MMO.

void validateBinaryOp(const LLT Res, const LLT Op0, const LLT Op1)

void validateShiftOp(const LLT Res, const LLT Op0, const LLT Op1)

MachineFunction & getMF()

Getter for the function we currently build.

MachineInstrBuilder buildDbgLabel(const MDNode *Label)

Build and insert a DBG_LABEL instructions specifying that Label is given.

MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI, Register IndexReg)

Build and insert G_BRJT TablePtr, JTI, IndexReg.

MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src, const SrcOp &Op, unsigned Index)

MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size, Align Alignment)

Build and insert Res = G_DYN_STACKALLOC Size, Align.

MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable, const MDNode *Expr)

Build and insert a DBG_VALUE instruction expressing the fact that the associated Variable lives in th...

MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res, const SrcOp &Op)

Build and insert Res = ExtOpc, Res = G_TRUNC Op, or Res = COPY Op depending on the differing sizes of...

MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_SUB Addr, Val, MMO.

MachineInstrBuilder buildMergeValues(const DstOp &Res, ArrayRef< Register > Ops)

Build and insert Res = G_MERGE_VALUES Op0, ...

MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)

Build and insert Res = G_TRUNC Op.

MachineInstrBuilder buildAtomicRMWFMax(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_FMAX Addr, Val, MMO.

MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_OR Addr, Val, MMO.

const MachineBasicBlock & getMBB() const

Getter for the basic block we currently build.

MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)

Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.

MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)

Build and insert Res = G_ANYEXT Op0.

MachineInstrBuilder buildAtomicCmpXchgWithSuccess(const DstOp &OldValRes, const DstOp &SuccessRes, const SrcOp &Addr, const SrcOp &CmpVal, const SrcOp &NewVal, MachineMemOperand &MMO)

Build and insert OldValRes, SuccessRes = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr,...

MachineInstrBuilder buildDeleteTrailingVectorElements(const DstOp &Res, const SrcOp &Op0)

Build and insert a, b, ..., x, y, z = G_UNMERGE_VALUES Op0 Res = G_BUILD_VECTOR a,...

MachineRegisterInfo * getMRI()

Getter for MRI.

MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_ADD Addr, Val, MMO.

MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op, std::optional< unsigned > Flags=std::nullopt)

Build and insert Res = G_FPTRUNC Op.

MachineInstrBuilder buildAtomicCmpXchg(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &CmpVal, const SrcOp &NewVal, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, MMO.

MachineInstrBuilder buildShuffleVector(const DstOp &Res, const SrcOp &Src1, const SrcOp &Src2, ArrayRef< int > Mask)

Build and insert Res = G_SHUFFLE_VECTOR Src1, Src2, Mask.

void validateTruncExt(const LLT Dst, const LLT Src, bool IsExtend)

MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)

Build but don't insert = Opcode .

MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)

Build and insert Res = G_PTRMASK Op0, Op1.

MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)

Build and insert Res = COPY Op.

void validateUnaryOp(const LLT Res, const LLT Op0)

MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA)

Build and insert Res = G_BLOCK_ADDR BA.

MDNode * getMMRAMetadata()

Get the current instruction's MMRA metadata.

MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_MAX Addr, Val, MMO.

MachineInstrBuilder buildPrefetch(const SrcOp &Addr, unsigned RW, unsigned Locality, unsigned CacheType, MachineMemOperand &MMO)

Build and insert G_PREFETCH Addr, RW, Locality, CacheType.

MachineInstrBuilder buildExtractSubvector(const DstOp &Res, const SrcOp &Src, unsigned Index)

Build and insert Res = G_EXTRACT_SUBVECTOR Src, Idx0.

MachineInstrBuilder buildBrIndirect(Register Tgt)

Build and insert G_BRINDIRECT Tgt.

MachineInstrBuilder buildSplatVector(const DstOp &Res, const SrcOp &Val)

Build and insert Res = G_SPLAT_VECTOR Val.

MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)

Build and insert Res = Addr, MMO.

void setMF(MachineFunction &MF)

MachineInstrBuilder buildStepVector(const DstOp &Res, unsigned Step)

Build and insert Res = G_STEP_VECTOR Step.

MachineInstrBuilder buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_FSUB Addr, Val, MMO.

MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr, Register Val, MachineMemOperand &MMO)

Build and insert OldValRes = G_ATOMICRMW_XCHG Addr, Val, MMO.

MachineInstrBuilder buildMaskLowPtrBits(const DstOp &Res, const SrcOp &Op0, uint32_t NumBits)

Build and insert Res = G_PTRMASK Op0, G_CONSTANT (1 << NumBits) - 1.

virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)

Build and insert Res = G_CONSTANT Val.

MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)

Build and insert a Res = G_FCMP PredOp0, Op1.

MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp)

Build and insert Res = G_SEXT_INREG Op, ImmOp.

MachineInstrBuilder buildConstantPtrAuth(const DstOp &Res, const ConstantPtrAuth *CPA, Register Addr, Register AddrDisc)

Build and insert G_PTRAUTH_GLOBAL_VALUE.

Get the register for the operand index.

const MachineInstrBuilder & addCImm(const ConstantInt *Val) const

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & addBlockAddress(const BlockAddress *BA, int64_t Offset=0, unsigned TargetFlags=0) const

const MachineInstrBuilder & addFPImm(const ConstantFP *Val) const

const MachineInstrBuilder & addJumpTableIndex(unsigned Idx, unsigned TargetFlags=0) const

const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const

const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const

Add a virtual register use operand.

const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const

Add a virtual register definition operand.

A description of a memory reference used in the backend.

bool isAtomic() const

Returns true if this operation has an atomic ordering requirement of unordered or higher,...

Flags

Flags values. These may be or'd together.

@ MOLoad

The memory access reads data.

@ MOStore

The memory access writes data.

Create and return a new generic virtual register with low-level type Ty.

unsigned getAddressSpace() const

Return the address space of the Pointer type.

Wrapper class representing virtual and physical registers.

void reserve(size_type N)

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

LLT getLLTTy(const MachineRegisterInfo &MRI) const

void addSrcToMIB(MachineInstrBuilder &MIB) const

@ ZeroOrOneBooleanContent

@ UndefinedBooleanContent

@ ZeroOrNegativeOneBooleanContent

virtual const TargetInstrInfo * getInstrInfo() const

virtual const TargetLowering * getTargetLowering() const

LLVM Value Representation.

static constexpr bool isKnownLT(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)

static constexpr bool isKnownGT(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

@ C

The default llvm calling convention, compatible with C.

AttributeList getAttributes(LLVMContext &C, ID id)

Return the attributes for an intrinsic.

This is an optimization pass for GlobalISel generic memory operations.

bool all_of(R &&range, UnaryPredicate P)

Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)

DWARFExpression::Operation Op

APFloat getAPFloatFromSize(double Val, unsigned Size)

Returns an APFloat from Val converted to the appropriate size.

A collection of metadata nodes that might be associated with a memory access used by the alias-analys...

static unsigned getSizeInBits(const fltSemantics &Sem)

Returns the size of the floating point number (in bits) in the given semantics.

This struct is a compact representation of a valid (non-zero power of two) alignment.

uint64_t value() const

This is a hole in the type system and should not be abused.

MachineFunction * MF

MachineFunction under construction.

MDNode * MMRA

MMRA Metadata to be set on any instruction we create.

DebugLoc DL

Debug location to be set to any instruction we create.

const TargetInstrInfo * TII

Information used to access the description of the opcodes.

MDNode * PCSections

PC sections metadata to be set to any instruction we create.

MachineBasicBlock::iterator II

MachineRegisterInfo * MRI

Information used to verify types are consistent and to create virtual registers.

GISelChangeObserver * Observer

This class contains a discriminated union of information about pointers in memory operands,...