MachinePipeliner.h Source File (original) (raw)

40#ifndef LLVM_CODEGEN_MACHINEPIPELINER_H

41#define LLVM_CODEGEN_MACHINEPIPELINER_H

56#include

58namespace llvm {

70public:

81#ifndef NDEBUG

83#endif

97 static char ID;

102

104

106

107private:

111 bool swingModuloScheduler(MachineLoop &L);

112 void setPragmaPipelineOptions(MachineLoop &L);

114 bool useSwingModuloScheduler();

115 bool useWindowScheduler(bool Changed);

116};

117

118

120 SUnit *Dst = nullptr;

122 unsigned Distance = 0;

123 bool IsValidationOnly = false;

124

125public:

126

127

128

129

131 bool IsValidationOnly)

132 : Dst(PredOrSucc), Pred(Dep), Distance(0u),

133 IsValidationOnly(IsValidationOnly) {

135

136 if (IsSucc) {

138 Pred.setSUnit(Src);

139 }

140

141

142 if (Pred.getKind() == SDep::Anti && Src->getInstr()->isPHI()) {

143 Distance = 1;

144 std::swap(Src, Dst);

145 auto Reg = Pred.getReg();

146 Pred = SDep(Src, SDep::Kind::Data, Reg);

147 }

148 }

149

150

152

153

155

156

157 unsigned getLatency() const { return Pred.getLatency(); }

158

159

161

162

164

165

167

168

170

171

173

174

176

177

178

180

181

182 bool isBarrier() const { return Pred.isBarrier(); }

183

184

185 bool isArtificial() const { return Pred.isArtificial(); }

186

187

189

190

191

192

194

195

196

198};

199

200

201

202

203

204

208

210

214 return nullptr;

215 return &Ite->second;

216 }

217

218

219

220

221

223

226};

227

228

229

230

231

232

235

236 struct SwingSchedulerDDGEdges {

237 EdgesType Preds;

238 EdgesType Succs;

239 };

240

241 void initEdges(SUnit *SU);

242

245

246 std::vector EdgesVec;

247 SwingSchedulerDDGEdges EntrySUEdges;

248 SwingSchedulerDDGEdges ExitSUEdges;

249

250

251

253

254

255

257

258 SwingSchedulerDDGEdges &getEdges(const SUnit *SU);

259 const SwingSchedulerDDGEdges &getEdges(const SUnit *SU) const;

260

261public:

264

266

268

270};

271

272

273

276

277 std::unique_ptr DDG;

278

279

280 unsigned MII = 0;

281

282 unsigned MAX_II = 0;

283

284 bool Scheduled = false;

288 unsigned II_setByPragma = 0;

290

291

292

294

295 struct NodeInfo {

296 int ASAP = 0;

297 int ALAP = 0;

298 int ZeroLatencyDepth = 0;

299 int ZeroLatencyHeight = 0;

300

301 NodeInfo() = default;

302 };

303

304 std::vector ScheduleInfo;

305

306 enum OrderKind { BottomUp = 0, TopDown = 1 };

307

309

314

315

317

318

319

321

322

323 std::vector<std::unique_ptr> Mutations;

324

325

327

328

329

331

332

333 class Circuits {

334 std::vector &SUnits;

339

340 std::vector *Node2Idx;

341 unsigned NumPaths = 0u;

342 static unsigned MaxPaths;

343

344 public:

346 : SUnits(SUs), Blocked(SUs.size()), B(SUs.size()), AdjK(SUs.size()) {

347 Node2Idx = new std::vector(SUs.size());

348 unsigned Idx = 0;

349 for (const auto &NodeNum : Topo)

350 Node2Idx->at(NodeNum) = Idx++;

351 }

352 Circuits &operator=(const Circuits &other) = delete;

353 Circuits(const Circuits &other) = delete;

354 ~Circuits() { delete Node2Idx; }

355

356

357 void reset() {

358 Stack.clear();

361 NumPaths = 0;

362 }

363

365 bool circuit(int V, int S, NodeSetType &NodeSets,

367 void unblock(int U);

368 };

369

372 };

373

374public:

379 RegClassInfo(rci), II_setByPragma(II), LoopPipelinerInfo(PLI),

381 P.MF->getSubtarget().getSMSMutations(Mutations);

383 Mutations.push_back(std::make_unique());

384 BAA.enableCrossIterationMode();

385 }

386

389

390

392

393

395

396

398

399

400

402

403

405

406

407

409 return ScheduleInfo[Node->NodeNum].ZeroLatencyDepth;

410 }

411

412

414

415

416

418 return ScheduleInfo[Node->NodeNum].ZeroLatencyHeight;

419 }

420

422

424

426

427

428

431 InstrChanges.find(SU);

432 if (It != InstrChanges.end())

433 return It->second.first;

435 }

436

438 Mutations.push_back(std::move(Mutation));

439 }

440

442

444

447

448private:

450 void updatePhiDependences();

451 void changeDependences();

452 unsigned calculateResMII();

453 unsigned calculateRecMII(NodeSetType &RecNodeSets);

454 void findCircuits(NodeSetType &NodeSets);

455 void fuseRecs(NodeSetType &NodeSets);

456 void removeDuplicateNodes(NodeSetType &NodeSets);

457 void computeNodeFunctions(NodeSetType &NodeSets);

458 void registerPressureFilter(NodeSetType &NodeSets);

459 void colocateNodeSets(NodeSetType &NodeSets);

460 void checkNodeSets(NodeSetType &NodeSets);

461 void groupRemainingNodes(NodeSetType &NodeSets);

462 void addConnectedNodes(SUnit *SU, NodeSet &NewSet,

464 void computeNodeOrder(NodeSetType &NodeSets);

465 void checkValidNodeOrder(const NodeSetType &Circuits) const;

466 bool schedulePipeline(SMSchedule &Schedule);

469 bool canUseLastOffsetValue(MachineInstr *MI, unsigned &BasePos,

470 unsigned &OffsetPos, Register &NewBase,

471 int64_t &NewOffset);

472 void postProcessDAG();

473

474 void setMII(unsigned ResMII, unsigned RecMII);

475

476 void setMAX_II();

477};

478

479

480

483 bool HasRecurrence = false;

484 unsigned RecMII = 0;

485 int MaxMOV = 0;

486 unsigned MaxDepth = 0;

487 unsigned Colocate = 0;

488 SUnit *ExceedPressure = nullptr;

489 unsigned Latency = 0;

490

491public:

493

496 : Nodes(S, E), HasRecurrence(true) {

497

498

499

500

501

502

503

504

505

506

507

508

509

510

513 for (auto *Node : Nodes)

514 SUnitToDistance[Node] = 0;

515

516 for (unsigned I = 1, E = Nodes.size(); I <= E; ++I) {

517 SUnit *U = Nodes[I - 1];

518 SUnit *V = Nodes[I % Nodes.size()];

519 for (const SwingSchedulerDDGEdge &Succ : DDG->getOutEdges(U)) {

520 SUnit *SuccSUnit = Succ.getDst();

521 if (V != SuccSUnit)

522 continue;

523 unsigned &DU = SUnitToDistance[U];

524 unsigned &DV = SUnitToDistance[V];

525 if (DU + Succ.getLatency() > DV)

526 DV = DU + Succ.getLatency();

527 }

528 }

529

530 SUnit *FirstNode = Nodes[0];

531 SUnit *LastNode = Nodes[Nodes.size() - 1];

532

533 for (auto &PI : DDG->getInEdges(LastNode)) {

534

535

536

537

538 if (PI.getSrc() != FirstNode || !PI.isOrderDep() ||

539 !DAG->isLoopCarriedDep(PI))

540 continue;

541 unsigned &First = SUnitToDistance[FirstNode];

542 unsigned Last = SUnitToDistance[LastNode];

543 First = std::max(First, Last + 1);

544 }

545

546

548 }

549

551

553

554 template bool remove_if(UnaryPredicate P) {

555 return Nodes.remove_if(P);

556 }

557

558 unsigned count(SUnit *SU) const { return Nodes.count(SU); }

559

561

562 unsigned size() const { return Nodes.size(); }

563

564 bool empty() const { return Nodes.empty(); }

565

567

568 void setRecMII(unsigned mii) { RecMII = mii; };

569

571

573

575

577

579

580

582 for (SUnit *SU : *this) {

583 MaxMOV = std::max(MaxMOV, SSD->getMOV(SU));

584 MaxDepth = std::max(MaxDepth, SSD->getDepth(SU));

585 }

586 }

587

589

591

593 Nodes.clear();

594 RecMII = 0;

595 HasRecurrence = false;

596 MaxMOV = 0;

597 MaxDepth = 0;

598 Colocate = 0;

599 ExceedPressure = nullptr;

600 }

601

603

604

605

606

607

609 if (RecMII == RHS.RecMII) {

610 if (Colocate != 0 && RHS.Colocate != 0 && Colocate != RHS.Colocate)

611 return Colocate < RHS.Colocate;

612 if (MaxMOV == RHS.MaxMOV)

613 return MaxDepth > RHS.MaxDepth;

614 return MaxMOV < RHS.MaxMOV;

615 }

616 return RecMII > RHS.RecMII;

617 }

618

620 return RecMII == RHS.RecMII && MaxMOV == RHS.MaxMOV &&

621 MaxDepth == RHS.MaxDepth;

622 }

623

625

629

630#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

632#endif

633};

634

635

636

638

640private:

646 const bool UseDFA;

647

649

650

652

653

654

656

657

658

659

661 int InitiationInterval = 0;

662

663 int IssueWidth;

664

665 int calculateResMIIDFA() const;

666

667 bool isOverbooked() const;

668

670

672

673

674

675

676 int positiveModulo(int Dividend, int Divisor) const {

678 int R = Dividend % Divisor;

679 if (R < 0)

680 R += Divisor;

681 return R;

682 }

683

684#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

686#endif

687

688public:

690 : STI(ST), SM(ST->getSchedModel()), ST(ST), TII(ST->getInstrInfo()),

691 DAG(DAG), UseDFA(ST->useDFAforSMS()),

692 ProcResourceMasks(SM.getNumProcResourceKinds(), 0),

693 IssueWidth(SM.IssueWidth) {

695 if (IssueWidth <= 0)

696

697 IssueWidth = 100;

700 }

701

702 void initProcResourceVectors(const MCSchedModel &SM,

704

705

706

707 bool canReserveResources(SUnit &SU, int Cycle);

708

709

710

711 void reserveResources(SUnit &SU, int Cycle);

712

713 int calculateResMII() const;

714

715

716 void init(int II);

717};

718

719

720

721

722

723

724

725

726

728private:

729

731

732

733 std::map<SUnit *, int> InstrToCycle;

734

735

736

737 int FirstCycle = 0;

738

739

740 int LastCycle = 0;

741

742

743 int InitiationInterval = 0;

744

745

747

748

750

752

753public:

755 : ST(mf->getSubtarget()), MRI(mf->getRegInfo()),

756 ProcItinResources(&ST, DAG) {}

757

759 ScheduledInstrs.clear();

760 InstrToCycle.clear();

761 FirstCycle = 0;

762 LastCycle = 0;

763 InitiationInterval = 0;

764 }

765

766

768 InitiationInterval = ii;

769 ProcItinResources.init(ii);

770 }

771

772

774

775

776

778

779

780 int getFinalCycle() const { return FirstCycle + InitiationInterval - 1; }

781

782

783

786

787

788

791

792 void computeStart(SUnit *SU, int *MaxEarlyStart, int *MinLateStart, int II,

794 bool insert(SUnit *SU, int StartCycle, int EndCycle, int II);

795

796

800

801

805

806

807

809 std::map<SUnit *, int>::const_iterator it = InstrToCycle.find(SU);

810 if (it == InstrToCycle.end())

811 return -1;

812 return (it->second - FirstCycle) / InitiationInterval;

813 }

814

815

816

818 std::map<SUnit *, int>::const_iterator it = InstrToCycle.find(SU);

819 assert(it != InstrToCycle.end() && "Instruction hasn't been scheduled.");

820 return (it->second - FirstCycle) % InitiationInterval;

821 }

822

823

825 return (LastCycle - FirstCycle) / InitiationInterval;

826 }

827

828

830 return ScheduledInstrs[cycle];

831 }

832

836

837 std::deque<SUnit *>

839 const std::deque<SUnit *> &Instrs) const;

840

841 bool

847 std::deque<SUnit *> &Insts) const;

851

852 bool onlyHasLoopCarriedOutputOrOrderPreds(SUnit *SU,

855 void dump() const;

856};

857

858}

859

860#endif

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)

static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")

static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

#define LLVM_DUMP_METHOD

Mark debug helper function definitions like dump() that should not be stripped from debug builds.

Promote Memory to Register

uint64_t IntrinsicInst * II

This file implements a set that has insertion order iteration characteristics.

Represent the analysis usage information of a pass.

This class is a wrapper over an AAResults, and it is intended to be used only when there are no IR ch...

Itinerary data supplied by a subtarget to be used by a target.

Generic base class for all target subtargets.

DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...

MachineFunctionPass(char &ID)

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

The main class in the implementation of the target independent software pipeliner pass.

Definition MachinePipeliner.h:69

bool runOnMachineFunction(MachineFunction &MF) override

The "main" function for implementing Swing Modulo Scheduling.

const TargetInstrInfo * TII

Definition MachinePipeliner.h:76

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

MachineFunction * MF

Definition MachinePipeliner.h:71

LoopInfo LI

Definition MachinePipeliner.h:95

const MachineDominatorTree * MDT

Definition MachinePipeliner.h:74

const MachineLoopInfo * MLI

Definition MachinePipeliner.h:73

static int NumTries

Definition MachinePipeliner.h:82

bool disabledByPragma

Definition MachinePipeliner.h:78

unsigned II_setByPragma

Definition MachinePipeliner.h:79

MachinePipeliner()

Definition MachinePipeliner.h:99

MachineOptimizationRemarkEmitter * ORE

Definition MachinePipeliner.h:72

RegisterClassInfo RegClassInfo

Definition MachinePipeliner.h:77

const InstrItineraryData * InstrItins

Definition MachinePipeliner.h:75

static char ID

Definition MachinePipeliner.h:97

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

A NodeSet contains a set of SUnit DAG nodes with additional information that assigns a priority to th...

Definition MachinePipeliner.h:481

SUnit * getNode(unsigned i) const

Definition MachinePipeliner.h:566

SetVector< SUnit * >::const_iterator iterator

Definition MachinePipeliner.h:492

bool isExceedSU(SUnit *SU)

Definition MachinePipeliner.h:574

void insert(iterator S, iterator E)

Definition MachinePipeliner.h:552

iterator begin()

Definition MachinePipeliner.h:626

void setRecMII(unsigned mii)

Definition MachinePipeliner.h:568

void computeNodeSetInfo(SwingSchedulerDAG *SSD)

Summarize node functions for the entire node set.

Definition MachinePipeliner.h:581

unsigned getMaxDepth()

Definition MachinePipeliner.h:590

unsigned count(SUnit *SU) const

Definition MachinePipeliner.h:558

void setColocate(unsigned c)

Definition MachinePipeliner.h:570

unsigned getLatency()

Definition MachinePipeliner.h:588

iterator end()

Definition MachinePipeliner.h:627

NodeSet(iterator S, iterator E, const SwingSchedulerDAG *DAG)

Definition MachinePipeliner.h:495

int getRecMII()

Definition MachinePipeliner.h:578

bool operator>(const NodeSet &RHS) const

Sort the node sets by importance.

Definition MachinePipeliner.h:608

bool hasRecurrence()

Definition MachinePipeliner.h:560

int compareRecMII(NodeSet &RHS)

Definition MachinePipeliner.h:576

unsigned size() const

Definition MachinePipeliner.h:562

bool operator!=(const NodeSet &RHS) const

Definition MachinePipeliner.h:624

bool insert(SUnit *SU)

Definition MachinePipeliner.h:550

bool operator==(const NodeSet &RHS) const

Definition MachinePipeliner.h:619

bool remove_if(UnaryPredicate P)

Definition MachinePipeliner.h:554

bool empty() const

Definition MachinePipeliner.h:564

void clear()

Definition MachinePipeliner.h:592

void setExceedPressure(SUnit *SU)

Definition MachinePipeliner.h:572

static LLVM_ABI PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

Wrapper class representing virtual and physical registers.

Definition MachinePipeliner.h:639

void initProcResourceVectors(const MCSchedModel &SM, SmallVectorImpl< uint64_t > &Masks)

ResourceManager(const TargetSubtargetInfo *ST, ScheduleDAGInstrs *DAG)

Definition MachinePipeliner.h:689

@ Output

A register output-dependence (aka WAW).

@ Order

Any other ordering dependency.

@ Anti

A register anti-dependence (aka WAR).

This class represents the scheduled code.

Definition MachinePipeliner.h:727

void setInitiationInterval(int ii)

Set the initiation interval for this schedule.

Definition MachinePipeliner.h:767

unsigned getMaxStageCount()

Return the maximum stage count needed for this schedule.

Definition MachinePipeliner.h:824

void reset()

Definition MachinePipeliner.h:758

int stageScheduled(SUnit *SU) const

Return the stage for a scheduled instruction.

Definition MachinePipeliner.h:808

bool isScheduledAtStage(SUnit *SU, unsigned StageNum)

Return true if the instruction is scheduled at the specified stage.

Definition MachinePipeliner.h:802

int getInitiationInterval() const

Return the initiation interval for this schedule.

Definition MachinePipeliner.h:773

std::deque< SUnit * > & getInstructions(int cycle)

Return the instructions that are scheduled at the specified cycle.

Definition MachinePipeliner.h:829

int getFirstCycle() const

Return the first cycle in the completed schedule.

Definition MachinePipeliner.h:777

DenseMap< int, std::deque< SUnit * > >::const_iterator const_sched_iterator

Definition MachinePipeliner.h:798

DenseMap< int, std::deque< SUnit * > >::iterator sched_iterator

Iterators for the cycle to instruction map.

Definition MachinePipeliner.h:797

unsigned cycleScheduled(SUnit *SU) const

Return the cycle for a scheduled instruction.

Definition MachinePipeliner.h:817

SMSchedule(MachineFunction *mf, SwingSchedulerDAG *DAG)

Definition MachinePipeliner.h:754

int getFinalCycle() const

Return the last cycle in the finalized schedule.

Definition MachinePipeliner.h:780

Scheduling unit. This is a node in the scheduling DAG.

A ScheduleDAG for scheduling lists of MachineInstr.

ScheduleDAGInstrs(MachineFunction &mf, const MachineLoopInfo *mli, bool RemoveKillFlags=false)

const MachineLoopInfo * MLI

Mutate the DAG as a postpass after normal DAG building.

This class can compute a topological ordering for SUnits and provides methods for dynamically updatin...

std::vector< SUnit > SUnits

The scheduling units.

MachineFunction & MF

Machine function.

ScheduleDAG & operator=(const ScheduleDAG &)=delete

SUnit ExitSU

Special node for the region exit.

A vector that has set insertion semantics.

size_type size() const

Determine the number of elements in the SetVector.

const value_type & front() const

Return the first element of the SetVector.

typename vector_type::const_iterator const_iterator

SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.

A SetVector that performs no allocations if smaller than a certain size.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

This class builds the dependence graph for the instructions in a loop, and attempts to schedule the i...

Definition MachinePipeliner.h:274

unsigned getDepth(SUnit *Node)

The depth, in the dependence graph, for a node.

Definition MachinePipeliner.h:404

int getASAP(SUnit *Node)

Return the earliest time an instruction may be scheduled.

Definition MachinePipeliner.h:394

void applyInstrChange(MachineInstr *MI, SMSchedule &Schedule)

Apply changes to the instruction if needed.

const SwingSchedulerDDG * getDDG() const

Definition MachinePipeliner.h:443

void finishBlock() override

Clean up after the software pipeliner runs.

void fixupRegisterOverlaps(std::deque< SUnit * > &Instrs)

Attempt to fix the degenerate cases when the instruction serialization causes the register lifetimes ...

bool hasNewSchedule()

Return true if the loop kernel has been scheduled.

Definition MachinePipeliner.h:391

void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)

Definition MachinePipeliner.h:437

int getZeroLatencyDepth(SUnit *Node)

The maximum unweighted length of a path from an arbitrary node to the given node in which each edge h...

Definition MachinePipeliner.h:408

bool isLoopCarriedDep(const SwingSchedulerDDGEdge &Edge) const

Return true for an order or output dependence that is loop carried potentially.

void schedule() override

We override the schedule function in ScheduleDAGInstrs to implement the scheduling part of the Swing ...

bool mayOverlapInLaterIter(const MachineInstr *BaseMI, const MachineInstr *OtherMI) const

Return false if there is no overlap between the region accessed by BaseMI in an iteration and the reg...

int getMOV(SUnit *Node)

The mobility function, which the number of slots in which an instruction may be scheduled.

Definition MachinePipeliner.h:401

SwingSchedulerDAG(MachinePipeliner &P, MachineLoop &L, LiveIntervals &lis, const RegisterClassInfo &rci, unsigned II, TargetInstrInfo::PipelinerLoopInfo *PLI, AliasAnalysis *AA)

Definition MachinePipeliner.h:375

int getZeroLatencyHeight(SUnit *Node)

The maximum unweighted length of a path from the given node to an arbitrary node in which each edge h...

Definition MachinePipeliner.h:417

Return the new base register that was stored away for the changed instruction.

Definition MachinePipeliner.h:429

static bool classof(const ScheduleDAGInstrs *DAG)

Definition MachinePipeliner.h:441

unsigned getHeight(SUnit *Node)

The height, in the dependence graph, for a node.

Definition MachinePipeliner.h:413

int getALAP(SUnit *Node)

Return the latest time an instruction my be scheduled.

Definition MachinePipeliner.h:397

Represents a dependence between two instruction.

Definition MachinePipeliner.h:119

SUnit * getDst() const

Returns the SUnit to which the edge points (destination node).

Definition MachinePipeliner.h:154

Returns the register associated with the edge.

Definition MachinePipeliner.h:169

void setDistance(unsigned D)

Sets the distance value for the edge.

Definition MachinePipeliner.h:166

bool isBarrier() const

Returns true if the edge represents unknown scheduling barrier.

Definition MachinePipeliner.h:182

void setLatency(unsigned Latency)

Sets the latency for the edge.

Definition MachinePipeliner.h:160

SwingSchedulerDDGEdge(SUnit *PredOrSucc, const SDep &Dep, bool IsSucc, bool IsValidationOnly)

Creates an edge corresponding to an edge represented by PredOrSucc and Dep in the original DAG.

Definition MachinePipeliner.h:130

bool isAntiDep() const

Returns true if the edge represents anti dependence.

Definition MachinePipeliner.h:172

bool isAssignedRegDep() const

Tests if this is a Data dependence that is associated with a register.

Definition MachinePipeliner.h:188

bool isArtificial() const

Returns true if the edge represents an artificial dependence.

Definition MachinePipeliner.h:185

bool ignoreDependence(bool IgnoreAnti) const

Returns true for DDG nodes that we ignore when computing the cost functions.

bool isOrderDep() const

Returns true if the edge represents a dependence that is not data, anti or output dependence.

Definition MachinePipeliner.h:179

unsigned getLatency() const

Returns the latency value for the edge.

Definition MachinePipeliner.h:157

SUnit * getSrc() const

Returns the SUnit from which the edge comes (source node).

Definition MachinePipeliner.h:151

bool isValidationOnly() const

Returns true if this edge is intended to be used only for validating the schedule.

Definition MachinePipeliner.h:197

unsigned getDistance() const

Returns the distance value for the edge.

Definition MachinePipeliner.h:163

bool isOutputDep() const

Returns true if the edge represents output dependence.

Definition MachinePipeliner.h:175

This class provides APIs to retrieve edges from/to an SUnit node, with a particular focus on loop-car...

Definition MachinePipeliner.h:233

SwingSchedulerDDG(std::vector< SUnit > &SUnits, SUnit *EntrySU, SUnit *ExitSU, const LoopCarriedEdges &LCE)

const EdgesType & getInEdges(const SUnit *SU) const

bool isValidSchedule(const SMSchedule &Schedule) const

Check if Schedule doesn't violate the validation-only dependencies.

const EdgesType & getOutEdges(const SUnit *SU) const

Object returned by analyzeLoopForPipelining.

TargetInstrInfo - Interface to description of machine instruction set.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

TargetSubtargetInfo - Generic base class for all target subtargets.

This class implements an extremely fast bulk output stream that can only output to a stream.

This is an optimization pass for GlobalISel generic memory operations.

void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)

Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr, unsigned DynamicVGPRBlockSize=0)

bool operator==(const AddressRangeValuePair &LHS, const AddressRangeValuePair &RHS)

static int64_t computeDelta(SectionEntry *A, SectionEntry *B)

LLVM_ABI void initializeMachinePipelinerPass(PassRegistry &)

LLVM_ATTRIBUTE_VISIBILITY_DEFAULT AnalysisKey InnerAnalysisManagerProxy< AnalysisManagerT, IRUnitT, ExtraArgTs... >::Key

cl::opt< bool > SwpEnableCopyToPhi

cl::opt< int > SwpForceIssueWidth

A command line argument to force pipeliner to use specified issue width.

static const int DefaultProcResSize

Definition MachinePipeliner.h:637

AAResults AliasAnalysis

Temporary typedef for legacy code that uses a generic AliasAnalysis pointer or reference.

void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)

Implement std::swap in terms of BitVector swap.

Represents loop-carried dependencies.

Definition MachinePipeliner.h:205

SmallSetVector< SUnit *, 8 > OrderDep

Definition MachinePipeliner.h:206

const OrderDep * getOrderDepOrNull(SUnit *Key) const

Definition MachinePipeliner.h:211

OrderDepsType OrderDeps

Definition MachinePipeliner.h:209

void modifySUnits(std::vector< SUnit > &SUnits, const TargetInstrInfo *TII)

Adds some edges to the original DAG that correspond to loop-carried dependencies.

void dump(SUnit *SU, const TargetRegisterInfo *TRI, const MachineRegisterInfo *MRI) const

DenseMap< SUnit *, OrderDep > OrderDepsType

Definition MachinePipeliner.h:207

Summarize the scheduling resources required for an instruction of a particular scheduling class.

Machine model for scheduling, bundling, and heuristics.

Cache the target analysis information about the loop.

Definition MachinePipeliner.h:86

MachineBasicBlock * FBB

Definition MachinePipeliner.h:88

MachineInstr * LoopInductionVar

Definition MachinePipeliner.h:90

SmallVector< MachineOperand, 4 > BrCond

Definition MachinePipeliner.h:89

MachineBasicBlock * TBB

Definition MachinePipeliner.h:87

MachineInstr * LoopCompare

Definition MachinePipeliner.h:91

std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > LoopPipelinerInfo

Definition MachinePipeliner.h:92