LLVM: llvm::MCSchedModel Struct Reference (original) (raw)

Machine model for scheduling, bundling, and heuristics. More...

#include "[llvm/MC/MCSchedule.h](MCSchedule%5F8h%5Fsource.html)"

Machine model for scheduling, bundling, and heuristics.

The machine model directly provides basic information about the microarchitecture to the scheduler in the form of properties. It also optionally refers to scheduler resource tables and itinerary tables. Scheduler resource tables model the latency and cost for each instruction type. Itinerary tables are an independent mechanism that provides a detailed reservation table describing each cycle of instruction execution. Subtargets may define any or all of the above categories of data depending on the type of CPU and selected scheduler.

The machine independent properties defined here are used by the scheduler as an abstract machine model. A real micro-architecture has a number of buffers, queues, and stages. Declaring that a given machine-independent abstract property corresponds to a specific physical property across all subtargets can't be done. Nonetheless, the abstract model is useful. Futhermore, subtargets typically extend this model with processor specific resources to model any hardware features that can be exploited by scheduling heuristics and aren't sufficiently represented in the abstract.

The abstract pipeline is built around the notion of an "issue point". This is merely a reference point for counting machine cycles. The physical machine will have pipeline stages that delay execution. The scheduler does not model those delays because they are irrelevant as long as they are consistent. Inaccuracies arise when instructions have different execution delays relative to each other, in addition to their intrinsic latency. Those special cases can be handled by TableGen constructs such as, ReadAdvance, which reduces latency when reading data, and ReleaseAtCycles, which consumes a processor resource when writing data for a number of abstract cycles.

TODO: One tool currently missing is the ability to add a delay to ReleaseAtCycles. That would be easy to add and would likely cover all cases currently handled by the legacy itinerary tables.

A note on out-of-order execution and, more generally, instruction buffers. Part of the CPU pipeline is always in-order. The issue point, which is the point of reference for counting cycles, only makes sense as an in-order part of the pipeline. Other parts of the pipeline are sometimes falling behind and sometimes catching up. It's only interesting to model those other, decoupled parts of the pipeline if they may be predictably resource constrained in a way that the scheduler can exploit.

The LLVM machine model distinguishes between in-order constraints and out-of-order constraints so that the target's scheduling strategy can apply appropriate heuristics. For a well-balanced CPU pipeline, out-of-order resources would not typically be treated as a hard scheduling constraint. For example, in the GenericScheduler, a delay caused by limited out-of-order resources is not directly reflected in the number of cycles that the scheduler sees between issuing an instruction and its dependent instructions. In other words, out-of-order resources don't directly increase the latency between pairs of instructions. However, they can still be used to detect potential bottlenecks across a sequence of instructions and bias the scheduling heuristics appropriately.

Definition at line 256 of file MCSchedule.h.

◆ computeInstrLatency() [1/4]

◆ computeInstrLatency() [2/4]

Definition at line 415 of file MCSchedule.h.

References computeInstrLatency(), llvm::StringRef::empty(), llvm::MCInstrInfo::get(), llvm::MCSubtargetInfo::getCPU(), llvm::MCSubtargetInfo::getInstrItineraryForCPU(), llvm::InstrItineraryData::getOperandCycle(), llvm::MCInstrDesc::getSchedClass(), getSchedClassDesc(), hasInstrSchedModel(), Idx, llvm::MCSchedClassDesc::isValid(), and llvm::Latency.

◆ computeInstrLatency() [3/4]

◆ computeInstrLatency() [4/4]

◆ getExtraProcessorInfo()

◆ getForwardingDelayCycles()

Returns the maximum forwarding delay for register reads dependent on writes of scheduling class WriteResourceIdx.

Definition at line 163 of file MCSchedule.cpp.

◆ getNumProcResourceKinds()

◆ getProcessorID()

◆ getProcResource()

Definition at line 356 of file MCSchedule.h.

References assert(), hasInstrSchedModel(), NumProcResourceKinds, and ProcResourceTable.

Referenced by llvm::ResourceManager::calculateResMII(), llvm::mca::computeBlockRThroughput(), llvm::TargetSchedModel::computeOutputLatency(), llvm::mca::computeProcResourceMasks(), llvm::mca::InstructionTables::execute(), llvm::TargetSchedModel::getProcResource(), getReciprocalThroughput(), llvm::TargetSchedModel::getResourceBufferSize(), llvm::TargetSchedModel::getResourceName(), llvm::TargetSchedModel::init(), llvm::mca::initializeUsedResources(), llvm::ResourceManager::initProcResourceVectors(), llvm::mca::LSUnitBase::LSUnitBase(), and llvm::mca::ResourceManager::ResourceManager().

◆ getReciprocalThroughput() [1/3]

Definition at line 119 of file MCSchedule.cpp.

References llvm::MCInstrInfo::get(), llvm::MCInst::getOpcode(), getProcessorID(), getReciprocalThroughput(), llvm::MCInstrDesc::getSchedClass(), getSchedClassDesc(), IssueWidth, llvm::MCSchedClassDesc::isValid(), llvm::MCSchedClassDesc::isVariant(), llvm_unreachable, and llvm::MCSubtargetInfo::resolveVariantSchedClass().

◆ getReciprocalThroughput() [2/3]

◆ getReciprocalThroughput() [3/3]

◆ getSchedClassDesc()

Definition at line 363 of file MCSchedule.h.

References assert(), hasInstrSchedModel(), NumSchedClasses, and SchedClassTable.

Referenced by llvm::mca::RegisterFile::addRegisterRead(), llvm::mca::RegisterFile::checkRAWHazards(), llvm::mca::RegisterFile::collectWrites(), computeInstrLatency(), llvm::TargetSchedModel::computeReciprocalThroughput(), llvm::mca::InstrBuilder::createInstruction(), getReciprocalThroughput(), and llvm::TargetSchedModel::resolveSchedClass().

◆ hasExtraProcessorInfo()

◆ hasInstrSchedModel()

◆ isComplete()

◆ isOutOfOrder()

◆ InstrItineraryData

◆ CompleteModel

bool llvm::MCSchedModel::CompleteModel

◆ Default

Initial value:

false,

true,

false,

0,

nullptr,

nullptr,

0,

0,

nullptr,

nullptr}

static const unsigned DefaultLoopMicroOpBufferSize

static const unsigned DefaultHighLatency

static const unsigned DefaultLoadLatency

static const unsigned DefaultMicroOpBufferSize

static const unsigned DefaultMispredictPenalty

static const unsigned DefaultIssueWidth

Returns the default initialized model.

Definition at line 406 of file MCSchedule.h.

Referenced by llvm::MCSubtargetInfo::getSchedModelForCPU(), and llvm::MCSubtargetInfo::InitMCProcessorInfo().

◆ DefaultHighLatency

◆ DefaultIssueWidth

◆ DefaultLoadLatency

◆ DefaultLoopMicroOpBufferSize

◆ DefaultMicroOpBufferSize

◆ DefaultMispredictPenalty

◆ EnableIntervals

bool llvm::MCSchedModel::EnableIntervals

◆ ExtraProcessorInfo

◆ HighLatency

unsigned llvm::MCSchedModel::HighLatency

◆ InstrItineraries

◆ IssueWidth

◆ LoadLatency

unsigned llvm::MCSchedModel::LoadLatency

◆ LoopMicroOpBufferSize

unsigned llvm::MCSchedModel::LoopMicroOpBufferSize

◆ MicroOpBufferSize

unsigned llvm::MCSchedModel::MicroOpBufferSize

◆ MispredictPenalty

unsigned llvm::MCSchedModel::MispredictPenalty

◆ NumProcResourceKinds

unsigned llvm::MCSchedModel::NumProcResourceKinds

◆ NumSchedClasses

unsigned llvm::MCSchedModel::NumSchedClasses

◆ PostRAScheduler

bool llvm::MCSchedModel::PostRAScheduler

◆ ProcID

◆ ProcResourceTable

◆ SchedClassTable

The documentation for this struct was generated from the following files:

• include/llvm/MC/MCSchedule.h
• lib/MC/MCSchedule.cpp