MachineRegisterInfo.h Source File (original) (raw)

13#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H

14#define LLVM_CODEGEN_MACHINEREGISTERINFO_H

34#include

35#include

36#include

37#include

38#include

39#include

40#include

42namespace llvm {

54public:

56 virtual void anchor();

58 public:

66 };

68private:

73 const bool TracksSubRegLiveness;

92 bool IsUpdatedCSRsInitialized = false;

100

101

102

103

104

105

108 RegAllocHints;

109

110

111

112 std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists;

113

114

115

119 return PhysRegUseDefLists[RegNo.id()];

120 }

121

122 MachineOperand *getRegUseDefListHead(Register RegNo) const {

123 if (RegNo.isVirtual())

124 return VRegInfo[RegNo.id()].second;

125 return PhysRegUseDefLists[RegNo.id()];

126 }

127

128

129 static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {

130 assert(MO && MO->isReg() && "This is not a register operand!");

131 return MO->Contents.Reg.Next;

132 }

133

134

135

136 BitVector UsedPhysRegMask;

137

138

139

140

141

142 BitVector ReservedRegs;

143

144 using VRegToTypeMap = IndexedMap<LLT, VirtReg2IndexFunctor>;

145

146 VRegToTypeMap VRegToType;

147

148

149

150

151

152 std::vector<std::pair<MCRegister, Register>> LiveIns;

153

154public:

158

160 return MF->getSubtarget().getRegisterInfo();

161 }

162

164

165

166 assert(TheDelegates.count(delegate) &&

167 "Only an existing delegate can perform reset!");

168 TheDelegates.erase(delegate);

169 }

170

172 assert(delegate && !TheDelegates.count(delegate) &&

173 "Attempted to add null delegate, or to change it without "

174 "first resetting it!");

175

176 TheDelegates.insert(delegate);

177 }

178

180 for (auto *TheDelegate : TheDelegates)

181 TheDelegate->MRI_NoteNewVirtualRegister(Reg);

182 }

183

185 for (auto *TheDelegate : TheDelegates)

186 TheDelegate->MRI_NoteCloneVirtualRegister(NewReg, SrcReg);

187 }

188

190

191

192

193

194

195

196

197

198

199

200

201

202 bool isSSA() const { return MF->getProperties().hasIsSSA(); }

203

204

205 void leaveSSA() { MF->getProperties().resetIsSSA(); }

206

207

208

210 return MF->getProperties().hasTracksLiveness();

211 }

212

213

214

215

216

217

219

220

221

231 return TracksSubRegLiveness;

232 }

233

234

235

236

237

238

240

241

242

243

245

246

247

248

250

251

252

254

255

257

258

260

261

264

265

267

268

270

271

272

273

274 template <bool Uses, bool Defs, bool SkipDebug, bool ByOperand, bool ByInstr>

276 template <bool Uses, bool Defs, bool SkipDebug, bool ByInstr>

278

279

282

283

284

290

294

295

296

305

310

311

312

321

325

326

327

329

330

331

340

345

346

347

348

357

362

363

364

365

374

379

380

381

385

386

392

396

397

398

407

412

413

414

423

427

428

429

431

435

437 assert((Name.empty() || !VRegNames.contains(Name)) &&

438 "Named VRegs Must be Unique.");

439 if (!Name.empty()) {

440 VRegNames.insert(Name);

441 VReg2Name.grow(Reg);

442 VReg2Name[Reg] = Name.str();

443 }

444 }

445

446

447

451

452

453

456 if (DI == def_end())

457 return nullptr;

458

461 return &*OneDef;

462 return nullptr;

463 }

464

465

471

475

476

477

486

491

492

493

502

506

507

508

510

511

512

516

517

518

527

532

533

534

535

544

549

550

551

552

561

566

567

568

572

573

574

576

577

578

579

581

582

583

585

586

587

589

590

591

593

594

595

596

597

598

599

600

601

602

603

604

605

606

607

608

609

610

611

612

614

615

616

617

619

620

621

622

624

625

626

627

628

630

632

633

634

636

637

638

640

641

642

643

644

645

646

647

650 "Register class not set, wrong accessor");

652 }

653

654

655

656

657

658

659

660

661

662

663

664

669

670

671

675

676

677

678

679

684

685

686

687

689 return VRegInfo[Reg].first;

690 }

691

692

694

695

697

700 VRegInfo[Reg].first = RCOrRB;

701 }

702

703

704

705

706

707

708

709

710

711

712

713

716 unsigned MinNumRegs = 0);

717

718

719

720

721

722

723

724

725

726

727

728

730 unsigned MinNumRegs = 0);

731

732

733

734

735

736

737

738

740

741

742

745

746

747

752

753

754

755

759

760

761

764

765

766

768

769

770

772 if (Reg.isVirtual() && VRegToType.inBounds(Reg))

773 return VRegToType[Reg];

774 return LLT{};

775 }

776

777

779

780

781

783

784

785

787

788

789

790

791

792

794

795

797

798

800

801

802

803

807 auto &Hint = RegAllocHints[VReg];

808 Hint.first = Type;

809 Hint.second.clear();

810 Hint.second.push_back(PrefReg);

811 }

812

813

814

818 RegAllocHints[VReg].second.push_back(PrefReg);

819 }

820

821

822

826

828 assert (!RegAllocHints[VReg].first &&

829 "Expected to clear a non-target hint!");

830 if (RegAllocHints.inBounds(VReg))

831 RegAllocHints[VReg].second.clear();

832 }

833

834

835

836

839 if (!RegAllocHints.inBounds(VReg))

841 auto &Hint = RegAllocHints[VReg.id()];

842 Register BestHint = (Hint.second.size() ? Hint.second[0] : Register());

843 return {Hint.first, BestHint};

844 }

845

846

847

851 return Hint.first ? Register() : Hint.second;

852 }

853

854

855

856 const std::pair<unsigned, SmallVector<Register, 4>> *

859 return RegAllocHints.inBounds(VReg) ? &RegAllocHints[VReg] : nullptr;

860 }

861

862

863

864

866

867

868

871

872

873 auto UpdateOp = [this, &NewReg, &OldReg](MachineOperand &Op) {

874 if (Op.isReg() &&

876 Op.setReg(NewReg);

877 };

878

879

880

882 if (MI->isDebugValue()) {

883 for (auto &Op : MI->debug_operands())

884 UpdateOp(Op);

885 assert(MI->hasDebugOperandForReg(NewReg) &&

886 "Expected debug value to have some overlap with OldReg");

887 } else if (MI->isDebugPHI()) {

888 UpdateOp(MI->getOperand(0));

889 } else {

890 llvm_unreachable("Non-DBG_VALUE, Non-DBG_PHI debug instr updated");

891 }

892 }

893 }

894

895

896

897

898

899

900

902 bool SkipNoReturnDef = false) const;

903

904

905

906

907

909 bool SkipRegMaskTest = false) const;

910

911

912

914 UsedPhysRegMask.setBitsNotInMask(RegMask);

915 }

916

918

919

920

921

922

923

924

925

926

927

928

929

930

931

932

934

935

936

937

940 "Reserved registers haven't been frozen yet. ");

942

943 for (; R.isValid(); ++R)

944 ReservedRegs.set((*R).id());

945 }

946

947

948

950 return !ReservedRegs.empty();

951 }

952

953

954

955

959

960

961

962

965 "Reserved registers haven't been frozen yet. "

966 "Use TRI::getReservedRegs().");

967 return ReservedRegs;

968 }

969

970

971

972

973

977

978

979

980

981

982

983

985

986

987

988

989

990

991

996

997

998

999

1000

1001

1002

1004 LiveIns.push_back(std::make_pair(Reg, vreg));

1005 }

1006

1007

1008

1010 std::vector<std::pair<MCRegister,Register>>::const_iterator;

1014

1016 return LiveIns;

1017 }

1018

1020

1021

1022

1024

1025

1026

1028

1029

1030

1034

1035

1036

1038

1039

1040

1041

1042

1043

1044

1045 template <bool ReturnUses, bool ReturnDefs, bool SkipDebug, bool ByOperand,

1046 bool ByInstr>

1047 class defusechain_iterator {

1049 static_assert(!ByOperand || !ByInstr,

1050 "ByOperand and ByInstr are mutually exclusive");

1051

1052 public:

1058

1059 private:

1061

1063

1064

1065 if (op) {

1066 if ((!ReturnUses && op->isUse()) ||

1067 (!ReturnDefs && op->isDef()) ||

1068 (SkipDebug && op->isDebug()))

1069 advance();

1070 }

1071 }

1072

1073 void advance() {

1074 assert(Op && "Cannot increment end iterator!");

1075 Op = getNextOperandForReg(Op);

1076

1077

1078 if (!ReturnUses) {

1079 if (Op) {

1080 if (Op->isUse())

1081 Op = nullptr;

1082 else

1083 assert(->isDebug() && "Can't have debug defs");

1084 }

1085 } else {

1086

1087 while (Op && ((!ReturnDefs && Op->isDef()) ||

1088 (SkipDebug && Op->isDebug())))

1089 Op = getNextOperandForReg(Op);

1090 }

1091 }

1092

1093 public:

1095

1096 bool operator==(const defusechain_iterator &x) const {

1097 return Op == x.Op;

1098 }

1102

1103

1104 defusechain_iterator &operator++() {

1105 assert(Op && "Cannot increment end iterator!");

1106 if (ByOperand)

1107 advance();

1108 else if (ByInstr) {

1110 do {

1111 advance();

1112 } while (Op && Op->getParent() == P);

1113 } else {

1116 do {

1117 advance();

1118 } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);

1119 }

1120

1121 return *this;

1122 }

1123 defusechain_iterator operator++(int) {

1124 defusechain_iterator tmp = *this; ++*this; return tmp;

1125 }

1126

1127

1128

1130 assert(Op && "Cannot dereference end iterator!");

1131 return Op - &Op->getParent()->getOperand(0);

1132 }

1133

1134

1136 assert(Op && "Cannot dereference end iterator!");

1137 return *Op;

1138 }

1139

1141 assert(Op && "Cannot dereference end iterator!");

1142 return Op;

1143 }

1144 };

1145

1146

1147

1148

1149

1150

1151

1152 template <bool ReturnUses, bool ReturnDefs, bool SkipDebug, bool ByInstr>

1153 class defusechain_instr_iterator {

1155

1156 public:

1162

1163 private:

1165

1167

1168

1169 if (op) {

1170 if ((!ReturnUses && op->isUse()) ||

1171 (!ReturnDefs && op->isDef()) ||

1172 (SkipDebug && op->isDebug()))

1173 advance();

1174 }

1175 }

1176

1177 void advance() {

1178 assert(Op && "Cannot increment end iterator!");

1179 Op = getNextOperandForReg(Op);

1180

1181

1182 if (!ReturnUses) {

1183 if (Op) {

1184 if (Op->isUse())

1185 Op = nullptr;

1186 else

1187 assert(->isDebug() && "Can't have debug defs");

1188 }

1189 } else {

1190

1191 while (Op && ((!ReturnDefs && Op->isDef()) ||

1192 (SkipDebug && Op->isDebug())))

1193 Op = getNextOperandForReg(Op);

1194 }

1195 }

1196

1197 public:

1199

1200 bool operator==(const defusechain_instr_iterator &x) const {

1201 return Op == x.Op;

1202 }

1203 bool operator!=(const defusechain_instr_iterator &x) const {

1205 }

1206

1207

1208 defusechain_instr_iterator &operator++() {

1209 assert(Op && "Cannot increment end iterator!");

1210 if (ByInstr) {

1212 do {

1213 advance();

1214 } while (Op && Op->getParent() == P);

1215 } else {

1218 do {

1219 advance();

1220 } while (Op && getBundleStart(Op->getParent()->getIterator()) == P);

1221 }

1222

1223 return *this;

1224 }

1225 defusechain_instr_iterator operator++(int) {

1226 defusechain_instr_iterator tmp = *this; ++*this; return tmp;

1227 }

1228

1229

1231 assert(Op && "Cannot dereference end iterator!");

1232 if (!ByInstr)

1233 return *getBundleStart(Op->getParent()->getIterator());

1234 return *Op->getParent();

1235 }

1236

1238 };

1239};

1240

1241

1242

1243

1245 const int *PSet = nullptr;

1246 unsigned Weight = 0;

1247

1248public:

1250

1256 PSet = TRI->getRegClassPressureSets(RC);

1257 Weight = TRI->getRegClassWeight(RC).RegWeight;

1258 } else {

1259 PSet = TRI->getRegUnitPressureSets(VRegOrUnit.asMCRegUnit());

1260 Weight = TRI->getRegUnitWeight(VRegOrUnit.asMCRegUnit());

1261 }

1262 if (*PSet == -1)

1263 PSet = nullptr;

1264 }

1265

1267

1269

1271

1274 ++PSet;

1275 if (*PSet == -1)

1276 PSet = nullptr;

1277 }

1278};

1279

1280inline PSetIterator

1284

1285}

1286

1287#endif

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

This file implements the BitVector class.

#define LLVM_LIKELY(EXPR)

iv Induction Variable Users

This file implements an indexed map.

const size_t AbstractManglingParser< Derived, Alloc >::NumOps

A common definition of LaneBitmask for use in TableGen and CodeGen.

Promote Memory to Register

This file defines the PointerUnion class, which is a discriminated union of pointer types.

This file defines the SmallPtrSet class.

This file defines the SmallVector class.

StringSet - A set-like wrapper for the StringMap.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

bool test(unsigned Idx) const

MCRegAliasIterator enumerates all registers aliasing Reg.

Wrapper class representing physical registers. Should be passed by value.

constexpr unsigned id() const

Instructions::iterator instr_iterator

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

virtual void MRI_NoteNewVirtualRegister(Register Reg)=0

virtual void MRI_NoteCloneVirtualRegister(Register NewReg, Register SrcReg)

Definition MachineRegisterInfo.h:62

virtual ~Delegate()=default

defusechain_iterator - This class provides iterator support for machine operands in the function that...

Definition MachineRegisterInfo.h:1153

value_type * pointer

Definition MachineRegisterInfo.h:1160

defusechain_instr_iterator()=default

bool operator==(const defusechain_instr_iterator &x) const

Definition MachineRegisterInfo.h:1200

defusechain_instr_iterator operator++(int)

Definition MachineRegisterInfo.h:1225

std::forward_iterator_tag iterator_category

Definition MachineRegisterInfo.h:1157

MachineInstr & operator*() const

Definition MachineRegisterInfo.h:1230

bool operator!=(const defusechain_instr_iterator &x) const

Definition MachineRegisterInfo.h:1203

MachineInstr * operator->() const

Definition MachineRegisterInfo.h:1237

MachineInstr value_type

Definition MachineRegisterInfo.h:1158

std::ptrdiff_t difference_type

Definition MachineRegisterInfo.h:1159

defusechain_instr_iterator & operator++()

Definition MachineRegisterInfo.h:1208

friend class MachineRegisterInfo

Definition MachineRegisterInfo.h:1154

value_type & reference

Definition MachineRegisterInfo.h:1161

reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...

Definition MachineRegisterInfo.h:1047

value_type * pointer

Definition MachineRegisterInfo.h:1056

defusechain_iterator operator++(int)

Definition MachineRegisterInfo.h:1123

MachineOperand & operator*() const

Definition MachineRegisterInfo.h:1135

unsigned getOperandNo() const

getOperandNo - Return the operand # of this MachineOperand in its MachineInstr.

Definition MachineRegisterInfo.h:1129

std::ptrdiff_t difference_type

Definition MachineRegisterInfo.h:1055

defusechain_iterator()=default

std::forward_iterator_tag iterator_category

Definition MachineRegisterInfo.h:1053

bool operator!=(const defusechain_iterator &x) const

Definition MachineRegisterInfo.h:1099

defusechain_iterator & operator++()

Definition MachineRegisterInfo.h:1104

value_type & reference

Definition MachineRegisterInfo.h:1057

MachineOperand * operator->() const

Definition MachineRegisterInfo.h:1140

MachineOperand value_type

Definition MachineRegisterInfo.h:1054

friend class MachineRegisterInfo

Definition MachineRegisterInfo.h:1048

bool operator==(const defusechain_iterator &x) const

Definition MachineRegisterInfo.h:1096

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

Definition MachineRegisterInfo.h:53

LLVM_ABI void verifyUseList(Register Reg) const

Verify the sanity of the use list for Reg.

LLVM_ABI bool hasOneNonDBGUse(Register RegNo) const

hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.

getSimpleHint - same as getRegAllocationHint except it will only return a target independent hint.

Definition MachineRegisterInfo.h:848

void leaveSSA()

Definition MachineRegisterInfo.h:205

use_nodbg_iterator use_nodbg_begin(Register RegNo) const

Definition MachineRegisterInfo.h:521

reg_nodbg_iterator reg_nodbg_begin(Register RegNo) const

Definition MachineRegisterInfo.h:334

void insertVRegByName(StringRef Name, Register Reg)

Definition MachineRegisterInfo.h:436

iterator_range< reg_bundle_iterator > reg_bundles(Register Reg) const

Definition MachineRegisterInfo.h:322

defusechain_instr_iterator< true, false, true, true > use_instr_nodbg_iterator

use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk all uses of the specified r...

Definition MachineRegisterInfo.h:536

LLVM_ABI void verifyUseLists() const

Verify the use list of all registers.

defusechain_instr_iterator< false, true, false, false > def_bundle_iterator

def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the specified register,...

Definition MachineRegisterInfo.h:415

bool livein_empty() const

Definition MachineRegisterInfo.h:1013

VRegAttrs getVRegAttrs(Register Reg) const

Returns register class or bank and low level type of Reg.

Definition MachineRegisterInfo.h:756

static reg_iterator reg_end()

Definition MachineRegisterInfo.h:289

LLVM_ABI void markUsesInDebugValueAsUndef(Register Reg) const

markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...

bool tracksLiveness() const

tracksLiveness - Returns true when tracking register liveness accurately.

Definition MachineRegisterInfo.h:209

defusechain_instr_iterator< true, false, false, true > use_instr_iterator

use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the specified register,...

Definition MachineRegisterInfo.h:478

const BitVector & getUsedPhysRegsMask() const

Definition MachineRegisterInfo.h:917

iterator_range< reg_iterator > reg_operands(Register Reg) const

Definition MachineRegisterInfo.h:291

LLVM_ABI bool recomputeRegClass(Register Reg)

recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the ...

static reg_instr_nodbg_iterator reg_instr_nodbg_end()

Definition MachineRegisterInfo.h:354

reg_instr_iterator reg_instr_begin(Register RegNo) const

Definition MachineRegisterInfo.h:299

defusechain_instr_iterator< true, true, false, false > reg_bundle_iterator

reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses of the specified registe...

Definition MachineRegisterInfo.h:313

MachineRegisterInfo & operator=(const MachineRegisterInfo &)=delete

bool isUpdatedCSRsInitialized() const

Returns true if the updated CSR list was initialized and false otherwise.

Definition MachineRegisterInfo.h:239

LLVM_ABI void freezeReservedRegs()

freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...

defusechain_instr_iterator< true, false, true, false > use_bundle_nodbg_iterator

use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk all uses of the specifie...

Definition MachineRegisterInfo.h:553

const TargetRegisterClass * getRegClass(Register Reg) const

Return the register class of the specified virtual register.

Definition MachineRegisterInfo.h:648

static use_nodbg_iterator use_nodbg_end()

Definition MachineRegisterInfo.h:524

reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(Register RegNo) const

Definition MachineRegisterInfo.h:368

defusechain_instr_iterator< true, true, true, false > reg_bundle_nodbg_iterator

reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk all defs and uses of the...

Definition MachineRegisterInfo.h:366

LLVM_ABI void clearKillFlags(Register Reg) const

clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...

LLVM_ABI MachineRegisterInfo(MachineFunction *MF)

reg_iterator reg_begin(Register RegNo) const

Definition MachineRegisterInfo.h:286

defusechain_instr_iterator< true, true, true, true > reg_instr_nodbg_iterator

reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk all defs and uses of the sp...

Definition MachineRegisterInfo.h:349

LLVM_ABI MachineInstr * getVRegDef(Register Reg) const

getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...

iterator_range< def_instr_iterator > def_instructions(Register Reg) const

Definition MachineRegisterInfo.h:409

bool shouldTrackSubRegLiveness(Register VReg) const

Definition MachineRegisterInfo.h:225

iterator_range< use_nodbg_iterator > use_nodbg_operands(Register Reg) const

Definition MachineRegisterInfo.h:529

LLVM_ABI void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)

EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block.

static reg_instr_iterator reg_instr_end()

Definition MachineRegisterInfo.h:302

use_instr_iterator use_instr_begin(Register RegNo) const

Definition MachineRegisterInfo.h:480

bool subRegLivenessEnabled() const

Definition MachineRegisterInfo.h:230

friend class defusechain_iterator

Definition MachineRegisterInfo.h:280

PSetIterator getPressureSets(VirtRegOrUnit VRegOrUnit) const

Get an iterator over the pressure sets affected by the virtual register or register unit.

Definition MachineRegisterInfo.h:1281

bool use_nodbg_empty(Register RegNo) const

use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.

Definition MachineRegisterInfo.h:569

const RegClassOrRegBank & getRegClassOrRegBank(Register Reg) const

Return the register bank or register class of Reg.

Definition MachineRegisterInfo.h:688

LLVM_ABI MachineOperand * getOneNonDBGUse(Register RegNo) const

If the register has a single non-Debug use, returns it; otherwise returns nullptr.

iterator_range< reg_bundle_nodbg_iterator > reg_nodbg_bundles(Register Reg) const

Definition MachineRegisterInfo.h:376

bool isReserved(MCRegister PhysReg) const

isReserved - Returns true when PhysReg is a reserved register.

Definition MachineRegisterInfo.h:974

const RegisterBank * getRegBank(Register Reg) const

Return the register bank of Reg.

Definition MachineRegisterInfo.h:672

static def_instr_iterator def_instr_end()

Definition MachineRegisterInfo.h:404

LLVM_ABI void dumpUses(Register RegNo) const

LLVM_ABI void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)

Move NumOps operands from Src to Dst, updating use-def lists as needed.

MachineOperand * getOneDef(Register Reg) const

Returns the defining operand if there is exactly one operand defining the specified register,...

Definition MachineRegisterInfo.h:454

def_iterator def_begin(Register RegNo) const

Definition MachineRegisterInfo.h:388

defusechain_iterator< true, false, false, true, false > use_iterator

use_iterator/use_begin/use_end - Walk all uses of the specified register.

Definition MachineRegisterInfo.h:466

defusechain_instr_iterator< false, true, false, true > def_instr_iterator

def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the specified register,...

Definition MachineRegisterInfo.h:399

static def_bundle_iterator def_bundle_end()

Definition MachineRegisterInfo.h:420

const BitVector & getReservedRegs() const

getReservedRegs - Returns a reference to the frozen set of reserved registers.

Definition MachineRegisterInfo.h:963

iterator_range< use_bundle_nodbg_iterator > use_nodbg_bundles(Register Reg) const

Definition MachineRegisterInfo.h:563

void setRegClassOrRegBank(Register Reg, const RegClassOrRegBank &RCOrRB)

Definition MachineRegisterInfo.h:698

LLVM_ABI Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")

createVirtualRegister - Create and return a new virtual register in the function with the specified r...

def_instr_iterator def_instr_begin(Register RegNo) const

Definition MachineRegisterInfo.h:401

LLT getType(Register Reg) const

Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.

Definition MachineRegisterInfo.h:771

bool reservedRegsFrozen() const

reservedRegsFrozen - Returns true after freezeReservedRegs() was called to ensure the set of reserved...

Definition MachineRegisterInfo.h:949

bool def_empty(Register RegNo) const

def_empty - Return true if there are no instructions defining the specified register (it may be live-...

Definition MachineRegisterInfo.h:430

bool hasOneUse(Register RegNo) const

hasOneUse - Return true if there is exactly one instruction using the specified register.

Definition MachineRegisterInfo.h:513

void resetDelegate(Delegate *delegate)

Definition MachineRegisterInfo.h:163

LLVM_ABI bool isLiveIn(Register Reg) const

bool reg_nodbg_empty(Register RegNo) const

reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.

Definition MachineRegisterInfo.h:382

std::vector< std::pair< MCRegister, Register > >::const_iterator livein_iterator

Definition MachineRegisterInfo.h:1009

static use_bundle_iterator use_bundle_end()

Definition MachineRegisterInfo.h:499

const RegisterBank * getRegBankOrNull(Register Reg) const

Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...

Definition MachineRegisterInfo.h:680

void invalidateLiveness()

invalidateLiveness - Indicates that register liveness is no longer being tracked accurately.

Definition MachineRegisterInfo.h:218

static reg_nodbg_iterator reg_nodbg_end()

Definition MachineRegisterInfo.h:337

use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const

Definition MachineRegisterInfo.h:538

ArrayRef< std::pair< MCRegister, Register > > liveins() const

Definition MachineRegisterInfo.h:1015

use_bundle_nodbg_iterator use_bundle_nodbg_begin(Register RegNo) const

Definition MachineRegisterInfo.h:555

LLVM_ABI bool hasAtMostUserInstrs(Register Reg, unsigned MaxUsers) const

hasAtMostUses - Return true if the given register has at most MaxUsers non-debug user instructions.

static use_instr_iterator use_instr_end()

Definition MachineRegisterInfo.h:483

LLVM_ABI bool hasOneNonDBGUser(Register RegNo) const

hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...

LLVM_ABI void clearVirtRegs()

clearVirtRegs - Remove all virtual registers (after physreg assignment).

LLVM_ABI Register createIncompleteVirtualRegister(StringRef Name="")

Creates a new virtual register that has no register class, register bank or size assigned yet.

bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const

Returns true if liveness for register class RC should be tracked at the subregister level.

Definition MachineRegisterInfo.h:222

bool isAllocatable(MCRegister PhysReg) const

isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...

Definition MachineRegisterInfo.h:992

LLVM_ABI void setRegBank(Register Reg, const RegisterBank &RegBank)

Set the register bank to RegBank for Reg.

defusechain_iterator< true, false, true, true, false > use_nodbg_iterator

use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the specified register,...

Definition MachineRegisterInfo.h:519

defusechain_iterator< false, true, false, true, false > def_iterator

def_iterator/def_begin/def_end - Walk all defs of the specified register.

Definition MachineRegisterInfo.h:387

bool isSSA() const

Definition MachineRegisterInfo.h:202

LLVM_ABI MCRegister getLiveInPhysReg(Register VReg) const

getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...

LLVM_ABI const MCPhysReg * getCalleeSavedRegs() const

Returns list of callee saved registers.

std::pair< unsigned, Register > getRegAllocationHint(Register VReg) const

getRegAllocationHint - Return the register allocation hint for the specified virtual register.

Definition MachineRegisterInfo.h:837

iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(Register Reg) const

Definition MachineRegisterInfo.h:546

iterator_range< def_iterator > def_operands(Register Reg) const

Definition MachineRegisterInfo.h:393

LLVM_ABI void setType(Register VReg, LLT Ty)

Set the low-level type of VReg to Ty.

void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg)

setRegAllocationHint - Specify a register allocation hint for the specified virtual register.

Definition MachineRegisterInfo.h:804

void addDelegate(Delegate *delegate)

Definition MachineRegisterInfo.h:171

const MachineFunction & getMF() const

Definition MachineRegisterInfo.h:189

bool hasOneDef(Register RegNo) const

Return true if there is exactly one operand defining the specified register.

Definition MachineRegisterInfo.h:448

static reg_bundle_nodbg_iterator reg_bundle_nodbg_end()

Definition MachineRegisterInfo.h:371

LLVM_ABI void setRegClass(Register Reg, const TargetRegisterClass *RC)

setRegClass - Set the register class of the specified virtual register.

LLVM_ABI Register createGenericVirtualRegister(LLT Ty, StringRef Name="")

Create and return a new generic virtual register with low-level type Ty.

bool canReserveReg(MCRegister PhysReg) const

canReserveReg - Returns true if PhysReg can be used as a reserved register.

Definition MachineRegisterInfo.h:956

LLVM_ABI bool isReservedRegUnit(MCRegUnit Unit) const

Returns true when the given register unit is considered reserved.

LLVM_ABI void clearVirtRegTypes()

Remove all types associated to virtual registers (after instruction selection and constraining of all...

LLVM_ABI Register getLiveInVirtReg(MCRegister PReg) const

getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in virtual r...

const TargetRegisterClass * getRegClassOrNull(Register Reg) const

Return the register class of Reg, or null if Reg has not been assigned a register class yet.

Definition MachineRegisterInfo.h:665

void setSimpleHint(Register VReg, Register PrefReg)

Specify the preferred (target independent) register allocation hint for the specified virtual registe...

Definition MachineRegisterInfo.h:823

static def_iterator def_end()

Definition MachineRegisterInfo.h:391

LLVM_ABI void disableCalleeSavedRegister(MCRegister Reg)

Disables the register from the list of CSRs.

use_bundle_iterator use_bundle_begin(Register RegNo) const

Definition MachineRegisterInfo.h:496

livein_iterator livein_end() const

Definition MachineRegisterInfo.h:1012

reg_bundle_iterator reg_bundle_begin(Register RegNo) const

Definition MachineRegisterInfo.h:315

iterator_range< reg_instr_iterator > reg_instructions(Register Reg) const

Definition MachineRegisterInfo.h:307

void noteNewVirtualRegister(Register Reg)

Definition MachineRegisterInfo.h:179

static use_bundle_nodbg_iterator use_bundle_nodbg_end()

Definition MachineRegisterInfo.h:558

const std::pair< unsigned, SmallVector< Register, 4 > > * getRegAllocationHints(Register VReg) const

getRegAllocationHints - Return a reference to the vector of all register allocation hints for VReg.

Definition MachineRegisterInfo.h:857

LLVM_ABI void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)

Sets the updated Callee Saved Registers list.

static reg_bundle_iterator reg_bundle_end()

Definition MachineRegisterInfo.h:318

iterator_range< use_instr_iterator > use_instructions(Register Reg) const

Definition MachineRegisterInfo.h:488

void reserveReg(MCRegister PhysReg, const TargetRegisterInfo *TRI)

reserveReg – Mark a register as reserved so checks like isAllocatable will not suggest using it.

Definition MachineRegisterInfo.h:938

const TargetRegisterInfo * getTargetRegisterInfo() const

Definition MachineRegisterInfo.h:159

LLVM_ABI LaneBitmask getMaxLaneMaskForVReg(Register Reg) const

Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...

use_iterator use_begin(Register RegNo) const

Definition MachineRegisterInfo.h:467

void addRegAllocationHint(Register VReg, Register PrefReg)

addRegAllocationHint - Add a register allocation hint to the hints vector for VReg.

Definition MachineRegisterInfo.h:815

LLVM_ABI bool isConstantPhysReg(MCRegister PhysReg) const

Returns true if PhysReg is unallocatable and constant throughout the function.

iterator_range< reg_nodbg_iterator > reg_nodbg_operands(Register Reg) const

Definition MachineRegisterInfo.h:342

LLVM_ABI Register cloneVirtualRegister(Register VReg, StringRef Name="")

Create and return a new virtual register in the function with the same attributes as the given regist...

void addPhysRegsUsedFromRegMask(const uint32_t *RegMask)

addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.

Definition MachineRegisterInfo.h:913

MachineRegisterInfo(const MachineRegisterInfo &)=delete

defusechain_instr_iterator< true, false, false, false > use_bundle_iterator

use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the specified register,...

Definition MachineRegisterInfo.h:494

static use_iterator use_end()

Definition MachineRegisterInfo.h:470

void addLiveIn(MCRegister Reg, Register vreg=Register())

addLiveIn - Add the specified register as a live-in.

Definition MachineRegisterInfo.h:1003

LLVM_ABI bool constrainRegAttrs(Register Reg, Register ConstrainingReg, unsigned MinNumRegs=0)

Constrain the register class or the register bank of the virtual register Reg (and low-level type) to...

iterator_range< def_bundle_iterator > def_bundles(Register Reg) const

Definition MachineRegisterInfo.h:424

defusechain_instr_iterator< true, true, false, true > reg_instr_iterator

reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses of the specified register,...

Definition MachineRegisterInfo.h:297

LLVM_ABI const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)

constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...

void clearSimpleHint(Register VReg)

Definition MachineRegisterInfo.h:827

defusechain_iterator< true, true, false, true, false > reg_iterator

reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified register.

Definition MachineRegisterInfo.h:285

void noteCloneVirtualRegister(Register NewReg, Register SrcReg)

Definition MachineRegisterInfo.h:184

iterator_range< use_iterator > use_operands(Register Reg) const

Definition MachineRegisterInfo.h:472

livein_iterator livein_begin() const

Definition MachineRegisterInfo.h:1011

friend class defusechain_instr_iterator

Definition MachineRegisterInfo.h:281

reg_instr_nodbg_iterator reg_instr_nodbg_begin(Register RegNo) const

Definition MachineRegisterInfo.h:351

unsigned getNumVirtRegs() const

getNumVirtRegs - Return the number of virtual registers created.

Definition MachineRegisterInfo.h:796

iterator_range< reg_instr_nodbg_iterator > reg_nodbg_instructions(Register Reg) const

Definition MachineRegisterInfo.h:359

LLVM_ABI void removeRegOperandFromUseList(MachineOperand *MO)

Remove MO from its use-def list.

bool use_empty(Register RegNo) const

use_empty - Return true if there are no instructions using the specified register.

Definition MachineRegisterInfo.h:509

bool reg_empty(Register RegNo) const

reg_empty - Return true if there are no instructions using or defining the specified register (it may...

Definition MachineRegisterInfo.h:328

StringRef getVRegName(Register Reg) const

Definition MachineRegisterInfo.h:432

iterator_range< use_bundle_iterator > use_bundles(Register Reg) const

Definition MachineRegisterInfo.h:503

LLVM_ABI void replaceRegWith(Register FromReg, Register ToReg)

replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.

LLVM_ABI bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef=false) const

Return true if the specified register is modified in this function.

void updateDbgUsersToReg(MCRegister OldReg, MCRegister NewReg, ArrayRef< MachineInstr * > Users) const

updateDbgUsersToReg - Update a collection of debug instructions to refer to the designated register.

Definition MachineRegisterInfo.h:869

LLVM_ABI void addRegOperandToUseList(MachineOperand *MO)

Add MO to the linked list of operands for its register.

LLVM_ABI MachineInstr * getOneNonDBGUser(Register RegNo) const

If the register has a single non-Debug instruction using the specified register, returns it; otherwis...

LLVM_ABI MachineInstr * getUniqueVRegDef(Register Reg) const

getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...

def_bundle_iterator def_bundle_begin(Register RegNo) const

Definition MachineRegisterInfo.h:417

static use_instr_nodbg_iterator use_instr_nodbg_end()

Definition MachineRegisterInfo.h:541

LLVM_ABI bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest=false) const

Return true if the specified register is modified or read in this function.

defusechain_iterator< true, true, true, true, false > reg_nodbg_iterator

reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses of the specified register,...

Definition MachineRegisterInfo.h:332

Iterate over the pressure sets affected by the given physical or virtual register.

Definition MachineRegisterInfo.h:1244

unsigned operator*() const

Definition MachineRegisterInfo.h:1270

unsigned getWeight() const

Definition MachineRegisterInfo.h:1268

PSetIterator(VirtRegOrUnit VRegOrUnit, const MachineRegisterInfo *MRI)

Definition MachineRegisterInfo.h:1251

bool isValid() const

Definition MachineRegisterInfo.h:1266

void operator++()

Definition MachineRegisterInfo.h:1272

A discriminated union of two or more pointer types, with the discriminator in the low bit of the poin...

This class implements the register bank concept.

Wrapper class representing virtual and physical registers.

static Register index2VirtReg(unsigned Index)

Convert a 0-based index to a virtual register number.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

constexpr unsigned id() const

SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StringRef - Represent a constant reference to a string, i.e.

StringSet - A wrapper for StringMap that provides set-like functionality.

TargetInstrInfo - Interface to description of machine instruction set.

const bool HasDisjunctSubRegs

Whether the class supports two (or more) disjunct subregister indices.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

bool isInAllocatableClass(MCRegister RegNo) const

Return true if the register is in the allocation of any register class.

The instances of the Type class are immutable: once they are created, they are never changed.

Wrapper class representing a virtual register or register unit.

constexpr bool isVirtualReg() const

constexpr MCRegUnit asMCRegUnit() const

constexpr Register asVirtualReg() const

A range adaptor for a pair of iterators.

This provides a very simple, boring adaptor for a begin and end iterator into a range type.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

This is an optimization pass for GlobalISel generic memory operations.

MachineBasicBlock::instr_iterator getBundleStart(MachineBasicBlock::instr_iterator I)

Returns an iterator to the first instruction in the bundle containing I.

PointerUnion< const TargetRegisterClass *, const RegisterBank * > RegClassOrRegBank

Convenient type to represent either a register class or a register bank.

Definition MachineRegisterInfo.h:47

auto dyn_cast_if_present(const Y &Val)

dyn_cast_if_present - Functionally identical to dyn_cast, except that a null (or none in the case ...

iterator_range< T > make_range(T x, T y)

Convenience function for iterating over sub-ranges.

bool hasSingleElement(ContainerTy &&C)

Returns true if the given container only contains a single element.

bool isa(const From &Val)

isa - Return true if the parameter to the template is an instance of one of the template type argu...

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

DWARFExpression::Operation Op

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

All attributes(register class or bank and low-level type) a virtual register can have.

Definition MachineRegisterInfo.h:748

LLT Ty

Definition MachineRegisterInfo.h:750

RegClassOrRegBank RCOrRB

Definition MachineRegisterInfo.h:749