MachineRegisterInfo.h Source File (original) (raw)

13#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H

14#define LLVM_CODEGEN_MACHINEREGISTERINFO_H

32#include

33#include

34#include

35#include

36#include

37#include

38#include

40namespace llvm {

42class PSetIterator;

52public:

54 virtual void anchor();

56 public:

63 }

64 };

66private:

71 const bool TracksSubRegLiveness;

90 bool IsUpdatedCSRsInitialized = false;

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101

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106 RegAllocHints;

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110 std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists;

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117 return PhysRegUseDefLists[RegNo.id()];

118 }

119

120 MachineOperand *getRegUseDefListHead(Register RegNo) const {

121 if (RegNo.isVirtual())

122 return VRegInfo[RegNo.id()].second;

123 return PhysRegUseDefLists[RegNo.id()];

124 }

125

126

127 static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {

128 assert(MO && MO->isReg() && "This is not a register operand!");

129 return MO->Contents.Reg.Next;

130 }

131

132

133

134 BitVector UsedPhysRegMask;

135

136

137

138

139

140 BitVector ReservedRegs;

141

142 using VRegToTypeMap = IndexedMap<LLT, VirtReg2IndexFunctor>;

143

144 VRegToTypeMap VRegToType;

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148

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150 std::vector<std::pair<MCRegister, Register>> LiveIns;

151

152public:

156

159 }

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162

163

165 "Only an existing delegate can perform reset!");

166 TheDelegates.erase(delegate);

167 }

168

170 assert(delegate && !TheDelegates.count(delegate) &&

171 "Attempted to add null delegate, or to change it without "

172 "first resetting it!");

173

174 TheDelegates.insert(delegate);

175 }

176

178 for (auto *TheDelegate : TheDelegates)

179 TheDelegate->MRI_NoteNewVirtualRegister(Reg);

180 }

181

183 for (auto *TheDelegate : TheDelegates)

184 TheDelegate->MRI_NoteCloneVirtualRegister(NewReg, SrcReg);

185 }

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231 }

236 }

238 return TracksSubRegLiveness;

239 }

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280 template<bool Uses, bool Defs, bool SkipDebug,

281 bool ByOperand, bool ByInstr, bool ByBundle>

282 class defusechain_iterator;

283 template<bool Uses, bool Defs, bool SkipDebug,

284 bool ByOperand, bool ByInstr, bool ByBundle>

285 class defusechain_instr_iterator;

286

287

288 template<bool, bool, bool, bool, bool, bool>

290 template<bool, bool, bool, bool, bool, bool>

292

293

294

298 return reg_iterator(getRegUseDefListHead(RegNo));

299 }

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304 }

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312 }

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381 }

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395 }

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401 return def_iterator(getRegUseDefListHead(RegNo));

402 }

404

407 }

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415 }

418 }

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423 }

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431 }

434 }

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438 }

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446 }

447

450 "Named VRegs Must be Unique.");

451 if ( Name .empty()) {

454 VReg2Name[Reg] = Name.str();

455 }

456 }

457

458

459

462 }

463

464

465

468 if (DI == def_end())

469 return nullptr;

470

473 return &*OneDef;

474 return nullptr;

475 }

476

477

481 return use_iterator(getRegUseDefListHead(RegNo));

482 }

484

487 }

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495 }

498 }

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656 assert(isa<const TargetRegisterClass *>(VRegInfo[Reg.id()].first) &&

657 "Register class not set, wrong accessor");

658 return cast<const TargetRegisterClass *>(VRegInfo[Reg.id()].first);

659 }

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674 return dyn_cast_if_present<const TargetRegisterClass *>(Val);

675 }

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683 return dyn_cast_if_present<const RegisterBank *>(Val);

684 }

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691 }

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702 }

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717 unsigned MinNumRegs = 0);

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731 unsigned MinNumRegs = 0);

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752 };

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759 }

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772 if (Reg.isVirtual() && VRegToType.inBounds(Reg))

773 return VRegToType[Reg];

774 return LLT{};

775 }

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807 RegAllocHints[VReg].first = Type;

808 RegAllocHints[VReg].second.clear();

809 RegAllocHints[VReg].second.push_back(PrefReg);

810 }

811

812

813

817 RegAllocHints[VReg].second.push_back(PrefReg);

818 }

819

820

821

824 }

825

827 assert (!RegAllocHints[VReg].first &&

828 "Expected to clear a non-target hint!");

829 if (RegAllocHints.inBounds(VReg))

830 RegAllocHints[VReg].second.clear();

831 }

832

833

834

835

838 if (!RegAllocHints.inBounds(VReg))

840 Register BestHint = (RegAllocHints[VReg.id()].second.size() ?

841 RegAllocHints[VReg.id()].second[0] : Register());

842 return {RegAllocHints[VReg.id()].first, BestHint};

843 }

844

845

846

850 return Hint.first ? Register() : Hint.second;

851 }

852

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854

855 const std::pair<unsigned, SmallVector<Register, 4>> *

858 return RegAllocHints.inBounds(VReg) ? &RegAllocHints[VReg] : nullptr;

859 }

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871

872 auto UpdateOp = [this, &NewReg, &OldReg](MachineOperand &Op) {

873 if (Op.isReg() &&

875 Op.setReg(NewReg);

876 };

877

878

879

881 if (MI->isDebugValue()) {

882 for (auto &Op : MI->debug_operands())

883 UpdateOp(Op);

884 assert(MI->hasDebugOperandForReg(NewReg) &&

885 "Expected debug value to have some overlap with OldReg");

886 } else if (MI->isDebugPHI()) {

887 UpdateOp(MI->getOperand(0));

888 } else {

889 llvm_unreachable("Non-DBG_VALUE, Non-DBG_PHI debug instr updated");

890 }

891 }

892 }

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911 UsedPhysRegMask.setBitsNotInMask(RegMask);

912 }

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937 "Reserved registers haven't been frozen yet. ");

939

940 for (; R.isValid(); ++R)

941 ReservedRegs.set((*R).id());

942 }

943

944

945

947 return !ReservedRegs.empty();

948 }

949

950

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955 }

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962 "Reserved registers haven't been frozen yet. "

963 "Use TRI::getReservedRegs().");

964 return ReservedRegs;

965 }

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973 }

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992 }

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1001 LiveIns.push_back(std::make_pair(Reg, vreg));

1002 }

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1007 std::vector<std::pair<MCRegister,Register>>::const_iterator;

1011

1013 return LiveIns;

1014 }

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1042 template <bool ReturnUses, bool ReturnDefs, bool SkipDebug, bool ByOperand,

1043 bool ByInstr, bool ByBundle>

1046

1047 public:

1053

1054 private:

1056

1058

1059

1060 if (op) {

1061 if ((!ReturnUses && op->isUse()) ||

1062 (!ReturnDefs && op->isDef()) ||

1063 (SkipDebug && op->isDebug()))

1064 advance();

1065 }

1066 }

1067

1068 void advance() {

1069 assert(Op && "Cannot increment end iterator!");

1070 Op = getNextOperandForReg(Op);

1071

1072

1073 if (!ReturnUses) {

1074 if (Op) {

1075 if (Op->isUse())

1076 Op = nullptr;

1077 else

1078 assert(->isDebug() && "Can't have debug defs");

1079 }

1080 } else {

1081

1082 while (Op && ((!ReturnDefs && Op->isDef()) ||

1083 (SkipDebug && Op->isDebug())))

1084 Op = getNextOperandForReg(Op);

1085 }

1086 }

1087

1088 public:

1090

1092 return Op == x.Op;

1093 }

1096 }

1097

1098

1100 assert(Op && "Cannot increment end iterator!");

1101 if (ByOperand)

1102 advance();

1103 else if (ByInstr) {

1105 do {

1106 advance();

1107 } while (Op && Op->getParent() == P);

1108 } else if (ByBundle) {

1111 do {

1112 advance();

1114 }

1115

1116 return *this;

1117 }

1120 }

1121

1122

1123

1125 assert(Op && "Cannot dereference end iterator!");

1126 return Op - &Op->getParent()->getOperand(0);

1127 }

1128

1129

1131 assert(Op && "Cannot dereference end iterator!");

1132 return *Op;

1133 }

1134

1136 assert(Op && "Cannot dereference end iterator!");

1137 return Op;

1138 }

1139 };

1140

1141

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1146

1147 template <bool ReturnUses, bool ReturnDefs, bool SkipDebug, bool ByOperand,

1148 bool ByInstr, bool ByBundle>

1151

1152 public:

1158

1159 private:

1161

1163

1164

1165 if (op) {

1166 if ((!ReturnUses && op->isUse()) ||

1167 (!ReturnDefs && op->isDef()) ||

1168 (SkipDebug && op->isDebug()))

1169 advance();

1170 }

1171 }

1172

1173 void advance() {

1174 assert(Op && "Cannot increment end iterator!");

1175 Op = getNextOperandForReg(Op);

1176

1177

1178 if (!ReturnUses) {

1179 if (Op) {

1180 if (Op->isUse())

1181 Op = nullptr;

1182 else

1183 assert(->isDebug() && "Can't have debug defs");

1184 }

1185 } else {

1186

1187 while (Op && ((!ReturnDefs && Op->isDef()) ||

1188 (SkipDebug && Op->isDebug())))

1189 Op = getNextOperandForReg(Op);

1190 }

1191 }

1192

1193 public:

1195

1197 return Op == x.Op;

1198 }

1201 }

1202

1203

1205 assert(Op && "Cannot increment end iterator!");

1206 if (ByOperand)

1207 advance();

1208 else if (ByInstr) {

1210 do {

1211 advance();

1212 } while (Op && Op->getParent() == P);

1213 } else if (ByBundle) {

1216 do {

1217 advance();

1219 }

1220

1221 return *this;

1222 }

1225 }

1226

1227

1229 assert(Op && "Cannot dereference end iterator!");

1230 if (ByBundle)

1232 return *Op->getParent();

1233 }

1234

1236 };

1237};

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1243 const int *PSet = nullptr;

1244 unsigned Weight = 0;

1245

1246public:

1248

1253 PSet = TRI->getRegClassPressureSets(RC);

1254 Weight = TRI->getRegClassWeight(RC).RegWeight;

1255 } else {

1256 PSet = TRI->getRegUnitPressureSets(RegUnit);

1257 Weight = TRI->getRegUnitWeight(RegUnit);

1258 }

1259 if (*PSet == -1)

1260 PSet = nullptr;

1261 }

1262

1264

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1271 ++PSet;

1272 if (*PSet == -1)

1273 PSet = nullptr;

1274 }

1275};

1276

1277inline PSetIterator

1280}

1281

1282}

1283

1284#endif

unsigned const MachineRegisterInfo * MRI

This file implements the BitVector class.

#define LLVM_LIKELY(EXPR)

const HexagonInstrInfo * TII

iv Induction Variable Users

This file implements an indexed map.

A common definition of LaneBitmask for use in TableGen and CodeGen.

unsigned const TargetRegisterInfo * TRI

This file defines the PointerUnion class, which is a discriminated union of pointer types.

Remove Loads Into Fake Uses

assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

This file defines the SmallPtrSet class.

This file defines the SmallVector class.

StringSet - A set-like wrapper for the StringMap.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

bool test(unsigned Idx) const

This class represents an Operation in the Expression.

StorageT::size_type size() const

bool inBounds(IndexT n) const

MCRegAliasIterator enumerates all registers aliasing Reg.

Wrapper class representing physical registers. Should be passed by value.

constexpr unsigned id() const

Instructions::iterator instr_iterator

bool hasProperty(Property P) const

MachineFunctionProperties & reset(Property P)

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

const MachineFunctionProperties & getProperties() const

Get the function properties.

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

virtual void MRI_NoteNewVirtualRegister(Register Reg)=0

virtual void MRI_NoteCloneVirtualRegister(Register NewReg, Register SrcReg)

virtual ~Delegate()=default

defusechain_iterator - This class provides iterator support for machine operands in the function that...

MachineInstr & operator*() const

std::ptrdiff_t difference_type

std::forward_iterator_tag iterator_category

defusechain_instr_iterator()=default

bool operator==(const defusechain_instr_iterator &x) const

MachineInstr * operator->() const

bool operator!=(const defusechain_instr_iterator &x) const

defusechain_instr_iterator & operator++()

defusechain_instr_iterator operator++(int)

reg_begin/reg_end - Provide iteration support to walk over all definitions and uses of a register wit...

bool operator==(const defusechain_iterator &x) const

defusechain_iterator operator++(int)

MachineOperand & operator*() const

unsigned getOperandNo() const

getOperandNo - Return the operand # of this MachineOperand in its MachineInstr.

defusechain_iterator & operator++()

defusechain_iterator()=default

std::ptrdiff_t difference_type

bool operator!=(const defusechain_iterator &x) const

std::forward_iterator_tag iterator_category

MachineOperand * operator->() const

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

defusechain_instr_iterator< false, true, false, false, false, true > def_bundle_iterator

def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the specified register,...

void verifyUseList(Register Reg) const

Verify the sanity of the use list for Reg.

bool hasOneNonDBGUse(Register RegNo) const

hasOneNonDBGUse - Return true if there is exactly one non-Debug use of the specified register.

getSimpleHint - same as getRegAllocationHint except it will only return a target independent hint.

use_nodbg_iterator use_nodbg_begin(Register RegNo) const

defusechain_instr_iterator< true, true, true, false, false, true > reg_bundle_nodbg_iterator

reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk all defs and uses of the...

reg_nodbg_iterator reg_nodbg_begin(Register RegNo) const

void insertVRegByName(StringRef Name, Register Reg)

iterator_range< reg_bundle_iterator > reg_bundles(Register Reg) const

void verifyUseLists() const

Verify the use list of all registers.

bool livein_empty() const

VRegAttrs getVRegAttrs(Register Reg) const

Returns register class or bank and low level type of Reg.

static reg_iterator reg_end()

defusechain_instr_iterator< false, true, false, false, true, false > def_instr_iterator

def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the specified register,...

void markUsesInDebugValueAsUndef(Register Reg) const

markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the specified register as undefined wh...

bool tracksLiveness() const

tracksLiveness - Returns true when tracking register liveness accurately.

const BitVector & getUsedPhysRegsMask() const

iterator_range< reg_iterator > reg_operands(Register Reg) const

bool recomputeRegClass(Register Reg)

recomputeRegClass - Try to find a legal super-class of Reg's register class that still satisfies the ...

static reg_instr_nodbg_iterator reg_instr_nodbg_end()

reg_instr_iterator reg_instr_begin(Register RegNo) const

MachineRegisterInfo & operator=(const MachineRegisterInfo &)=delete

bool isUpdatedCSRsInitialized() const

Returns true if the updated CSR list was initialized and false otherwise.

void freezeReservedRegs()

freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...

const TargetRegisterClass * getRegClass(Register Reg) const

Return the register class of the specified virtual register.

static use_nodbg_iterator use_nodbg_end()

defusechain_instr_iterator< true, true, true, false, true, false > reg_instr_nodbg_iterator

reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk all defs and uses of the sp...

reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(Register RegNo) const

void clearKillFlags(Register Reg) const

clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...

MachineRegisterInfo(MachineFunction *MF)

reg_iterator reg_begin(Register RegNo) const

MachineInstr * getVRegDef(Register Reg) const

getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...

iterator_range< def_instr_iterator > def_instructions(Register Reg) const

bool shouldTrackSubRegLiveness(Register VReg) const

iterator_range< use_nodbg_iterator > use_nodbg_operands(Register Reg) const

void EmitLiveInCopies(MachineBasicBlock *EntryMBB, const TargetRegisterInfo &TRI, const TargetInstrInfo &TII)

EmitLiveInCopies - Emit copies to initialize livein virtual registers into the given entry block.

static reg_instr_iterator reg_instr_end()

use_instr_iterator use_instr_begin(Register RegNo) const

bool subRegLivenessEnabled() const

bool use_nodbg_empty(Register RegNo) const

use_nodbg_empty - Return true if there are no non-Debug instructions using the specified register.

const RegClassOrRegBank & getRegClassOrRegBank(Register Reg) const

Return the register bank or register class of Reg.

iterator_range< reg_bundle_nodbg_iterator > reg_nodbg_bundles(Register Reg) const

bool isReserved(MCRegister PhysReg) const

isReserved - Returns true when PhysReg is a reserved register.

static def_instr_iterator def_instr_end()

void dumpUses(Register RegNo) const

void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps)

Move NumOps operands from Src to Dst, updating use-def lists as needed.

MachineOperand * getOneDef(Register Reg) const

Returns the defining operand if there is exactly one operand defining the specified register,...

def_iterator def_begin(Register RegNo) const

static def_bundle_iterator def_bundle_end()

const BitVector & getReservedRegs() const

getReservedRegs - Returns a reference to the frozen set of reserved registers.

iterator_range< use_bundle_nodbg_iterator > use_nodbg_bundles(Register Reg) const

void setRegClassOrRegBank(Register Reg, const RegClassOrRegBank &RCOrRB)

defusechain_iterator< false, true, false, true, false, false > def_iterator

def_iterator/def_begin/def_end - Walk all defs of the specified register.

createVirtualRegister - Create and return a new virtual register in the function with the specified r...

def_instr_iterator def_instr_begin(Register RegNo) const

LLT getType(Register Reg) const

Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.

bool reservedRegsFrozen() const

reservedRegsFrozen - Returns true after freezeReservedRegs() was called to ensure the set of reserved...

bool def_empty(Register RegNo) const

def_empty - Return true if there are no instructions defining the specified register (it may be live-...

bool hasOneUse(Register RegNo) const

hasOneUse - Return true if there is exactly one instruction using the specified register.

void resetDelegate(Delegate *delegate)

bool isLiveIn(Register Reg) const

bool reg_nodbg_empty(Register RegNo) const

reg_nodbg_empty - Return true if the only instructions using or defining Reg are Debug instructions.

defusechain_iterator< true, false, false, true, false, false > use_iterator

use_iterator/use_begin/use_end - Walk all uses of the specified register.

static use_bundle_iterator use_bundle_end()

defusechain_instr_iterator< true, false, false, false, false, true > use_bundle_iterator

use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the specified register,...

const RegisterBank * getRegBankOrNull(Register Reg) const

Return the register bank of Reg, or null if Reg has not been assigned a register bank or has been ass...

void invalidateLiveness()

invalidateLiveness - Indicates that register liveness is no longer being tracked accurately.

static reg_nodbg_iterator reg_nodbg_end()

use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const

ArrayRef< std::pair< MCRegister, Register > > liveins() const

use_bundle_nodbg_iterator use_bundle_nodbg_begin(Register RegNo) const

defusechain_instr_iterator< true, false, true, false, false, true > use_bundle_nodbg_iterator

use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk all uses of the specifie...

defusechain_instr_iterator< true, true, false, false, false, true > reg_bundle_iterator

reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses of the specified registe...

bool hasAtMostUserInstrs(Register Reg, unsigned MaxUsers) const

hasAtMostUses - Return true if the given register has at most MaxUsers non-debug user instructions.

static use_instr_iterator use_instr_end()

bool hasOneNonDBGUser(Register RegNo) const

hasOneNonDBGUse - Return true if there is exactly one non-Debug instruction using the specified regis...

void clearVirtRegs()

clearVirtRegs - Remove all virtual registers (after physreg assignment).

std::vector< std::pair< MCRegister, Register > >::const_iterator livein_iterator

Creates a new virtual register that has no register class, register bank or size assigned yet.

bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const

Returns true if liveness for register class RC should be tracked at the subregister level.

bool isAllocatable(MCRegister PhysReg) const

isAllocatable - Returns true when PhysReg belongs to an allocatable register class and it hasn't been...

void setRegBank(Register Reg, const RegisterBank &RegBank)

Set the register bank to RegBank for Reg.

MCRegister getLiveInPhysReg(Register VReg) const

getLiveInPhysReg - If VReg is a live-in virtual register, return the corresponding live-in physical r...

const MCPhysReg * getCalleeSavedRegs() const

Returns list of callee saved registers.

std::pair< unsigned, Register > getRegAllocationHint(Register VReg) const

getRegAllocationHint - Return the register allocation hint for the specified virtual register.

iterator_range< use_instr_nodbg_iterator > use_nodbg_instructions(Register Reg) const

iterator_range< def_iterator > def_operands(Register Reg) const

void setType(Register VReg, LLT Ty)

Set the low-level type of VReg to Ty.

void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg)

setRegAllocationHint - Specify a register allocation hint for the specified virtual register.

void addDelegate(Delegate *delegate)

const MachineFunction & getMF() const

bool hasOneDef(Register RegNo) const

Return true if there is exactly one operand defining the specified register.

static reg_bundle_nodbg_iterator reg_bundle_nodbg_end()

void setRegClass(Register Reg, const TargetRegisterClass *RC)

setRegClass - Set the register class of the specified virtual register.

Create and return a new generic virtual register with low-level type Ty.

bool canReserveReg(MCRegister PhysReg) const

canReserveReg - Returns true if PhysReg can be used as a reserved register.

void clearVirtRegTypes()

Remove all types associated to virtual registers (after instruction selection and constraining of all...

defusechain_iterator< true, true, false, true, false, false > reg_iterator

reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified register.

getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in virtual r...

defusechain_iterator< true, true, true, true, false, false > reg_nodbg_iterator

reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses of the specified register,...

const TargetRegisterClass * getRegClassOrNull(Register Reg) const

Return the register class of Reg, or null if Reg has not been assigned a register class yet.

void setSimpleHint(Register VReg, Register PrefReg)

Specify the preferred (target independent) register allocation hint for the specified virtual registe...

static def_iterator def_end()

void disableCalleeSavedRegister(MCRegister Reg)

Disables the register from the list of CSRs.

use_bundle_iterator use_bundle_begin(Register RegNo) const

livein_iterator livein_end() const

reg_bundle_iterator reg_bundle_begin(Register RegNo) const

iterator_range< reg_instr_iterator > reg_instructions(Register Reg) const

void noteNewVirtualRegister(Register Reg)

static use_bundle_nodbg_iterator use_bundle_nodbg_end()

const std::pair< unsigned, SmallVector< Register, 4 > > * getRegAllocationHints(Register VReg) const

getRegAllocationHints - Return a reference to the vector of all register allocation hints for VReg.

void setCalleeSavedRegs(ArrayRef< MCPhysReg > CSRs)

Sets the updated Callee Saved Registers list.

defusechain_instr_iterator< true, false, false, false, true, false > use_instr_iterator

use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the specified register,...

static reg_bundle_iterator reg_bundle_end()

iterator_range< use_instr_iterator > use_instructions(Register Reg) const

defusechain_iterator< true, false, true, true, false, false > use_nodbg_iterator

use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the specified register,...

void reserveReg(MCRegister PhysReg, const TargetRegisterInfo *TRI)

reserveReg – Mark a register as reserved so checks like isAllocatable will not suggest using it.

const TargetRegisterInfo * getTargetRegisterInfo() const

LaneBitmask getMaxLaneMaskForVReg(Register Reg) const

Returns a mask covering all bits that can appear in lane masks of subregisters of the virtual registe...

use_iterator use_begin(Register RegNo) const

void addRegAllocationHint(Register VReg, Register PrefReg)

addRegAllocationHint - Add a register allocation hint to the hints vector for VReg.

bool isConstantPhysReg(MCRegister PhysReg) const

Returns true if PhysReg is unallocatable and constant throughout the function.

iterator_range< reg_nodbg_iterator > reg_nodbg_operands(Register Reg) const

Create and return a new virtual register in the function with the same attributes as the given regist...

void addPhysRegsUsedFromRegMask(const uint32_t *RegMask)

addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.

MachineRegisterInfo(const MachineRegisterInfo &)=delete

defusechain_instr_iterator< true, false, true, false, true, false > use_instr_nodbg_iterator

use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk all uses of the specified r...

static use_iterator use_end()

void addLiveIn(MCRegister Reg, Register vreg=Register())

addLiveIn - Add the specified register as a live-in.

PSetIterator getPressureSets(Register RegUnit) const

Get an iterator over the pressure sets affected by the given physical or virtual register.

bool constrainRegAttrs(Register Reg, Register ConstrainingReg, unsigned MinNumRegs=0)

Constrain the register class or the register bank of the virtual register Reg (and low-level type) to...

iterator_range< def_bundle_iterator > def_bundles(Register Reg) const

const TargetRegisterClass * constrainRegClass(Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs=0)

constrainRegClass - Constrain the register class of the specified virtual register to be a common sub...

void clearSimpleHint(Register VReg)

bool isReservedRegUnit(unsigned Unit) const

Returns true when the given register unit is considered reserved.

void noteCloneVirtualRegister(Register NewReg, Register SrcReg)

iterator_range< use_iterator > use_operands(Register Reg) const

livein_iterator livein_begin() const

reg_instr_nodbg_iterator reg_instr_nodbg_begin(Register RegNo) const

unsigned getNumVirtRegs() const

getNumVirtRegs - Return the number of virtual registers created.

iterator_range< reg_instr_nodbg_iterator > reg_nodbg_instructions(Register Reg) const

void removeRegOperandFromUseList(MachineOperand *MO)

Remove MO from its use-def list.

bool use_empty(Register RegNo) const

use_empty - Return true if there are no instructions using the specified register.

bool reg_empty(Register RegNo) const

reg_empty - Return true if there are no instructions using or defining the specified register (it may...

StringRef getVRegName(Register Reg) const

defusechain_instr_iterator< true, true, false, false, true, false > reg_instr_iterator

reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses of the specified register,...

iterator_range< use_bundle_iterator > use_bundles(Register Reg) const

void replaceRegWith(Register FromReg, Register ToReg)

replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.

bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef=false) const

Return true if the specified register is modified in this function.

void updateDbgUsersToReg(MCRegister OldReg, MCRegister NewReg, ArrayRef< MachineInstr * > Users) const

updateDbgUsersToReg - Update a collection of debug instructions to refer to the designated register.

void addRegOperandToUseList(MachineOperand *MO)

Add MO to the linked list of operands for its register.

MachineInstr * getUniqueVRegDef(Register Reg) const

getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...

def_bundle_iterator def_bundle_begin(Register RegNo) const

static use_instr_nodbg_iterator use_instr_nodbg_end()

bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest=false) const

Return true if the specified register is modified or read in this function.

Iterate over the pressure sets affected by the given physical or virtual register.

unsigned operator*() const

PSetIterator(Register RegUnit, const MachineRegisterInfo *MRI)

unsigned getWeight() const

This class implements the register bank concept.

Wrapper class representing virtual and physical registers.

static Register index2VirtReg(unsigned Index)

Convert a 0-based index to a virtual register number.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

constexpr unsigned id() const

bool erase(PtrType Ptr)

Remove pointer from the set.

size_type count(ConstPtrType Ptr) const

count - Return 1 if the specified pointer is in the set, 0 otherwise.

std::pair< iterator, bool > insert(PtrType Ptr)

Inserts Ptr if and only if there is no element in the container equal to Ptr.

SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StringRef - Represent a constant reference to a string, i.e.

StringSet - A wrapper for StringMap that provides set-like functionality.

bool contains(StringRef key) const

Check if the set contains the given key.

std::pair< typename Base::iterator, bool > insert(StringRef key)

TargetInstrInfo - Interface to description of machine instruction set.

const bool HasDisjunctSubRegs

Whether the class supports two (or more) disjunct subregister indices.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

bool regsOverlap(Register RegA, Register RegB) const

Returns true if the two registers are equal or alias each other.

bool isInAllocatableClass(MCRegister RegNo) const

Return true if the register is in the allocation of any register class.

virtual const TargetRegisterInfo * getRegisterInfo() const

getRegisterInfo - If register information is available, return it.

The instances of the Type class are immutable: once they are created, they are never changed.

A range adaptor for a pair of iterators.

This provides a very simple, boring adaptor for a begin and end iterator into a range type.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

This is an optimization pass for GlobalISel generic memory operations.

MachineBasicBlock::instr_iterator getBundleStart(MachineBasicBlock::instr_iterator I)

Returns an iterator to the first instruction in the bundle containing I.

iterator_range< T > make_range(T x, T y)

Convenience function for iterating over sub-ranges.

bool hasSingleElement(ContainerTy &&C)

Returns true if the given container only contains a single element.

DWARFExpression::Operation Op

All attributes(register class or bank and low-level type) a virtual register can have.