MipsInstrInfo.cpp Source File (original) (raw)

32#include

34using namespace llvm;

36#define GET_INSTRINFO_CTOR_DTOR

37#include "MipsGenInstrInfo.inc"

40void MipsInstrInfo::anchor() {}

55 return op.isImm() && op.getImm() == 0;

56}

78 "insertNop does not support MIPS16e mode at this time");

79 const unsigned MMOpc =

80 Subtarget.hasMips32r6() ? Mips::SLL_MMR6 : Mips::SLL_MM;

81 const unsigned Opc =

86}

100

101

102

103void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,

106 assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch");

108

109

110

113

114 for (int i = 0; i < NumOp-1; i++)

116}

117

122 bool AllowModify) const {

125

127}

128

132 unsigned Opc = Cond[0].getImm();

135

136 for (unsigned i = 1; i < Cond.size(); ++i) {

138 "Cannot copy operand for conditional branch!");

140 }

142}

143

149 int *BytesAdded) const {

150

151 assert(TBB && "insertBranch must not be told to insert a fallthrough");

152 assert(!BytesAdded && "code size not handled");

153

154

155

156

157

158

160 "# of Mips branch conditions must be <= 3!");

161

162

163 if (FBB) {

166 return 2;

167 }

168

169

170

171 if (Cond.empty())

173 else

175 return 1;

176}

177

179 int *BytesRemoved) const {

180 assert(!BytesRemoved && "code size not handled");

181

183 unsigned removed = 0;

184

185

186

187 while (I != REnd && removed < 2) {

188

189 if (I->isDebugInstr()) {

190 ++I;

191 continue;

192 }

193 if (!getAnalyzableBrOpc(I->getOpcode()))

194 break;

195

196 I->eraseFromParent();

197 I = MBB.rbegin();

198 ++removed;

199 }

200

201 return removed;

202}

203

204

205

209 "Invalid Mips branch condition!");

211 return false;

212}

213

219

220

221 while (I != REnd && I->isDebugInstr())

222 ++I;

223

224 if (I == REnd || !isUnpredicatedTerminator(*I)) {

225

226

227 TBB = FBB = nullptr;

229 }

230

232 unsigned LastOpc = LastInst->getOpcode();

233 BranchInstrs.push_back(LastInst);

234

235

236 if (!getAnalyzableBrOpc(LastOpc))

238

239

240 unsigned SecondLastOpc = 0;

242

243

244

245 ++I;

246 while (I != REnd && I->isDebugInstr())

247 ++I;

248

249 if (I != REnd) {

250 SecondLastInst = &*I;

251 SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->getOpcode());

252

253

254 if (isUnpredicatedTerminator(*SecondLastInst) && !SecondLastOpc)

256 }

257

258

259 if (!SecondLastOpc) {

260

264 }

265

266

267 AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);

269 }

270

271

272

273 if (++I != REnd && isUnpredicatedTerminator(*I))

275

276 BranchInstrs.insert(BranchInstrs.begin(), SecondLastInst);

277

278

279

281

282 if (!AllowModify)

284

289 }

290

291

292

295

296 AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);

298

300}

301

303 int64_t BrOffset) const {

304 switch (BranchOpc) {

305 case Mips::B:

306 case Mips::BAL:

307 case Mips::BAL_BR:

308 case Mips::BAL_BR_MM:

309 case Mips::BC1F:

310 case Mips::BC1FL:

311 case Mips::BC1T:

312 case Mips::BC1TL:

313 case Mips::BEQ: case Mips::BEQ64:

314 case Mips::BEQL:

315 case Mips::BGEZ: case Mips::BGEZ64:

316 case Mips::BGEZL:

317 case Mips::BGEZAL:

318 case Mips::BGEZALL:

319 case Mips::BGTZ: case Mips::BGTZ64:

320 case Mips::BGTZL:

321 case Mips::BLEZ: case Mips::BLEZ64:

322 case Mips::BLEZL:

323 case Mips::BLTZ: case Mips::BLTZ64:

324 case Mips::BLTZL:

325 case Mips::BLTZAL:

326 case Mips::BLTZALL:

327 case Mips::BNE: case Mips::BNE64:

328 case Mips::BNEL:

330

331

332 case Mips::B_MM:

333 case Mips::BC1F_MM:

334 case Mips::BC1T_MM:

335 case Mips::BEQ_MM:

336 case Mips::BGEZ_MM:

337 case Mips::BGEZAL_MM:

338 case Mips::BGTZ_MM:

339 case Mips::BLEZ_MM:

340 case Mips::BLTZ_MM:

341 case Mips::BLTZAL_MM:

342 case Mips::BNE_MM:

343 case Mips::BEQZC_MM:

344 case Mips::BNEZC_MM:

346

347

348 case Mips::B16_MM:

350

351 case Mips::BEQZ16_MM:

352 case Mips::BNEZ16_MM:

354

355

356 case Mips::BALC:

357 case Mips::BC:

359

360 case Mips::BC1EQZ:

361 case Mips::BC1NEZ:

362 case Mips::BC2EQZ:

363 case Mips::BC2NEZ:

364 case Mips::BEQC: case Mips::BEQC64:

365 case Mips::BNEC: case Mips::BNEC64:

366 case Mips::BGEC: case Mips::BGEC64:

367 case Mips::BGEUC: case Mips::BGEUC64:

368 case Mips::BGEZC: case Mips::BGEZC64:

369 case Mips::BGTZC: case Mips::BGTZC64:

370 case Mips::BLEZC: case Mips::BLEZC64:

371 case Mips::BLTC: case Mips::BLTC64:

372 case Mips::BLTUC: case Mips::BLTUC64:

373 case Mips::BLTZC: case Mips::BLTZC64:

374 case Mips::BNVC:

375 case Mips::BOVC:

376 case Mips::BGEZALC:

377 case Mips::BEQZALC:

378 case Mips::BGTZALC:

379 case Mips::BLEZALC:

380 case Mips::BLTZALC:

381 case Mips::BNEZALC:

383

384 case Mips::BEQZC: case Mips::BEQZC64:

385 case Mips::BNEZC: case Mips::BNEZC64:

387

388

389 case Mips::BC16_MMR6:

391

392 case Mips::BEQZC16_MMR6:

393 case Mips::BNEZC16_MMR6:

395

396 case Mips::BALC_MMR6:

397 case Mips::BC_MMR6:

399

400 case Mips::BC1EQZC_MMR6:

401 case Mips::BC1NEZC_MMR6:

402 case Mips::BC2EQZC_MMR6:

403 case Mips::BC2NEZC_MMR6:

404 case Mips::BGEZALC_MMR6:

405 case Mips::BEQZALC_MMR6:

406 case Mips::BGTZALC_MMR6:

407 case Mips::BLEZALC_MMR6:

408 case Mips::BLTZALC_MMR6:

409 case Mips::BNEZALC_MMR6:

410 case Mips::BNVC_MMR6:

411 case Mips::BOVC_MMR6:

413

414 case Mips::BEQC_MMR6:

415 case Mips::BNEC_MMR6:

416 case Mips::BGEC_MMR6:

417 case Mips::BGEUC_MMR6:

418 case Mips::BGEZC_MMR6:

419 case Mips::BGTZC_MMR6:

420 case Mips::BLEZC_MMR6:

421 case Mips::BLTC_MMR6:

422 case Mips::BLTUC_MMR6:

423 case Mips::BLTZC_MMR6:

425

426 case Mips::BEQZC_MMR6:

427 case Mips::BNEZC_MMR6:

429

430

431 case Mips::BPOSGE32:

433 case Mips::BPOSGE32_MM:

434 case Mips::BPOSGE32C_MMR3:

436

437

438 case Mips::BBIT0:

439 case Mips::BBIT032:

440 case Mips::BBIT1:

441 case Mips::BBIT132:

443

444

445 case Mips::BZ_B:

446 case Mips::BZ_H:

447 case Mips::BZ_W:

448 case Mips::BZ_D:

449 case Mips::BZ_V:

450 case Mips::BNZ_B:

451 case Mips::BNZ_H:

452 case Mips::BNZ_W:

453 case Mips::BNZ_D:

454 case Mips::BNZ_V:

456 }

457

459}

460

461

464 unsigned Opcode = I->getOpcode();

465 bool canUseShortMicroMipsCTI = false;

466

467 if (Subtarget.inMicroMipsMode()) {

468 switch (Opcode) {

469 case Mips::BNE:

470 case Mips::BNE_MM:

471 case Mips::BEQ:

472 case Mips::BEQ_MM:

473

474

475 if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg())

476 canUseShortMicroMipsCTI = true;

477 break;

478

479

480 case Mips::JR:

481 case Mips::PseudoReturn:

482 case Mips::PseudoIndirectBranch:

483 canUseShortMicroMipsCTI = true;

484 break;

485 }

486 }

487

488

489 if (Subtarget.hasMips32r6() && (I->getNumOperands() > 1) &&

490 (I->getOperand(0).isReg() &&

491 (I->getOperand(0).getReg() == Mips::ZERO ||

492 I->getOperand(0).getReg() == Mips::ZERO_64)) &&

493 (I->getOperand(1).isReg() &&

494 (I->getOperand(1).getReg() == Mips::ZERO ||

495 I->getOperand(1).getReg() == Mips::ZERO_64)))

496 return 0;

497

498 if (Subtarget.hasMips32r6() || canUseShortMicroMipsCTI) {

499 switch (Opcode) {

500 case Mips::B:

501 return Mips::BC;

502 case Mips::BAL:

503 return Mips::BALC;

504 case Mips::BEQ:

505 case Mips::BEQ_MM:

506 if (canUseShortMicroMipsCTI)

507 return Mips::BEQZC_MM;

508 else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())

509 return 0;

510 return Mips::BEQC;

511 case Mips::BNE:

512 case Mips::BNE_MM:

513 if (canUseShortMicroMipsCTI)

514 return Mips::BNEZC_MM;

515 else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())

516 return 0;

517 return Mips::BNEC;

518 case Mips::BGE:

519 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())

520 return 0;

521 return Mips::BGEC;

522 case Mips::BGEU:

523 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())

524 return 0;

525 return Mips::BGEUC;

526 case Mips::BGEZ:

527 return Mips::BGEZC;

528 case Mips::BGTZ:

529 return Mips::BGTZC;

530 case Mips::BLEZ:

531 return Mips::BLEZC;

532 case Mips::BLT:

533 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())

534 return 0;

535 return Mips::BLTC;

536 case Mips::BLTU:

537 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())

538 return 0;

539 return Mips::BLTUC;

540 case Mips::BLTZ:

541 return Mips::BLTZC;

542 case Mips::BEQ64:

543 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())

544 return 0;

545 return Mips::BEQC64;

546 case Mips::BNE64:

547 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())

548 return 0;

549 return Mips::BNEC64;

550 case Mips::BGTZ64:

551 return Mips::BGTZC64;

552 case Mips::BGEZ64:

553 return Mips::BGEZC64;

554 case Mips::BLTZ64:

555 return Mips::BLTZC64;

556 case Mips::BLEZ64:

557 return Mips::BLEZC64;

558

559

560 case Mips::JR:

561 case Mips::PseudoIndirectBranchR6:

562 case Mips::PseudoReturn:

563 case Mips::TAILCALLR6REG:

564 if (canUseShortMicroMipsCTI)

565 return Mips::JRC16_MM;

566 return Mips::JIC;

567 case Mips::JALRPseudo:

568 return Mips::JIALC;

569 case Mips::JR64:

570 case Mips::PseudoIndirectBranch64R6:

571 case Mips::PseudoReturn64:

572 case Mips::TAILCALL64R6REG:

573 return Mips::JIC64;

574 case Mips::JALR64Pseudo:

575 return Mips::JIALC64;

576 default:

577 return 0;

578 }

579 }

580

581 return 0;

582}

583

586 return false;

587

588 return true;

589}

590

591

592

593

595 if (MI.isInlineAsm())

596 return false;

597

599}

600

604 return false;

605

607 return false;

608

610 case Mips::BC1F:

611 case Mips::BC1FL:

612 case Mips::BC1T:

613 case Mips::BC1TL:

614 return false;

615 }

616

618 if (.isReg())

619 continue;

620

621 bool Reads, Writes;

623

624 if (Reads || Writes)

625 return false;

626 }

627

628 return true;

629}

630

631

632

636 return false;

637

639 return Op.isReg() && MIInSlot.readsRegister(Op.getReg(), nullptr);

640 });

641}

642

645 return true;

646

647 return false;

648}

649

650

654

655

657 switch (MI.getOpcode()) {

658 case Mips::MTC1:

659 case Mips::MFC1:

660 case Mips::MTC1_D64:

661 case Mips::MFC1_D64:

662 case Mips::DMTC1:

663 case Mips::DMFC1:

664 case Mips::FCMP_S32:

665 case Mips::FCMP_D32:

666 case Mips::FCMP_D64:

667 return true;

668

669 default:

670 return false;

671 }

672}

673

674

676 switch (MI.getOpcode()) {

677 case Mips::LB:

678 case Mips::LBu:

679 case Mips::LH:

680 case Mips::LHu:

681 case Mips::LW:

682 case Mips::LWR:

683 case Mips::LWL:

684 return true;

685 default:

686 return false;

687 }

688}

689

691 const unsigned Opcode = MI.getOpcode();

692 switch (Opcode) {

693 default:

694 break;

695 case Mips::ADDiu:

696 case Mips::ADDiu_MM:

697 case Mips::DADDiu:

698 return ((MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) ||

699 (MI.getOperand(1).isReg() &&

700 (MI.getOperand(1).getReg() == Mips::ZERO ||

701 MI.getOperand(1).getReg() == Mips::ZERO_64)));

702 }

703 return MI.isAsCheapAsAMove();

704}

705

706

708 switch (MI.getOpcode()) {

709 default:

710 return MI.getDesc().getSize();

711 case TargetOpcode::INLINEASM:

712 case TargetOpcode::INLINEASM_BR: {

714 const char *AsmStr = MI.getOperand(0).getSymbolName();

716 }

717 case Mips::CONSTPOOL_ENTRY:

718

719

720 return MI.getOperand(2).getImm();

721 }

722}

723

728

729

730

731

732

733

734

735

736

737

738 int ZeroOperandPosition = -1;

739 bool BranchWithZeroOperand = false;

740 if (I->isBranch() && ->isPseudo()) {

741 auto TRI = I->getParent()->getParent()->getSubtarget().getRegisterInfo();

742 ZeroOperandPosition = I->findRegisterUseOperandIdx(Mips::ZERO, TRI, false);

743 BranchWithZeroOperand = ZeroOperandPosition != -1;

744 }

745

746 if (BranchWithZeroOperand) {

747 switch (NewOpc) {

748 case Mips::BEQC:

749 NewOpc = Mips::BEQZC;

750 break;

751 case Mips::BNEC:

752 NewOpc = Mips::BNEZC;

753 break;

754 case Mips::BGEC:

755 NewOpc = Mips::BGEZC;

756 break;

757 case Mips::BLTC:

758 NewOpc = Mips::BLTZC;

759 break;

760 case Mips::BEQC64:

761 NewOpc = Mips::BEQZC64;

762 break;

763 case Mips::BNEC64:

764 NewOpc = Mips::BNEZC64;

765 break;

766 }

767 }

768

769 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));

770

771

772

773

774

775 if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 ||

776 NewOpc == Mips::JIALC64) {

777

778 if (NewOpc == Mips::JIALC || NewOpc == Mips::JIALC64)

780

781 for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {

782 MIB.add(I->getOperand(J));

783 }

784

786

787

788

789 for (unsigned J = I->getDesc().getNumOperands(), E = I->getNumOperands();

790 J < E; ++J) {

794 }

795

796

797 } else {

798 for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) {

799 if (BranchWithZeroOperand && (unsigned)ZeroOperandPosition == J)

800 continue;

801

802 MIB.add(I->getOperand(J));

803 }

804 }

805

808 return MIB;

809}

810

812 unsigned &SrcOpIdx1,

813 unsigned &SrcOpIdx2) const {

815 "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");

816

818 if ( MCID .isCommutable())

819 return false;

820

821 switch (MI.getOpcode()) {

822 case Mips::DPADD_U_H:

823 case Mips::DPADD_U_W:

824 case Mips::DPADD_U_D:

825 case Mips::DPADD_S_H:

826 case Mips::DPADD_S_W:

827 case Mips::DPADD_S_D:

828

829 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3))

830 return false;

831

832 if (.getOperand(SrcOpIdx1).isReg() || .getOperand(SrcOpIdx2).isReg())

833 return false;

834 return true;

835 }

837}

838

839

840

841

842

843

844

845

846

847

848

849

850

851

852

854 const int64_t PosLow, const int64_t PosHigh,

855 const int64_t SizeLow,

856 const int64_t SizeHigh,

857 const int64_t BothLow,

858 const int64_t BothHigh) {

860 if (!MOPos.isImm()) {

861 ErrInfo = "Position is not an immediate!";

862 return false;

863 }

864 int64_t Pos = MOPos.getImm();

865 if (!((PosLow <= Pos) && (Pos < PosHigh))) {

866 ErrInfo = "Position operand is out of range!";

867 return false;

868 }

869

871 if (!MOSize.isImm()) {

872 ErrInfo = "Size operand is not an immediate!";

873 return false;

874 }

876 if (!((SizeLow < Size) && (Size <= SizeHigh))) {

877 ErrInfo = "Size operand is out of range!";

878 return false;

879 }

880

881 if (!((BothLow < (Pos + Size)) && ((Pos + Size) <= BothHigh))) {

882 ErrInfo = "Position + Size is out of range!";

883 return false;

884 }

885

886 return true;

887}

888

889

892

893 switch (MI.getOpcode()) {

894 case Mips::EXT:

895 case Mips::EXT_MM:

896 case Mips::INS:

897 case Mips::INS_MM:

898 case Mips::DINS:

900 case Mips::DINSM:

901

902

903

904

905

907 case Mips::DINSU:

908

909

910

911

913 case Mips::DEXT:

915 case Mips::DEXTM:

917 case Mips::DEXTU:

919 case Mips::TAILCALLREG:

920 case Mips::PseudoIndirectBranch:

921 case Mips::JR:

922 case Mips::JR64:

923 case Mips::JALR:

924 case Mips::JALR64:

925 case Mips::JALRPseudo:

926 if ( Subtarget .useIndirectJumpsHazard())

927 return true;

928

929 ErrInfo = "invalid instruction when using jump guards!";

930 return false;

931 default:

932 return true;

933 }

934

935 return true;

936}

937

938std::pair<unsigned, unsigned>

940 return std::make_pair(TF, 0u);

941}

942

945 using namespace MipsII;

946

947 static const std::pair<unsigned, const char*> Flags[] = {

948 {MO_GOT, "mips-got"},

949 {MO_GOT_CALL, "mips-got-call"},

950 {MO_GPREL, "mips-gprel"},

951 {MO_ABS_HI, "mips-abs-hi"},

952 {MO_ABS_LO, "mips-abs-lo"},

953 {MO_TLSGD, "mips-tlsgd"},

954 {MO_TLSLDM, "mips-tlsldm"},

955 {MO_DTPREL_HI, "mips-dtprel-hi"},

956 {MO_DTPREL_LO, "mips-dtprel-lo"},

957 {MO_GOTTPREL, "mips-gottprel"},

958 {MO_TPREL_HI, "mips-tprel-hi"},

959 {MO_TPREL_LO, "mips-tprel-lo"},

960 {MO_GPOFF_HI, "mips-gpoff-hi"},

961 {MO_GPOFF_LO, "mips-gpoff-lo"},

962 {MO_GOT_DISP, "mips-got-disp"},

963 {MO_GOT_PAGE, "mips-got-page"},

964 {MO_GOT_OFST, "mips-got-ofst"},

965 {MO_HIGHER, "mips-higher"},

966 {MO_HIGHEST, "mips-highest"},

967 {MO_GOT_HI16, "mips-got-hi16"},

968 {MO_GOT_LO16, "mips-got-lo16"},

969 {MO_CALL_HI16, "mips-call-hi16"},

970 {MO_CALL_LO16, "mips-call-lo16"},

971 {MO_JALR, "mips-jalr"}

972 };

974}

975

976std::optional

980

981

983 Register SrcReg = RegImm->Reg;

984 int64_t Offset = RegImm->Imm;

985

986

987 if (SrcReg == Mips::ZERO || SrcReg == Mips::ZERO_64) {

989 }

992 } else if (auto DestSrc = isCopyInstr(MI)) {

995 Register DestReg = DestSrc->Destination->getReg();

996

997

998 if (TRI->isSuperRegister(Reg, DestReg) || TRI->isSubRegister(Reg, DestReg))

999 return std::nullopt;

1000 }

1001

1003}

1004

1007

1008

1010 if (!Op0.isReg() || Reg != Op0.getReg())

1011 return std::nullopt;

1012

1013 switch (MI.getOpcode()) {

1014 case Mips::ADDiu:

1015 case Mips::DADDiu: {

1019

1020

1023

1024 }

1025 }

1026 return std::nullopt;

1027}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

static bool isReg(const MCInst &MI, unsigned OpNo)

static bool verifyInsExtInstruction(const MachineInstr &MI, StringRef &ErrInfo, const int64_t PosLow, const int64_t PosHigh, const int64_t SizeLow, const int64_t SizeHigh, const int64_t BothLow, const int64_t BothHigh)

Definition MipsInstrInfo.cpp:853

#define IsMFLOMFHI(instr)

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

This file defines the SmallVector class.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

static LLVM_ABI DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)

Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...

MCInstBuilder & addReg(MCRegister Reg)

Add a new register operand.

MCInstBuilder & addImm(int64_t Val)

Add a new integer immediate operand.

Instances of this class represent a single low-level machine instruction.

Describe properties that are true of each instruction in the target description file.

static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)

MachineInstrBundleIterator< MachineInstr, true > reverse_iterator

MachineInstrBundleIterator< MachineInstr > iterator

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

Align getObjectAlign(int ObjectIdx) const

Return the alignment of the specified stack object.

int64_t getObjectSize(int ObjectIdx) const

Return the size of the specified object.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)

getMachineMemOperand - Allocate a new MachineMemOperand.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

const TargetMachine & getTarget() const

getTarget - Return the target machine this machine code is compiled with

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & add(const MachineOperand &MO) const

const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const

const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const

const MachineInstrBuilder & copyImplicitOps(const MachineInstr &OtherMI) const

Copy all the implicit operands from OtherMI onto this one.

Representation of each machine instruction.

mop_range defs()

Returns all explicit operands that are register definitions.

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

LLVM_ABI std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const

Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.

LLVM_ABI unsigned getNumExplicitOperands() const

Returns the number of non-implicit operands.

bool isUnconditionalBranch(QueryType Type=AnyInBundle) const

Return true if this is a branch which always transfers control flow to some other block.

LLVM_ABI void eraseFromParent()

Unlink 'this' from the containing basic block and delete it.

LLVM_ABI void removeOperand(unsigned OpNo)

Erase an operand from an instruction, leaving it with one fewer operand than it started with.

const MachineOperand & getOperand(unsigned i) const

bool isIndirectBranch(QueryType Type=AnyInBundle) const

Return true if this is an indirect branch, such as a branch through a register.

A description of a memory reference used in the backend.

Flags

Flags values. These may be or'd together.

MachineOperand class - Representation of each machine instruction operand.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

MachineBasicBlock * getMBB() const

bool isImm() const

isImm - Tests if this is a MO_Immediate operand.

unsigned getTargetFlags() const

static MachineOperand CreateImm(int64_t Val)

getReg - Returns the register number.

MCSymbol * getMCSymbol() const

static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)

MCInst getNop() const override

Definition MipsInstrInfo.cpp:58

bool SafeAfterMflo(const MachineInstr &MI) const

Definition MipsInstrInfo.cpp:584

ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override

Definition MipsInstrInfo.cpp:944

bool SafeInForbiddenSlot(const MachineInstr &MI) const

Predicate to determine if an instruction can go in a forbidden slot.

Definition MipsInstrInfo.cpp:594

unsigned getInstSizeInBytes(const MachineInstr &MI) const override

Return the number of bytes of code the specified instruction may be.

Definition MipsInstrInfo.cpp:707

MachineInstrBuilder insertNop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL) const

Insert an ISA appropriate nop.

Definition MipsInstrInfo.cpp:74

bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const override

Determine if the branch target is in range.

Definition MipsInstrInfo.cpp:302

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override

Branch Analysis.

Definition MipsInstrInfo.cpp:118

const MipsSubtarget & Subtarget

MachineMemOperand * GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const

Definition MipsInstrInfo.cpp:89

MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc, MachineBasicBlock::iterator I) const

Create an instruction which has the same operands and memory operands as MI but has a new opcode.

Definition MipsInstrInfo.cpp:725

bool HasForbiddenSlot(const MachineInstr &MI) const

Predicate to determine if an instruction has a forbidden slot.

Definition MipsInstrInfo.cpp:651

bool SafeInFPUDelaySlot(const MachineInstr &MIInSlot, const MachineInstr &FPUMI) const

Predicate to determine if an instruction can go in an FPU delay slot.

Definition MipsInstrInfo.cpp:601

bool isZeroImm(const MachineOperand &op) const

Definition MipsInstrInfo.cpp:54

unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const

Determine the opcode of a non-delay slot form for a branch if one exists.

Definition MipsInstrInfo.cpp:462

bool SafeInLoadDelaySlot(const MachineInstr &MIInSlot, const MachineInstr &LoadMI) const

Predicate to determine if an instruction can go in a load delay slot.

Definition MipsInstrInfo.cpp:633

bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override

reverseBranchCondition - Return the inverse opcode of the specified Branch instruction.

Definition MipsInstrInfo.cpp:206

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

Definition MipsInstrInfo.cpp:144

std::optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const override

Definition MipsInstrInfo.cpp:1005

bool HasFPUDelaySlot(const MachineInstr &MI) const

Predicate to determine if an instruction has an FPU delay slot.

Definition MipsInstrInfo.cpp:656

bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override

Perform target specific instruction verification.

Definition MipsInstrInfo.cpp:890

std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override

Definition MipsInstrInfo.cpp:939

static const MipsInstrInfo * create(MipsSubtarget &STI)

Definition MipsInstrInfo.cpp:47

bool IsMfloOrMfhi(const MachineInstr &MI) const

Definition MipsInstrInfo.cpp:643

bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override

Definition MipsInstrInfo.cpp:811

std::optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override

Definition MipsInstrInfo.cpp:977

MipsInstrInfo(const MipsSubtarget &STI, const MipsRegisterInfo &RI, unsigned UncondBrOpc)

Definition MipsInstrInfo.cpp:42

virtual unsigned getOppositeBranchOpc(unsigned Opc) const =0

bool HasLoadDelaySlot(const MachineInstr &MI) const

Predicate to determine if an instruction has a load delay slot.

Definition MipsInstrInfo.cpp:675

bool isAsCheapAsAMove(const MachineInstr &MI) const override

Definition MipsInstrInfo.cpp:690

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

Definition MipsInstrInfo.cpp:178

void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override

Insert nop instruction when hazard condition is found.

Definition MipsInstrInfo.cpp:68

bool inMips16Mode() const

Wrapper class representing virtual and physical registers.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

iterator insert(iterator I, T &&Elt)

void push_back(const T &Elt)

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StringRef - Represent a constant reference to a string, i.e.

virtual bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const

Returns true iff the routine could find two commutable operands in the given machine instruction.

virtual std::optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const

Produce the expression describing the MI loading a value into the physical register Reg.

const MCAsmInfo * getMCAsmInfo() const

Return target specific asm information.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual const TargetRegisterInfo * getRegisterInfo() const =0

Return the target's register information.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

MipsII - This namespace holds all of the target specific flags that instruction info tracks.

This is an optimization pass for GlobalISel generic memory operations.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

constexpr bool isInt(int64_t x)

Checks if an integer fits into the given bit width.

const MipsInstrInfo * createMipsSEInstrInfo(const MipsSubtarget &STI)

bool any_of(R &&range, UnaryPredicate P)

Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.

MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)

decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)

DWARFExpression::Operation Op

ArrayRef(const T &OneElt) -> ArrayRef< T >

const MipsInstrInfo * createMips16InstrInfo(const MipsSubtarget &STI)

Create MipsInstrInfo objects.

std::pair< MachineOperand, DIExpression * > ParamLoadedValue

static LLVM_ABI MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)

Return a MachinePointerInfo record that refers to the specified FrameIndex.

Used to describe a register and immediate addition.