LLVM: llvm::MipsInstrInfo Class Reference (original) (raw)

#include "[Target/Mips/MipsInstrInfo.h](MipsInstrInfo%5F8h%5Fsource.html)"

Public Types
enum BranchType { BT_None, BT_NoBranch, BT_Uncond, BT_Cond, BT_CondUncond, BT_Indirect }
Public Member Functions
MipsInstrInfo (const MipsSubtarget &STI, const MipsRegisterInfo &RI, unsigned UncondBrOpc)
MCInst getNop () const override
bool analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Branch Analysis.
unsigned removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
bool reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
reverseBranchCondition - Return the inverse opcode of the specified Branch instruction.
BranchType analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify, SmallVectorImpl< MachineInstr * > &BranchInstrs) const
unsigned getEquivalentCompactForm (const MachineBasicBlock::iterator I) const
Determine the opcode of a non-delay slot form for a branch if one exists.
bool isBranchOffsetInRange (unsigned BranchOpc, int64_t BrOffset) const override
Determine if the branch target is in range.
bool SafeAfterMflo (const MachineInstr &MI) const
bool SafeInForbiddenSlot (const MachineInstr &MI) const
Predicate to determine if an instruction can go in a forbidden slot.
bool SafeInFPUDelaySlot (const MachineInstr &MIInSlot, const MachineInstr &FPUMI) const
Predicate to determine if an instruction can go in an FPU delay slot.
bool SafeInLoadDelaySlot (const MachineInstr &MIInSlot, const MachineInstr &LoadMI) const
Predicate to determine if an instruction can go in a load delay slot.
bool IsMfloOrMfhi (const MachineInstr &MI) const
bool HasForbiddenSlot (const MachineInstr &MI) const
Predicate to determine if an instruction has a forbidden slot.
bool HasFPUDelaySlot (const MachineInstr &MI) const
Predicate to determine if an instruction has an FPU delay slot.
bool HasLoadDelaySlot (const MachineInstr &MI) const
Predicate to determine if an instruction has a load delay slot.
bool isAsCheapAsAMove (const MachineInstr &MI) const override
void insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
Insert nop instruction when hazard condition is found.
MachineInstrBuilder insertNop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL) const
Insert an ISA appropriate nop.
const MipsRegisterInfo & getRegisterInfo () const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
virtual unsigned getOppositeBranchOpc (unsigned Opc) const =0
virtual bool isBranchWithImm (unsigned Opc) const
unsigned getInstSizeInBytes (const MachineInstr &MI) const override
Return the number of bytes of code the specified instruction may be.
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
virtual void storeRegToStack (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, int64_t Offset, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const =0
virtual void loadRegFromStack (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, int64_t Offset, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const =0
virtual void adjustStackPtr (unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const =0
MachineInstrBuilder genInstrWithNewOpc (unsigned NewOpc, MachineBasicBlock::iterator I) const
Create an instruction which has the same operands and memory operands as MI but has a new opcode.
bool findCommutedOpIndices (const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
bool verifyInstruction (const MachineInstr &MI, StringRef &ErrInfo) const override
Perform target specific instruction verification.
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags (unsigned TF) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags () const override
std::optional< RegImmPair > isAddImmediate (const MachineInstr &MI, Register Reg) const override
std::optional< ParamLoadedValue > describeLoadedValue (const MachineInstr &MI, Register Reg) const override

Definition at line 41 of file MipsInstrInfo.h.

◆ BranchType

Enumerator
BT_None
BT_NoBranch
BT_Uncond
BT_Cond
BT_CondUncond
BT_Indirect

Definition at line 49 of file MipsInstrInfo.h.

◆ adjustStackPtr()

◆ analyzeBranch() [1/2]

◆ analyzeBranch() [2/2]

Definition at line 214 of file MipsInstrInfo.cpp.

References llvm::SmallVectorTemplateCommon< T, typename >::begin(), BT_Cond, BT_CondUncond, BT_Indirect, BT_NoBranch, BT_None, BT_Uncond, Cond, llvm::MachineInstr::eraseFromParent(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, llvm::SmallVectorImpl< T >::insert(), llvm::MachineInstr::isIndirectBranch(), llvm::MachineInstr::isUnconditionalBranch(), MBB, llvm::SmallVectorTemplateBase< T, bool >::pop_back(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TBB.

◆ create()

◆ decomposeMachineOperandsTargetFlags()

◆ describeLoadedValue()

Definition at line 977 of file MipsInstrInfo.cpp.

References llvm::DIExpression::ApplyOffset, llvm::MachineOperand::CreateReg(), llvm::TargetInstrInfo::describeLoadedValue(), llvm::MDNode::get(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), isAddImmediate(), MI, llvm::Offset, llvm::DIExpression::prepend(), and TRI.

◆ findCommutedOpIndices()

◆ genInstrWithNewOpc()

Create an instruction which has the same operands and memory operands as MI but has a new opcode.

Definition at line 725 of file MipsInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addSym(), llvm::BuildMI(), llvm::MachineInstrBuilder::cloneMemRefs(), llvm::MachineInstrBuilder::copyImplicitOps(), llvm::get(), llvm::MachineOperand::getMCSymbol(), llvm::MachineOperand::getTargetFlags(), I, llvm::MachineOperand::isMCSymbol(), llvm::MipsII::MO_JALR, llvm::MachineInstr::removeOperand(), and TRI.

◆ getEquivalentCompactForm()

Determine the opcode of a non-delay slot form for a branch if one exists.

Return the corresponding compact (no delay slot) form of a branch.

Definition at line 462 of file MipsInstrInfo.cpp.

References I, and Subtarget.

◆ getInstSizeInBytes()

◆ GetMemOperand()

◆ getNop()

MCInst MipsInstrInfo::getNop ( ) const override

◆ getOppositeBranchOpc()

virtual unsigned llvm::MipsInstrInfo::getOppositeBranchOpc ( unsigned Opc) const pure virtual

◆ getRegisterInfo()

◆ getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > MipsInstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const override

◆ HasForbiddenSlot()

◆ HasFPUDelaySlot()

◆ HasLoadDelaySlot()

◆ insertBranch()

◆ insertNoop()

◆ insertNop()

◆ isAddImmediate()

◆ isAsCheapAsAMove()

◆ isBranchOffsetInRange()

bool MipsInstrInfo::isBranchOffsetInRange ( unsigned BranchOpc, int64_t BrOffset ) const override

◆ isBranchWithImm()

virtual bool llvm::MipsInstrInfo::isBranchWithImm ( unsigned Opc) const inlinevirtual

◆ IsMfloOrMfhi()

◆ isZeroImm()

◆ loadRegFromStack()

◆ loadRegFromStackSlot()

◆ removeBranch()

◆ reverseBranchCondition()

◆ SafeAfterMflo()

◆ SafeInForbiddenSlot()

Predicate to determine if an instruction can go in a forbidden slot.

Predicate for distingushing between control transfer instructions and all other instructions for handling forbidden slots.

Consider inline assembly as unsafe as well.

Definition at line 594 of file MipsInstrInfo.cpp.

References llvm::MipsII::IsCTI, and MI.

◆ SafeInFPUDelaySlot()

◆ SafeInLoadDelaySlot()

◆ storeRegToStack()

◆ storeRegToStackSlot()

◆ verifyInstruction()

◆ Subtarget

◆ UncondBrOpc

unsigned llvm::MipsInstrInfo::UncondBrOpc protected

The documentation for this class was generated from the following files: