MipsRegisterBankInfo.cpp Source File (original) (raw)

21#define GET_TARGET_REGBANK_IMPL

23#include "MipsGenRegisterBank.inc"

25namespace llvm {

26namespace Mips {

36 {0, 32, GPRBRegBank},

37 {0, 32, FPRBRegBank},

38 {0, 64, FPRBRegBank},

39 {0, 128, FPRBRegBank}

40};

52 {nullptr, 0},

69};

71}

72}

74using namespace llvm;

81 switch (Opc) {

82 case TargetOpcode::G_FPTOSI:

83 case TargetOpcode::G_FPTOUI:

84 case TargetOpcode::G_FCMP:

85 return true;

86 default:

88 }

89}

94 switch (Opc) {

95 case TargetOpcode::G_SITOFP:

96 case TargetOpcode::G_UITOFP:

97 return true;

98 default:

100 }

101}

102

104 if (MI->getOpcode() == TargetOpcode::G_LOAD ||

105 MI->getOpcode() == TargetOpcode::G_STORE) {

106 auto MMO = *MI->memoperands_begin();

109 (!MMO->getSize().hasValue() ||

110 MMO->getAlign() < MMO->getSize().getValue())))

111 return true;

112 }

113 return false;

114}

115

117 switch (Opc) {

118 case TargetOpcode::G_LOAD:

119 case TargetOpcode::G_STORE:

120 case TargetOpcode::G_PHI:

121 case TargetOpcode::G_SELECT:

122 case TargetOpcode::G_IMPLICIT_DEF:

123 case TargetOpcode::G_UNMERGE_VALUES:

124 case TargetOpcode::G_MERGE_VALUES:

125 return true;

126 default:

127 return false;

128 }

129}

130

131void MipsRegisterBankInfo::AmbiguousRegDefUseContainer::addDefUses(

134 "Pointers are gprb, they should not be considered as ambiguous.\n");

135 for (MachineInstr &UseMI : MRI.use_instructions(Reg)) {

136 MachineInstr *NonCopyInstr = skipCopiesOutgoing(&UseMI);

137

138 if (NonCopyInstr->getOpcode() == TargetOpcode::COPY &&

141 else

142 DefUses.push_back(skipCopiesOutgoing(&UseMI));

143 }

144}

145

146void MipsRegisterBankInfo::AmbiguousRegDefUseContainer::addUseDef(

149 "Pointers are gprb, they should not be considered as ambiguous.\n");

150 MachineInstr *DefMI = MRI.getVRegDef(Reg);

151 UseDefs.push_back(skipCopiesIncoming(DefMI));

152}

153

154MachineInstr *

155MipsRegisterBankInfo::AmbiguousRegDefUseContainer::skipCopiesOutgoing(

156 MachineInstr *MI) const {

157 const MachineFunction &MF = *MI->getParent()->getParent();

158 const MachineRegisterInfo &MRI = MF.getRegInfo();

159 MachineInstr *Ret = MI;

160 while (Ret->getOpcode() == TargetOpcode::COPY &&

164 }

165 return Ret;

166}

167

168MachineInstr *

169MipsRegisterBankInfo::AmbiguousRegDefUseContainer::skipCopiesIncoming(

170 MachineInstr *MI) const {

171 const MachineFunction &MF = *MI->getParent()->getParent();

172 const MachineRegisterInfo &MRI = MF.getRegInfo();

173 MachineInstr *Ret = MI;

174 while (Ret->getOpcode() == TargetOpcode::COPY &&

177 return Ret;

178}

179

180MipsRegisterBankInfo::AmbiguousRegDefUseContainer::AmbiguousRegDefUseContainer(

181 const MachineInstr *MI) {

183 "Not implemented for non Ambiguous opcode.\n");

184

185 const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();

186

187 if (MI->getOpcode() == TargetOpcode::G_LOAD)

188 addDefUses(MI->getOperand(0).getReg(), MRI);

189

190 if (MI->getOpcode() == TargetOpcode::G_STORE)

191 addUseDef(MI->getOperand(0).getReg(), MRI);

192

194 addDefUses(PHI->getReg(0), MRI);

195

196 for (unsigned I = 1; I < PHI->getNumIncomingValues(); ++I)

197 addUseDef(PHI->getIncomingValue(I), MRI);

198 }

199

200 if (MI->getOpcode() == TargetOpcode::G_SELECT) {

201 addDefUses(MI->getOperand(0).getReg(), MRI);

202

203 addUseDef(MI->getOperand(2).getReg(), MRI);

204 addUseDef(MI->getOperand(3).getReg(), MRI);

205 }

206

207 if (MI->getOpcode() == TargetOpcode::G_IMPLICIT_DEF)

208 addDefUses(MI->getOperand(0).getReg(), MRI);

209

210 if (MI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES)

211 addUseDef(MI->getOperand(MI->getNumOperands() - 1).getReg(), MRI);

212

213 if (MI->getOpcode() == TargetOpcode::G_MERGE_VALUES)

214 addDefUses(MI->getOperand(0).getReg(), MRI);

215}

216

217bool MipsRegisterBankInfo::TypeInfoForMF::visit(

218 const MachineInstr *MI, const MachineInstr *WaitingForTypeOfMI,

219 InstType &AmbiguousTy) {

220 assert(isAmbiguous(MI->getOpcode()) && "Visiting non-Ambiguous opcode.\n");

221 if (wasVisited(MI))

222 return true;

223

224 startVisit(MI);

225 AmbiguousRegDefUseContainer DefUseContainer(MI);

226

228 setTypes(MI, Integer);

229 return true;

230 }

231

232 if (AmbiguousTy == InstType::Ambiguous &&

233 (MI->getOpcode() == TargetOpcode::G_MERGE_VALUES ||

234 MI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES))

235 AmbiguousTy = InstType::AmbiguousWithMergeOrUnmerge;

236

237

238 if (visitAdjacentInstrs(MI, DefUseContainer.getDefUses(), true, AmbiguousTy))

239 return true;

240

241

242 if (visitAdjacentInstrs(MI, DefUseContainer.getUseDefs(), false, AmbiguousTy))

243 return true;

244

245

246 if (!WaitingForTypeOfMI) {

247

248 setTypes(MI, AmbiguousTy);

249 return true;

250 }

251

252

253

254

255

256

257

258

259 addToWaitingQueue(WaitingForTypeOfMI, MI);

260 return false;

261}

262

263bool MipsRegisterBankInfo::TypeInfoForMF::visitAdjacentInstrs(

264 const MachineInstr *MI, SmallVectorImpl<MachineInstr *> &AdjacentInstrs,

265 bool isDefUse, InstType &AmbiguousTy) {

266 while (!AdjacentInstrs.empty()) {

267 MachineInstr *AdjMI = AdjacentInstrs.pop_back_val();

268

271 setTypes(MI, InstType::FloatingPoint);

272 return true;

273 }

274

275

276

277 if (AdjMI->getOpcode() == TargetOpcode::COPY) {

278 setTypesAccordingToPhysicalRegister(MI, AdjMI, isDefUse ? 0 : 1);

279 return true;

280 }

281

282

283

284 if ((!isDefUse && AdjMI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES) ||

285 (isDefUse && AdjMI->getOpcode() == TargetOpcode::G_MERGE_VALUES) ||

287 setTypes(MI, InstType::Integer);

288 return true;

289 }

290

291

292

293 if (!wasVisited(AdjMI) ||

294 getRecordedTypeForInstr(AdjMI) != InstType::NotDetermined) {

295 if (visit(AdjMI, MI, AmbiguousTy)) {

296

297 setTypes(MI, getRecordedTypeForInstr(AdjMI));

298 return true;

299 }

300 }

301 }

302 return false;

303}

304

305void MipsRegisterBankInfo::TypeInfoForMF::setTypes(const MachineInstr *MI,

306 InstType InstTy) {

307 changeRecordedTypeForInstr(MI, InstTy);

308 for (const MachineInstr *WaitingInstr : getWaitingQueueFor(MI)) {

309 setTypes(WaitingInstr, InstTy);

310 }

311}

312

313void MipsRegisterBankInfo::TypeInfoForMF::setTypesAccordingToPhysicalRegister(

314 const MachineInstr *MI, const MachineInstr *CopyInst, unsigned Op) {

316 "Copies of non physical registers should not be considered here.\n");

317

318 const MachineFunction &MF = *CopyInst->getMF();

319 const MachineRegisterInfo &MRI = MF.getRegInfo();

323 const RegisterBank *Bank =

325

326 if (Bank == &Mips::FPRBRegBank)

327 setTypes(MI, InstType::FloatingPoint);

328 else if (Bank == &Mips::GPRBRegBank)

329 setTypes(MI, InstType::Integer);

330 else

332}

333

334MipsRegisterBankInfo::InstType

335MipsRegisterBankInfo::TypeInfoForMF::determineInstType(const MachineInstr *MI) {

336 InstType DefaultAmbiguousType = InstType::Ambiguous;

337 visit(MI, nullptr, DefaultAmbiguousType);

338 return getRecordedTypeForInstr(MI);

339}

340

341void MipsRegisterBankInfo::TypeInfoForMF::cleanupIfNewFunction(

342 llvm::StringRef FunctionName) {

343 if (MFName != FunctionName) {

344 MFName = std::string(FunctionName);

345 WaitingQueues.clear();

347 }

348}

349

350static const MipsRegisterBankInfo::ValueMapping *

353 "MSA mapping not available on target without MSA.");

355}

356

361

363

364

365

368 if (Size == 32)

370

373}

374

375const RegisterBankInfo::InstructionMapping &

377

378 static TypeInfoForMF TI;

379

380

381 TI.cleanupIfNewFunction(MI.getMF()->getName());

382

383 unsigned Opc = MI.getOpcode();

386

387 if (MI.getOpcode() != TargetOpcode::G_PHI) {

391 return Mapping;

392 }

393

395

396 unsigned NumOperands = MI.getNumOperands();

399

400

402 if (Op.isReg()) {

403 LLT RegTy = MRI.getType(Op.getReg());

404

408

411 }

412 }

413

414 const LLT Op0Ty = MRI.getType(MI.getOperand(0).getReg());

416 InstType InstTy = InstType::Integer;

417

418 switch (Opc) {

419 case G_TRUNC:

420 case G_UMULH:

421 case G_ZEXTLOAD:

422 case G_SEXTLOAD:

423 case G_PTR_ADD:

424 case G_INTTOPTR:

425 case G_PTRTOINT:

426 case G_AND:

427 case G_OR:

428 case G_XOR:

429 case G_SHL:

430 case G_ASHR:

431 case G_LSHR:

432 case G_BRINDIRECT:

433 case G_VASTART:

434 case G_BSWAP:

435 case G_CTLZ:

437 break;

438 case G_ADD:

439 case G_SUB:

440 case G_MUL:

441 case G_SDIV:

442 case G_SREM:

443 case G_UDIV:

444 case G_UREM:

446 if (Op0Size == 128)

448 break;

449 case G_STORE:

450 case G_LOAD: {

451 if (Op0Size == 128) {

454 break;

455 }

456

458 InstTy = TI.determineInstType(&MI);

459

460 if (isFloatingPoint_32or64(InstTy, Op0Size) ||

461 isAmbiguous_64(InstTy, Op0Size)) {

464 } else {

465 assert((isInteger_32(InstTy, Op0Size) ||

466 isAmbiguous_32(InstTy, Op0Size) ||

467 isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size)) &&

468 "Unexpected Inst type");

469 OperandsMapping =

472 }

473

474 break;

475 }

476 case G_PHI: {

478 InstTy = TI.determineInstType(&MI);

479

480

481 if (isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size)) {

482 OperandsMapping =

484 TI.clearTypeInfoData(&MI);

486 1);

487 }

488 assert((isInteger_32(InstTy, Op0Size) ||

489 isFloatingPoint_32or64(InstTy, Op0Size) ||

490 isAmbiguous_32or64(InstTy, Op0Size)) &&

491 "Unexpected Inst type");

492

493

495 }

496 case G_SELECT: {

498 InstTy = TI.determineInstType(&MI);

499 if (isFloatingPoint_32or64(InstTy, Op0Size) ||

500 isAmbiguous_64(InstTy, Op0Size)) {

504 break;

505 } else {

506 assert((isInteger_32(InstTy, Op0Size) ||

507 isAmbiguous_32(InstTy, Op0Size) ||

508 isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size)) &&

509 "Unexpected Inst type");

514 }

515 break;

516 }

517 case G_IMPLICIT_DEF: {

519 InstTy = TI.determineInstType(&MI);

520

521 if (isFloatingPoint_32or64(InstTy, Op0Size))

523 else {

524 assert((isInteger_32(InstTy, Op0Size) ||

525 isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size)) &&

526 "Unexpected Inst type");

528 }

529 } break;

530 case G_UNMERGE_VALUES: {

531 assert(MI.getNumOperands() == 3 && "Unsupported G_UNMERGE_VALUES");

532 unsigned Op3Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();

533 InstTy = TI.determineInstType(&MI);

534 assert((isAmbiguousWithMergeOrUnmerge_64(InstTy, Op3Size) ||

535 isFloatingPoint_64(InstTy, Op3Size)) &&

536 "Unexpected Inst type");

540 if (isAmbiguousWithMergeOrUnmerge_64(InstTy, Op3Size))

542 break;

543 }

544 case G_MERGE_VALUES: {

545 InstTy = TI.determineInstType(&MI);

546 assert((isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size) ||

547 isFloatingPoint_64(InstTy, Op0Size)) &&

548 "Unexpected Inst type");

552 if (isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size))

554 break;

555 }

556 case G_FADD:

557 case G_FSUB:

558 case G_FMUL:

559 case G_FDIV:

560 case G_FABS:

561 case G_FSQRT:

563 if (Op0Size == 128)

565 break;

566 case G_FCONSTANT:

568 break;

569 case G_FCMP: {

570 unsigned Op2Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();

571 OperandsMapping =

574 break;

575 }

576 case G_FPEXT:

579 break;

580 case G_FPTRUNC:

583 break;

584 case G_FPTOSI: {

585 assert((Op0Size == 32) && "Unsupported integer size");

586 unsigned SizeFP = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();

589 break;

590 }

591 case G_SITOFP:

592 assert((MRI.getType(MI.getOperand(1).getReg()).getSizeInBits() == 32) &&

593 "Unsupported integer size");

596 break;

597 case G_CONSTANT:

598 case G_FRAME_INDEX:

599 case G_GLOBAL_VALUE:

600 case G_JUMP_TABLE:

601 case G_BRCOND:

602 OperandsMapping =

604 break;

605 case G_BRJT:

606 OperandsMapping =

609 break;

610 case G_ICMP:

611 OperandsMapping =

615 break;

616 default:

618 }

619

621 TI.clearTypeInfoData(&MI);

623 NumOperands);

624}

625

627namespace {

631

632public:

634 assert(.isObservingChanges());

635 B.setChangeObserver(*this);

636 }

637

638 ~InstManager() override { B.stopObservingChanges(); }

639

644};

645}

646

649 Register Dest = MI.getOperand(0).getReg();

650 switch (MI.getOpcode()) {

651 case TargetOpcode::G_STORE:

652

653 break;

654 case TargetOpcode::G_CONSTANT:

655 case TargetOpcode::G_LOAD:

656 case TargetOpcode::G_SELECT:

657 case TargetOpcode::G_PHI:

658 case TargetOpcode::G_IMPLICIT_DEF: {

660 MRI.setRegBank(Dest, getRegBank(Mips::GPRBRegBankID));

661 break;

662 }

663 case TargetOpcode::G_PTR_ADD: {

664 assert(MRI.getType(Dest).isPointer() && "Unexpected operand type.");

665 MRI.setRegBank(Dest, getRegBank(Mips::GPRBRegBankID));

666 break;

667 }

668 default:

670 }

671}

672

673static void

679 UpdatedDefs, Observer);

681 DeadMI->eraseFromParent();

682}

683

687 Builder.setInstrAndDebugLoc(MI);

688

693

694 InstManager NewInstrObserver(Builder, NewInstrs);

697

698 switch (MI.getOpcode()) {

699 case TargetOpcode::G_LOAD:

700 case TargetOpcode::G_STORE:

701 case TargetOpcode::G_PHI:

702 case TargetOpcode::G_SELECT:

703 case TargetOpcode::G_IMPLICIT_DEF: {

705

706 while (!NewInstrs.empty()) {

708

709

710

713

714

715 else if (NewMI->getOpcode() == TargetOpcode::G_MERGE_VALUES)

716 continue;

717 else

718

720 }

721 return;

722 }

723 case TargetOpcode::G_UNMERGE_VALUES:

725 NewInstrObserver);

726 return;

727 default:

728 break;

729 }

730

732}

unsigned const MachineRegisterInfo * MRI

MachineInstrBuilder & UseMI

MachineInstrBuilder MachineInstrBuilder & DefMI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static const unsigned CustomMappingID

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

This contains common code to allow clients to notify changes to machine instr.

GISelWorkList< 256 > InstListTy

Promote Memory to Register

static const MipsRegisterBankInfo::ValueMapping * getGprbOrCustomMapping(unsigned Size, unsigned &MappingID)

Definition MipsRegisterBankInfo.cpp:367

static bool isFloatingPointOpcodeUse(unsigned Opc)

Definition MipsRegisterBankInfo.cpp:80

static bool isFloatingPointOpcodeDef(unsigned Opc)

Definition MipsRegisterBankInfo.cpp:93

static const MipsRegisterBankInfo::ValueMapping * getMSAMapping(const MachineFunction &MF)

Definition MipsRegisterBankInfo.cpp:351

static bool isGprbTwoInstrUnalignedLoadOrStore(const MachineInstr *MI)

Definition MipsRegisterBankInfo.cpp:103

static bool isAmbiguous(unsigned Opc)

Definition MipsRegisterBankInfo.cpp:116

static const MipsRegisterBankInfo::ValueMapping * getFprbMapping(unsigned Size)

Definition MipsRegisterBankInfo.cpp:357

static void combineAwayG_UNMERGE_VALUES(LegalizationArtifactCombiner &ArtCombiner, GUnmerge &MI, GISelChangeObserver &Observer)

Definition MipsRegisterBankInfo.cpp:674

This file declares the targeting of the RegisterBankInfo class for Mips.

void visit(MachineFunction &MF, MachineBasicBlock &Start, std::function< void(MachineBasicBlock *)> op)

Abstract class that contains various methods for clients to notify about changes.

void insert(MachineInstr *I)

Add the specified instruction to the worklist if it isn't already in it.

MachineInstr * pop_back_val()

Represents a G_UNMERGE_VALUES.

constexpr bool isScalar() const

static constexpr LLT scalar(unsigned SizeInBits)

Get a low-level scalar or aggregate "bag of bits".

constexpr bool isVector() const

constexpr TypeSize getSizeInBits() const

Returns the total size of the type. Must only be called on sized types.

constexpr bool isPointer() const

bool tryCombineUnmergeValues(GUnmerge &MI, SmallVectorImpl< MachineInstr * > &DeadInsts, SmallVectorImpl< Register > &UpdatedDefs, GISelChangeObserver &Observer)

LLVM_ABI LegalizeResult narrowScalar(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy)

Legalize an instruction by reducing the width of the underlying scalar type.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Helper class to build MachineInstr.

Representation of each machine instruction.

unsigned getOpcode() const

Returns the opcode of this MachineInstr.

LLVM_ABI const MachineFunction * getMF() const

Return the function that contains the basic block that this instruction belongs to.

const MachineOperand & getOperand(unsigned i) const

MachineOperand class - Representation of each machine instruction operand.

getReg - Returns the register number.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

void applyMappingImpl(MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const override

Here we have to narrowScalar s64 operands to s32, combine away G_MERGE or G_UNMERGE and erase instruc...

Definition MipsRegisterBankInfo.cpp:684

MipsRegisterBankInfo(const TargetRegisterInfo &TRI)

Definition MipsRegisterBankInfo.cpp:76

void setRegBank(MachineInstr &MI, MachineRegisterInfo &MRI) const

RegBankSelect determined that s64 operand is better to be split into two s32 operands in gprb.

Definition MipsRegisterBankInfo.cpp:647

const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override

Get the mapping of the different operands of MI on the register bank.

Definition MipsRegisterBankInfo.cpp:376

bool systemSupportsUnalignedAccess() const

Does the system support unaligned memory access.

Helper class that represents how the value of an instruction may be mapped and what is the related co...

bool isValid() const

Check whether this object is valid.

Helper class used to get/create the virtual registers that will be used to replace the MachineOperand...

MachineInstr & getMI() const

MachineRegisterInfo & getMRI() const

The MachineRegisterInfo we used to realize the mapping.

const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const

Method to get a uniquely generated InstructionMapping.

static void applyDefaultMapping(const OperandsMapper &OpdMapper)

Helper method to apply something that is like the default mapping.

const InstructionMapping & getInvalidInstructionMapping() const

Method to get a uniquely generated invalid InstructionMapping.

const RegisterBank & getRegBank(unsigned ID)

Get the register bank identified by ID.

RegisterBankInfo(const RegisterBank **RegBanks, unsigned NumRegBanks, const unsigned *Sizes, unsigned HwMode)

Create a RegisterBankInfo that can accommodate up to NumRegBanks RegisterBank instances.

const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const

Get the uniquely generated array of ValueMapping for the elements of between Begin and End.

static const unsigned DefaultMappingID

Identifier used when the related instruction mapping instance is generated by target independent code...

const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const

Try to get the mapping of MI.

Wrapper class representing virtual and physical registers.

constexpr bool isPhysical() const

Return true if the specified register number is in the physical register namespace.

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual const RegisterBankInfo * getRegBankInfo() const

If the information for the register banks is available, return it.

virtual const LegalizerInfo * getLegalizerInfo() const

virtual const TargetRegisterInfo * getRegisterInfo() const =0

Return the target's register information.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

PartialMappingIdx

Definition MipsRegisterBankInfo.cpp:27

@ PMI_MSA

Definition MipsRegisterBankInfo.cpp:31

@ PMI_Min

Definition MipsRegisterBankInfo.cpp:32

@ PMI_DPR

Definition MipsRegisterBankInfo.cpp:30

@ PMI_GPR

Definition MipsRegisterBankInfo.cpp:28

@ PMI_SPR

Definition MipsRegisterBankInfo.cpp:29

const RegisterBankInfo::ValueMapping ValueMappings[]

Definition MipsRegisterBankInfo.cpp:50

ValueMappingIdx

Definition MipsRegisterBankInfo.cpp:42

@ GPRIdx

Definition MipsRegisterBankInfo.cpp:44

@ DPRIdx

Definition MipsRegisterBankInfo.cpp:46

@ InvalidIdx

Definition MipsRegisterBankInfo.cpp:43

@ SPRIdx

Definition MipsRegisterBankInfo.cpp:45

@ MSAIdx

Definition MipsRegisterBankInfo.cpp:47

const RegisterBankInfo::PartialMapping PartMappings[]

Definition MipsRegisterBankInfo.cpp:35

Invariant opcodes: All instruction sets have these as their low opcodes.

This is an optimization pass for GlobalISel generic memory operations.

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

DWARFExpression::Operation Op

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

LLVM_ABI bool isPreISelGenericFloatingPointOpcode(unsigned Opc)

Returns whether opcode Opc is a pre-isel generic floating-point opcode, having only floating-point op...

Helper struct that represents how a value is partially mapped into a register.

Helper struct that represents how a value is mapped through different register banks.