LLVM: llvm::RegisterBankInfo Class Reference (original) (raw)
Holds all the information related to register banks. More...
#include "[llvm/CodeGen/RegisterBankInfo.h](RegisterBankInfo%5F8h%5Fsource.html)"
| Classes | |
|---|---|
| class | InstructionMapping |
| Helper class that represents how the value of an instruction may be mapped and what is the related cost of such mapping. More... | |
| class | OperandsMapper |
| Helper class used to get/create the virtual registers that will be used to replace the MachineOperand when applying a mapping. More... | |
| struct | PartialMapping |
| Helper struct that represents how a value is partially mapped into a register. More... | |
| struct | ValueMapping |
| Helper struct that represents how a value is mapped through different register banks. More... |
| Public Member Functions | |
|---|---|
| const RegisterBank * | getRegBankFromConstraints (const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, const MachineRegisterInfo &MRI) const |
| Get the register bank for the OpIdx-th operand of MI form the encoding constraints, if any. | |
| virtual void | applyMappingImpl (MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const |
| See applyMapping. | |
| virtual | ~RegisterBankInfo ()=default |
| const RegisterBank & | getRegBank (unsigned ID) const |
| Get the register bank identified by ID. | |
| unsigned | getMaximumSize (unsigned RegBankID) const |
| Get the maximum size in bits that fits in the given register bank. | |
| const RegisterBank * | getRegBank (Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const |
| Get the register bank of Reg. | |
| unsigned | getNumRegBanks () const |
| Get the total number of register banks. | |
| virtual bool | isDivergentRegBank (const RegisterBank *RB) const |
| Returns true if the register bank is considered divergent. | |
| virtual const RegisterBank & | getRegBankFromRegClass (const TargetRegisterClass &RC, LLT Ty) const |
| Get a register bank that covers RC. | |
| virtual unsigned | copyCost (const RegisterBank &A, const RegisterBank &B, TypeSize Size) const |
| Get the cost of a copy from B to A, or put differently, get the cost of A = COPY B. | |
| bool | cannotCopy (const RegisterBank &Dst, const RegisterBank &Src, TypeSize Size) const |
| virtual unsigned | getBreakDownCost (const ValueMapping &ValMapping, const RegisterBank *CurBank=nullptr) const |
| Get the cost of using ValMapping to decompose a register. | |
| virtual const InstructionMapping & | getInstrMapping (const MachineInstr &MI) const |
| Get the mapping of the different operands of MI on the register bank. | |
| virtual InstructionMappings | getInstrAlternativeMappings (const MachineInstr &MI) const |
| Get the alternative mappings for MI. | |
| InstructionMappings | getInstrPossibleMappings (const MachineInstr &MI) const |
| Get the possible mapping for MI. | |
| void | applyMapping (MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const |
| Apply OpdMapper.getInstrMapping() to OpdMapper.getMI(). | |
| TypeSize | getSizeInBits (Register Reg, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI) const |
| Get the size in bits of Reg. | |
| bool | verify (const TargetRegisterInfo &TRI) const |
| Check that information hold by this instance make sense for the given TRI. |
| Static Public Attributes | |
|---|---|
| static const unsigned | DefaultMappingID = UINT_MAX |
| Identifier used when the related instruction mapping instance is generated by target independent code. | |
| static const unsigned | InvalidMappingID = UINT_MAX - 1 |
| Identifier used when the related instruction mapping instance is generated by the default constructor. |
| Protected Member Functions | |
|---|---|
| RegisterBankInfo (const RegisterBank **RegBanks, unsigned NumRegBanks, const unsigned *Sizes, unsigned HwMode) | |
| Create a RegisterBankInfo that can accommodate up to NumRegBanks RegisterBank instances. | |
| RegisterBankInfo () | |
| This constructor is meaningless. | |
| const RegisterBank & | getRegBank (unsigned ID) |
| Get the register bank identified by ID. | |
| const TargetRegisterClass * | getMinimalPhysRegClass (MCRegister Reg, const TargetRegisterInfo &TRI) const |
| Get the MinimalPhysRegClass for Reg. | |
| const InstructionMapping & | getInstrMappingImpl (const MachineInstr &MI) const |
| Try to get the mapping of MI. | |
| const PartialMapping & | getPartialMapping (unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const |
| Get the uniquely generated PartialMapping for the given arguments. | |
| Methods to get a uniquely generated ValueMapping. | |
| const ValueMapping & | getValueMapping (unsigned StartIdx, unsigned Length, const RegisterBank &RegBank) const |
| The most common ValueMapping consists of a single PartialMapping. | |
| const ValueMapping & | getValueMapping (const PartialMapping *BreakDown, unsigned NumBreakDowns) const |
| Get the ValueMapping for the given arguments. | |
| Methods to get a uniquely generated array of ValueMapping. | |
| template | |
| const ValueMapping * | getOperandsMapping (Iterator Begin, Iterator End) const |
| Get the uniquely generated array of ValueMapping for the elements of between Begin and End. | |
| const ValueMapping * | getOperandsMapping (const SmallVectorImpl< const ValueMapping * > &OpdsMapping) const |
| Get the uniquely generated array of ValueMapping for the elements of OpdsMapping. | |
| const ValueMapping * | getOperandsMapping (std::initializer_list< const ValueMapping * > OpdsMapping) const |
| Get the uniquely generated array of ValueMapping for the given arguments. |
| Protected Attributes | |
|---|---|
| const RegisterBank ** | RegBanks |
| Hold the set of supported register banks. | |
| unsigned | NumRegBanks |
| Total number of register banks. | |
| const unsigned * | Sizes |
| Hold the sizes of the register banks for all HwModes. | |
| unsigned | HwMode |
| Current HwMode for the target. | |
| DenseMap< hash_code, std::unique_ptr< const PartialMapping > > | MapOfPartialMappings |
| Keep dynamically allocated PartialMapping in a separate map. | |
| DenseMap< hash_code, std::unique_ptr< const ValueMapping > > | MapOfValueMappings |
| Keep dynamically allocated ValueMapping in a separate map. | |
| DenseMap< hash_code, std::unique_ptr< ValueMapping[]> > | MapOfOperandsMappings |
| Keep dynamically allocated array of ValueMapping in a separate map. | |
| DenseMap< hash_code, std::unique_ptr< const InstructionMapping > > | MapOfInstructionMappings |
| Keep dynamically allocated InstructionMapping in a separate map. | |
| DenseMap< MCRegister, const TargetRegisterClass * > | PhysRegMinimalRCs |
| Getting the minimal register class of a physreg is expensive. |
Holds all the information related to register banks.
Definition at line 40 of file RegisterBankInfo.h.
◆ InstructionMappings
Convenient type to represent the alternatives for mapping an instruction.
When we move to TableGen this should be an array ref.
Definition at line 277 of file RegisterBankInfo.h.
◆ RegisterBankInfo() [2/2]
| llvm::RegisterBankInfo::RegisterBankInfo ( ) | inlineprotected |
|---|
This constructor is meaningless.
It just provides a default constructor that can be used at link time when GlobalISel is not built. That way, targets can still inherit from this class without doing crazy gymnastic to avoid link time failures.
Note
That works because the constructor is inlined.
Definition at line 435 of file RegisterBankInfo.h.
References llvm_unreachable.
◆ ~RegisterBankInfo()
| virtual llvm::RegisterBankInfo::~RegisterBankInfo ( ) | virtualdefault |
|---|
◆ applyDefaultMapping()
Helper method to apply something that is like the default mapping.
Basically, that means that OpdMapper.getMI() is left untouched aside from the reassignment of the register operand that have been remapped.
The type of all the new registers that have been created by the mapper are properly remapped to the type of the original registers they replace. In other words, the semantic of the instruction does not change, only the register banks.
If the mapping of one of the operand spans several registers, this method will abort as this is not like a default mapping anymore.
Precondition
For OpIdx in {0..OpdMapper.getMI().getNumOperands()) the range OpdMapper.getVRegs(OpIdx) is empty or of size 1.
Definition at line 438 of file RegisterBankInfo.cpp.
References assert(), llvm::iterator_range< IteratorT >::begin(), llvm::dbgs(), llvm::iterator_range< IteratorT >::empty(), llvm::RegisterBankInfo::OperandsMapper::getInstrMapping(), llvm::RegisterBankInfo::OperandsMapper::getMI(), llvm::RegisterBankInfo::OperandsMapper::getMRI(), llvm::RegisterBankInfo::InstructionMapping::getNumOperands(), llvm::MachineOperand::getReg(), llvm::LLT::getSizeInBits(), llvm::RegisterBankInfo::OperandsMapper::getVRegs(), llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownLE(), llvm::MachineOperand::isReg(), LLVM_DEBUG, MI, MRI, llvm::RegisterBankInfo::ValueMapping::NumBreakDowns, OpIdx, llvm::printReg(), and llvm::MachineOperand::setReg().
Referenced by applyMapping(), llvm::AMDGPURegisterBankInfo::applyMappingBFE(), llvm::AMDGPURegisterBankInfo::applyMappingImage(), llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::MipsRegisterBankInfo::applyMappingImpl(), llvm::X86RegisterBankInfo::applyMappingImpl(), llvm::AMDGPURegisterBankInfo::applyMappingMAD_64_32(), and llvm::AMDGPURegisterBankInfo::applyMappingSMULU64().
◆ applyMapping()
◆ applyMappingImpl()
◆ cannotCopy()
◆ constrainGenericRegister()
Constrain the (possibly generic) virtual register Reg to RC.
Precondition
Reg is a virtual register that either has a bank or a class.
Returns
The constrained register class, or nullptr if there is none.
Note
This is a generic variant of MachineRegisterInfo::constrainRegClass
Use MachineRegisterInfo::constrainRegAttrs instead for any non-isel purpose, including non-select passes of GlobalISel
Definition at line 131 of file RegisterBankInfo.cpp.
References llvm::cast(), llvm::RegisterBank::covers(), llvm::isa(), and MRI.
Referenced by llvm::AMDGPURegisterBankInfo::buildReadFirstLane(), llvm::AMDGPURegisterBankInfo::buildVCopy(), llvm::constrainRegToClass(), copySubReg(), selectCopy(), selectCopy(), selectCopy(), and selectDebugInstr().
◆ copyCost()
◆ getBreakDownCost()
Get the cost of using ValMapping to decompose a register.
This is similar to copyCost, except for cases where multiple copy-like operations need to be inserted. If the register is used as a source operand and already has a bank assigned, CurBank is non-null.
Reimplemented in llvm::AMDGPURegisterBankInfo.
Definition at line 653 of file RegisterBankInfo.h.
◆ getInstrAlternativeMappings()
◆ getInstrMapping()
Get the mapping of the different operands of MI on the register bank.
This mapping should be the direct translation of MI. In other words, when MI is mapped with the returned mapping, only the register banks of the operands of MI need to be updated. In particular, neither the opcode nor the type of MI needs to be updated for this direct mapping.
The target independent implementation gives a mapping based on the register classes for the target specific opcode. It uses the ID RegisterBankInfo::DefaultMappingID for that mapping. Make sure you do not use that ID for the alternative mapping for MI. See getInstrAlternativeMappings for the alternative mappings.
For instance, if MI is a vector add, the mapping should not be a scalarization of the add.
Postcondition
returnedVal.verify(MI).
Note
If returnedVal does not verify MI, this would probably mean that the target does not support that instruction.
Reimplemented in llvm::AArch64RegisterBankInfo, llvm::AMDGPURegisterBankInfo, llvm::ARMRegisterBankInfo, llvm::M68kRegisterBankInfo, llvm::MipsRegisterBankInfo, llvm::PPCRegisterBankInfo, llvm::RISCVRegisterBankInfo, and llvm::X86RegisterBankInfo.
Definition at line 406 of file RegisterBankInfo.cpp.
References getInstrMappingImpl(), llvm::RegisterBankInfo::InstructionMapping::isValid(), llvm_unreachable, and MI.
Referenced by llvm::RegisterBankInfo::OperandsMapper::createVRegs(), getInstrPossibleMappings(), llvm::RegisterBankInfo::OperandsMapper::getVRegs(), llvm::RegisterBankInfo::OperandsMapper::print(), and llvm::RegisterBankInfo::OperandsMapper::setVRegs().
◆ getInstrMappingImpl()
Try to get the mapping of MI.
See getInstrMapping for more details on what a mapping represents.
Unlike getInstrMapping the returned InstructionMapping may be invalid (isValid() == false). This means that the target independent code is not smart enough to get the mapping of MI and thus, the target has to provide the information for MI.
This implementation is able to get the mapping of:
- Target specific instructions by looking at the encoding constraints.
- Any instruction if all the register operands have already been assigned a register, a register class, or a register bank.
- Copies and phis if at least one of the operands has been assigned a register, a register class, or a register bank. In other words, this method will likely fail to find a mapping for any generic opcode that has not been lowered by target specific code.
Definition at line 161 of file RegisterBankInfo.cpp.
References assert(), cannotCopy(), DefaultMappingID, llvm::TargetSubtargetInfo::getInstrInfo(), getInstructionMapping(), getInvalidInstructionMapping(), getOperandsMapping(), llvm::MachineOperand::getReg(), getRegBank(), getRegBankFromConstraints(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), getSizeInBits(), llvm::MachineFunction::getSubtarget(), getValueMapping(), isCopyLike(), llvm::MachineOperand::isReg(), MI, MRI, OpIdx, Size, TII, and TRI.
Referenced by llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), llvm::ARMRegisterBankInfo::getInstrMapping(), llvm::M68kRegisterBankInfo::getInstrMapping(), llvm::MipsRegisterBankInfo::getInstrMapping(), llvm::PPCRegisterBankInfo::getInstrMapping(), getInstrMapping(), llvm::RISCVRegisterBankInfo::getInstrMapping(), and llvm::X86RegisterBankInfo::getInstrMapping().
◆ getInstrPossibleMappings()
Get the possible mapping for MI.
A mapping defines where the different operands may live and at what cost. For instance, let us consider: v0(16) = G_ADD <2 x i8> v1, v2 The possible mapping could be:
{/*ID*/VectorAdd, /*Cost*/1, /*v0*/{(0xFFFF, VPR)}, /*v1*/{(0xFFFF, VPR)}, /*v2*/{(0xFFFF, VPR)}} {/*ID*/ScalarAddx2, /*Cost*/2, /*v0*/{(0x00FF, GPR),(0xFF00, GPR)}, /*v1*/{(0x00FF, GPR),(0xFF00, GPR)}, /*v2*/{(0x00FF, GPR),(0xFF00, GPR)}}
Note
The first alternative of the returned mapping should be the direct translation of MI current form.
Postcondition
!returnedVal.empty().
Definition at line 414 of file RegisterBankInfo.cpp.
References llvm::append_range(), assert(), getInstrAlternativeMappings(), getInstrMapping(), MI, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
◆ getInstructionMapping()
Method to get a uniquely generated InstructionMapping.
Definition at line 534 of file RegisterBankInfo.h.
Referenced by llvm::AMDGPURegisterBankInfo::addMappingFromTable(), llvm::AMDGPURegisterBankInfo::getDefaultMappingAllVGPR(), llvm::AMDGPURegisterBankInfo::getDefaultMappingSOP(), llvm::AMDGPURegisterBankInfo::getDefaultMappingVOP(), llvm::AMDGPURegisterBankInfo::getImageMapping(), llvm::AArch64RegisterBankInfo::getInstrAlternativeMappings(), llvm::AMDGPURegisterBankInfo::getInstrAlternativeMappings(), llvm::X86RegisterBankInfo::getInstrAlternativeMappings(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), llvm::ARMRegisterBankInfo::getInstrMapping(), llvm::M68kRegisterBankInfo::getInstrMapping(), llvm::MipsRegisterBankInfo::getInstrMapping(), llvm::PPCRegisterBankInfo::getInstrMapping(), llvm::RISCVRegisterBankInfo::getInstrMapping(), llvm::X86RegisterBankInfo::getInstrMapping(), llvm::AMDGPURegisterBankInfo::getInstrMappingForLoad(), and getInstrMappingImpl().
◆ getInvalidInstructionMapping()
◆ getMaximumSize()
| unsigned llvm::RegisterBankInfo::getMaximumSize ( unsigned RegBankID) const | inline |
|---|
◆ getMinimalPhysRegClass()
◆ getNumRegBanks()
| unsigned llvm::RegisterBankInfo::getNumRegBanks ( ) const | inline |
|---|
◆ getOperandsMapping() [1/3]
◆ getOperandsMapping() [2/3]
template
Get the uniquely generated array of ValueMapping for the elements of between Begin and End.
Elements that are nullptr will be replaced by invalid ValueMapping (ValueMapping::isValid == false).
Precondition
The pointers on ValueMapping between Begin and End must uniquely identify a ValueMapping. Otherwise, there is no guarantee that the return instance will be unique, i.e., another OperandsMapping could have the same content.
Definition at line 332 of file RegisterBankInfo.cpp.
References llvm::hash_combine_range(), and MapOfOperandsMappings.
Referenced by llvm::AMDGPURegisterBankInfo::addMappingFromTable(), llvm::AMDGPURegisterBankInfo::getDefaultMappingAllVGPR(), llvm::AMDGPURegisterBankInfo::getDefaultMappingSOP(), llvm::AMDGPURegisterBankInfo::getDefaultMappingVOP(), llvm::AMDGPURegisterBankInfo::getImageMapping(), llvm::AArch64RegisterBankInfo::getInstrAlternativeMappings(), llvm::AMDGPURegisterBankInfo::getInstrAlternativeMappings(), llvm::X86RegisterBankInfo::getInstrAlternativeMappings(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), llvm::ARMRegisterBankInfo::getInstrMapping(), llvm::M68kRegisterBankInfo::getInstrMapping(), llvm::MipsRegisterBankInfo::getInstrMapping(), llvm::PPCRegisterBankInfo::getInstrMapping(), llvm::RISCVRegisterBankInfo::getInstrMapping(), llvm::X86RegisterBankInfo::getInstrMapping(), llvm::AMDGPURegisterBankInfo::getInstrMappingForLoad(), getInstrMappingImpl(), and getOperandsMapping().
◆ getOperandsMapping() [3/3]
◆ getPartialMapping()
◆ getRegBank() [1/3]
◆ getRegBank() [2/3]
Get the register bank identified by [ID](namespacellvm%5F1%5F1CallingConv.html#abdf8cf606905c10634e831390981b0ed "LLVM IR allows to use arbitrary numbers as calling convention identifiers.").
Definition at line 440 of file RegisterBankInfo.h.
References assert(), getNumRegBanks(), and RegBanks.
Referenced by llvm::AArch64RegisterBankInfo::AArch64RegisterBankInfo(), llvm::AMDGPURegisterBankInfo::AMDGPURegisterBankInfo(), llvm::AMDGPURegisterBankInfo::applyMappingDynStackAlloc(), llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::ARMRegisterBankInfo::ARMRegisterBankInfo(), llvm::AMDGPURegisterBankInfo::buildReadFirstLane(), buildReadLane(), checkRB(), llvm::AMDGPURegisterBankInfo::collectWaterfallOperands(), llvm::AMDGPURegisterBankInfo::constrainOpWithReadfirstlane(), llvm::AMDGPURegisterBankInfo::executeInWaterfallLoop(), llvm::GIMatchTableExecutor::executeMatchTable(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), llvm::RISCVRegisterBankInfo::getInstrMapping(), llvm::AMDGPURegisterBankInfo::getInstrMappingForLoad(), getInstrMappingImpl(), llvm::SIInstrInfo::getInstructionUniformity(), llvm::AMDGPURegisterBankInfo::getMappingType(), getRegBank(), llvm::AArch64RegisterBankInfo::getRegBankFromRegClass(), llvm::PPCRegisterBankInfo::getRegBankFromRegClass(), llvm::AMDGPURegisterBankInfo::getRegBankID(), getRegClassesForCopy(), llvm::AMDGPURegisterBankInfo::getValueMappingForPtr(), llvm::AMDGPURegisterBankInfo::isSALUMapping(), llvm::SIRegisterInfo::isUniformReg(), selectCopy(), selectCopy(), selectMergeValues(), selectUnmergeValues(), llvm::AMDGPURegisterBankInfo::setBufferOffsets(), llvm::MipsRegisterBankInfo::setRegBank(), llvm::AMDGPURegisterBankInfo::split64BitValueForMapping(), unmergeReadAnyLane(), unsupportedBinOp(), verify(), and llvm::X86RegisterBankInfo::X86RegisterBankInfo().
◆ getRegBank() [3/3]
◆ getRegBankFromConstraints()
◆ getRegBankFromRegClass()
Get a register bank that covers RC.
Precondition
RC is a user-defined register class (as opposed as one generated by TableGen).
Note
The mapping RC -> RegBank could be built while adding the coverage for the register banks. However, we do not do it, because, at least for now, we only need this information for register classes that are used in the description of instruction. In other words, there are just a handful of them and we do not want to waste space.
This should be TableGen'ed.
Reimplemented in llvm::AArch64RegisterBankInfo, llvm::AMDGPURegisterBankInfo, llvm::PPCRegisterBankInfo, and llvm::SPIRVRegisterBankInfo.
Definition at line 623 of file RegisterBankInfo.h.
References llvm_unreachable.
Referenced by llvm::GIMatchTableExecutor::executeMatchTable(), getRegBank(), getRegBankFromConstraints(), llvm::AArch64RegisterBankInfo::getRegBankFromRegClass(), and llvm::PPCRegisterBankInfo::getRegBankFromRegClass().
◆ getSizeInBits()
Get the size in bits of Reg.
Utility method to get the size of any registers. Unlike MachineRegisterInfo::getSize, the register does not need to be a virtual register.
Precondition
Reg != 0 (NoRegister).
Definition at line 497 of file RegisterBankInfo.cpp.
References assert(), getMinimalPhysRegClass(), MRI, and TRI.
Referenced by llvm::AMDGPURegisterBankInfo::addMappingFromTable(), llvm::AMDGPURegisterBankInfo::getAGPROpMapping(), llvm::AMDGPURegisterBankInfo::getDefaultMappingAllVGPR(), llvm::AMDGPURegisterBankInfo::getDefaultMappingSOP(), llvm::AMDGPURegisterBankInfo::getDefaultMappingVOP(), llvm::AMDGPURegisterBankInfo::getImageMapping(), llvm::AArch64RegisterBankInfo::getInstrAlternativeMappings(), llvm::AMDGPURegisterBankInfo::getInstrAlternativeMappings(), llvm::X86RegisterBankInfo::getInstrAlternativeMappings(), llvm::AArch64RegisterBankInfo::getInstrMapping(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), llvm::PPCRegisterBankInfo::getInstrMapping(), llvm::AMDGPURegisterBankInfo::getInstrMappingForLoad(), getInstrMappingImpl(), getRegClassesForCopy(), llvm::AMDGPURegisterBankInfo::getSGPROpMapping(), llvm::AMDGPURegisterBankInfo::getVGPROpMapping(), selectCopy(), and llvm::RegisterBankInfo::InstructionMapping::verify().
◆ getValueMapping() [1/2]
◆ getValueMapping() [2/2]
◆ isDivergentRegBank()
◆ verify()
◆ DefaultMappingID
◆ HwMode
◆ InvalidMappingID
◆ MapOfInstructionMappings
◆ MapOfOperandsMappings
◆ MapOfPartialMappings
◆ MapOfValueMappings
◆ NumRegBanks
| unsigned llvm::RegisterBankInfo::NumRegBanks | protected |
|---|
◆ PhysRegMinimalRCs
◆ RegBanks
◆ Sizes
The documentation for this class was generated from the following files:
- include/llvm/CodeGen/RegisterBankInfo.h
- lib/CodeGen/RegisterBankInfo.cpp