MipsSEFrameLowering.cpp Source File (original) (raw)

40#include

41#include

42#include

43#include

45using namespace llvm;

47static std::pair<unsigned, unsigned> getMFHiLoOpc(unsigned Src) {

48 if (Mips::ACC64RegClass.contains(Src))

49 return std::make_pair((unsigned)Mips::PseudoMFHI,

50 (unsigned)Mips::PseudoMFLO);

52 if (Mips::ACC64DSPRegClass.contains(Src))

53 return std::make_pair((unsigned)Mips::MFHI_DSP, (unsigned)Mips::MFLO_DSP);

55 if (Mips::ACC128RegClass.contains(Src))

56 return std::make_pair((unsigned)Mips::PseudoMFHI64,

57 (unsigned)Mips::PseudoMFLO64);

59 return std::make_pair(0, 0);

60}

62namespace {

65class ExpandPseudo {

66public:

67 ExpandPseudo(MachineFunction &MF);

70private:

73 bool expandInstr(MachineBasicBlock &MBB, Iter I);

74 void expandLoadCCond(MachineBasicBlock &MBB, Iter I);

75 void expandStoreCCond(MachineBasicBlock &MBB, Iter I);

76 void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);

77 void expandStoreACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc,

78 unsigned MFLoOpc, unsigned RegSize);

79 bool expandCopy(MachineBasicBlock &MBB, Iter I);

80 bool expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc,

81 unsigned MFLoOpc);

82 bool expandBuildPairF64(MachineBasicBlock &MBB,

84 bool expandExtractElementF64(MachineBasicBlock &MBB,

87 MachineFunction &MF;

88 MachineRegisterInfo &MRI;

89 const MipsSubtarget &Subtarget;

90 const MipsSEInstrInfo &TII;

91 const MipsRegisterInfo &RegInfo;

92};

94}

97 : MF(MF_), MRI(MF.getRegInfo()),

100 RegInfo(*Subtarget.getRegisterInfo()) {}

101

102bool ExpandPseudo::expand() {

103 bool Expanded = false;

104

105 for (auto &MBB : MF) {

107 Expanded |= expandInstr(MBB, I++);

108 }

109

110 return Expanded;

111}

112

113bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) {

114 switch(I->getOpcode()) {

115 case Mips::LOAD_CCOND_DSP:

116 expandLoadCCond(MBB, I);

117 break;

118 case Mips::STORE_CCOND_DSP:

119 expandStoreCCond(MBB, I);

120 break;

121 case Mips::LOAD_ACC64:

122 case Mips::LOAD_ACC64DSP:

123 expandLoadACC(MBB, I, 4);

124 break;

125 case Mips::LOAD_ACC128:

126 expandLoadACC(MBB, I, 8);

127 break;

128 case Mips::STORE_ACC64:

129 expandStoreACC(MBB, I, Mips::PseudoMFHI, Mips::PseudoMFLO, 4);

130 break;

131 case Mips::STORE_ACC64DSP:

132 expandStoreACC(MBB, I, Mips::MFHI_DSP, Mips::MFLO_DSP, 4);

133 break;

134 case Mips::STORE_ACC128:

135 expandStoreACC(MBB, I, Mips::PseudoMFHI64, Mips::PseudoMFLO64, 8);

136 break;

137 case Mips::BuildPairF64:

138 if (expandBuildPairF64(MBB, I, false))

140 return false;

141 case Mips::BuildPairF64_64:

142 if (expandBuildPairF64(MBB, I, true))

144 return false;

145 case Mips::ExtractElementF64:

146 if (expandExtractElementF64(MBB, I, false))

148 return false;

149 case Mips::ExtractElementF64_64:

150 if (expandExtractElementF64(MBB, I, true))

152 return false;

153 case TargetOpcode::COPY:

154 if (!expandCopy(MBB, I))

155 return false;

156 break;

157 default:

158 return false;

159 }

160

162 return true;

163}

164

165void ExpandPseudo::expandLoadCCond(MachineBasicBlock &MBB, Iter I) {

166

167

168

169 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());

170

171 const TargetRegisterClass *RC = RegInfo.intRegClass(4);

172 Register VR = MRI.createVirtualRegister(RC);

173 Register Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();

174

175 TII.loadRegFromStack(MBB, I, VR, FI, RC, 0);

178}

179

180void ExpandPseudo::expandStoreCCond(MachineBasicBlock &MBB, Iter I) {

181

182

183

184 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());

185

186 const TargetRegisterClass *RC = RegInfo.intRegClass(4);

187 Register VR = MRI.createVirtualRegister(RC);

188 Register Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();

189

192 TII.storeRegToStack(MBB, I, VR, true, FI, RC, 0);

193}

194

195void ExpandPseudo::expandLoadACC(MachineBasicBlock &MBB, Iter I,

197

198

199

200

201

202 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());

203

205 Register VR0 = MRI.createVirtualRegister(RC);

206 Register VR1 = MRI.createVirtualRegister(RC);

207 Register Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();

208 Register Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);

209 Register Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);

211 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);

212

213 TII.loadRegFromStack(MBB, I, VR0, FI, RC, 0);

217}

218

219void ExpandPseudo::expandStoreACC(MachineBasicBlock &MBB, Iter I,

220 unsigned MFHiOpc, unsigned MFLoOpc,

222

223

224

225

226

227 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());

228

230 Register VR0 = MRI.createVirtualRegister(RC);

231 Register VR1 = MRI.createVirtualRegister(RC);

232 Register Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();

233 unsigned SrcKill = getKillRegState(I->getOperand(0).isKill());

235

237 TII.storeRegToStack(MBB, I, VR0, true, FI, RC, 0);

239 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, RegSize);

240}

241

242bool ExpandPseudo::expandCopy(MachineBasicBlock &MBB, Iter I) {

243 Register Src = I->getOperand(1).getReg();

244 std::pair<unsigned, unsigned> Opcodes = getMFHiLoOpc(Src);

245

246 if (!Opcodes.first)

247 return false;

248

249 return expandCopyACC(MBB, I, Opcodes.first, Opcodes.second);

250}

251

252bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I,

253 unsigned MFHiOpc, unsigned MFLoOpc) {

254

255

256

257

258

259 unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();

260 const TargetRegisterClass *DstRC = RegInfo.getMinimalPhysRegClass(Dst);

261 unsigned VRegSize = RegInfo.getRegSizeInBits(*DstRC) / 16;

262 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize);

263 Register VR0 = MRI.createVirtualRegister(RC);

264 Register VR1 = MRI.createVirtualRegister(RC);

265 unsigned SrcKill = getKillRegState(I->getOperand(1).isKill());

266 Register DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);

267 Register DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);

269

276 return true;

277}

278

279

280

281

282

283

284bool ExpandPseudo::expandBuildPairF64(MachineBasicBlock &MBB,

286 bool FP64) const {

287

288

289

290

291

292

293

294

295

296

297

298

299

300

301

302

303 if (I->getNumOperands() == 4 && I->getOperand(3).isReg()

304 && I->getOperand(3).getReg() == Mips::SP) {

305 Register DstReg = I->getOperand(0).getReg();

306 Register LoReg = I->getOperand(1).getReg();

307 Register HiReg = I->getOperand(2).getReg();

308

309

310

311

314

315 const TargetRegisterClass *RC = &Mips::GPR32RegClass;

316 const TargetRegisterClass *RC2 =

317 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;

318

319

320

321 int FI = MF.getInfo()->getMoveF64ViaSpillFI(MF, RC2);

324 TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, 0);

325 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, 4);

326 TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, 0);

327 return true;

328 }

329

330 return false;

331}

332

333

334

335

336

337

338bool ExpandPseudo::expandExtractElementF64(MachineBasicBlock &MBB,

340 bool FP64) const {

341 const MachineOperand &Op1 = I->getOperand(1);

342 const MachineOperand &Op2 = I->getOperand(2);

343

345 Register DstReg = I->getOperand(0).getReg();

346 BuildMI(MBB, I, I->getDebugLoc(), TII.get(Mips::IMPLICIT_DEF), DstReg);

347 return true;

348 }

349

350

351

352

353

354

355

356

357

358

359

360

361

362

363

364

365

366 if (I->getNumOperands() == 4 && I->getOperand(3).isReg()

367 && I->getOperand(3).getReg() == Mips::SP) {

368 Register DstReg = I->getOperand(0).getReg();

370 unsigned N = Op2.getImm();

372

373

374

375

378

379 const TargetRegisterClass *RC =

380 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;

381 const TargetRegisterClass *RC2 = &Mips::GPR32RegClass;

382

383

384

385 int FI = MF.getInfo()->getMoveF64ViaSpillFI(MF, RC);

386 TII.storeRegToStack(MBB, I, SrcReg, Op1.isKill(), FI, RC, 0);

387 TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, Offset);

388 return true;

389 }

390

391 return false;

392}

393

396

401

405

409 unsigned SP = ABI.GetStackPtr();

410 unsigned FP = ABI.GetFramePtr();

411 unsigned ZERO = ABI.GetNullPtr();

412 unsigned MOVE = ABI.GetGPRMoveOp();

413 unsigned ADDiu = ABI.GetPtrAddiuOp();

414 unsigned AND = ABI.IsN64() ? Mips::AND64 : Mips::AND;

415

417 &Mips::GPR64RegClass : &Mips::GPR32RegClass;

418

419

421

422

423 if (StackSize == 0 && !MFI.adjustsStack()) return;

424

426

427

428 TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);

430

432 emitInterruptPrologueStub(MF, MBB);

433

435

436

437

438 std::advance(MBBI, CSI.size());

440

441 if (!CSI.empty()) {

442

443

447

448

449

450 if (Mips::AFGR64RegClass.contains(Reg)) {

451 MCRegister Reg0 = RegInfo.getSubReg(Reg, Mips::sub_lo);

452 MCRegister Reg1 = RegInfo.getSubReg(Reg, Mips::sub_hi);

453

454 if ( STI .isLittle())

456

459 } else if (Mips::FGR64RegClass.contains(Reg)) {

462

463 if ( STI .isLittle())

465

468 } else {

469

471 }

472 }

473 }

474

476

477 for (int I = 0; I < 4; ++I) {

478 if ( MBB .isLiveIn(ABI.GetEhDataReg(I)))

479 MBB.addLiveIn(ABI.GetEhDataReg(I));

480 TII.storeRegToStackSlot(MBB, MBBI, ABI.GetEhDataReg(I), false,

482 }

483

484

485 for (int I = 0; I < 4; ++I) {

488 }

489 }

490

491

493

496

498

499 if (RegInfo.hasStackRealignment(MF)) {

500

501

504 "Function's alignment size requirement is not supported.");

506

509

511

512 unsigned BP = STI.isABI_N64() ? Mips::S7_64 : Mips::S7;

516 }

517 }

518 }

519}

520

521void MipsSEFrameLowering::emitInterruptPrologueStub(

526

527

528

529

530

531

534 "\"interrupt\" attribute is not supported on pre-MIPS32R2 or "

535 "MIPS16 targets.");

536

537

538

539

540

542 report_fatal_error("\"interrupt\" attribute is only supported for the "

543 "static relocation model on MIPS at the present time.");

544

546 report_fatal_error("\"interrupt\" attribute is only supported for the "

547 "O32 ABI on MIPS32R2+ at the present time.");

548

549

553

554

555

556 if (IntKind == "eic") {

557

558 MBB.addLiveIn(Mips::COP013);

560 .addReg(Mips::COP013)

563

569 }

570

571

572 MBB.addLiveIn(Mips::COP014);

574 .addReg(Mips::COP014)

577

580

581

582 MBB.addLiveIn(Mips::COP012);

584 .addReg(Mips::COP012)

587

590

591

592

593 unsigned InsPosition = 8;

594 unsigned InsSize = 0;

595 unsigned SrcReg = Mips::ZERO;

596

597

598

599 if (IntKind == "eic") {

600 SrcReg = Mips::K0;

601 InsPosition = 10;

602 InsSize = 6;

603 } else

604 InsSize = StringSwitch(IntKind)

605 .Case("sw0", 1)

606 .Case("sw1", 2)

607 .Case("hw0", 3)

608 .Case("hw1", 4)

609 .Case("hw2", 5)

610 .Case("hw3", 6)

611 .Case("hw4", 7)

612 .Case("hw5", 8)

613 .Default(0);

614 assert(InsSize != 0 && "Unknown interrupt type!");

615

622

623

630

631

632 if ( STI .useSoftFloat())

639

640

641 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012)

645}

646

652

655

658 unsigned SP = ABI.GetStackPtr();

659 unsigned FP = ABI.GetFramePtr();

660 unsigned ZERO = ABI.GetNullPtr();

661 unsigned MOVE = ABI.GetGPRMoveOp();

662

663

665

667

669 --I;

670

671

673 }

674

677 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;

678

679

682 --I;

683

684

685 for (int J = 0; J < 4; ++J) {

686 TII.loadRegFromStackSlot(MBB, I, ABI.GetEhDataReg(J),

688 }

689 }

690

692 emitInterruptEpilogueStub(MF, MBB);

693

694

696

697 if (!StackSize)

698 return;

699

700

701 TII.adjustStackPtr(SP, StackSize, MBB, MBBI);

702}

703

704void MipsSEFrameLowering::emitInterruptEpilogueStub(

709

710

712

713

716

717

723

724

730}

731

737

739 FrameReg = hasFP(MF) ? ABI.GetFramePtr() : ABI.GetStackPtr();

740 else

741 FrameReg = hasBP(MF) ? ABI.GetBasePtr() : ABI.GetStackPtr();

742

746}

747

753

755

756

757

758

759

761 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64)

763 if (!IsRAAndRetAddrIsTaken)

764 MBB.addLiveIn(Reg);

765

766

767

768 bool IsLOHI = (Reg == Mips::LO0 || Reg == Mips::LO0_64 ||

769 Reg == Mips::HI0 || Reg == Mips::HI0_64);

770 const Function &Func = MBB.getParent()->getFunction();

771 if (IsLOHI && Func.hasFnAttribute("interrupt")) {

773

774 unsigned Op = 0;

775 if ( STI .getABI().ArePtrs64bit()) {

776 Op = (Reg == Mips::HI0) ? Mips::MFHI : Mips::MFLO;

777 Reg = Mips::K0;

778 } else {

779 Op = (Reg == Mips::HI0) ? Mips::MFHI64 : Mips::MFLO64;

780 Reg = Mips::K0_64;

781 }

784 }

785

786

787 bool IsKill = !IsRAAndRetAddrIsTaken;

789 TII.storeRegToStackSlot(MBB, MI, Reg, IsKill, I.getFrameIdx(), RC,

791 }

792

793 return true;

794}

795

796bool

806

807

809 unsigned Reg) {

812 SavedRegs.set(*AI);

813}

814

822 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA;

823 unsigned FP = ABI.GetFramePtr();

824 unsigned BP = ABI.IsN64() ? Mips::S7_64 : Mips::S7;

825

826

830 }

831

834

835

838

839

840 if (MipsFI->isISR())

842

843

844

845 if (ExpandPseudo(MF).expand()) {

846

847

848

850 Mips::GPR64RegClass : Mips::GPR32RegClass;

852 TRI->getSpillAlign(RC));

853 RS->addScavengingFrameIndex(FI);

854 }

855

856

858

859

860

861 if (isIntN(STI.hasMSA() ? 10 : 16, MaxSPOffset) &&

863 return;

864

866 ABI.ArePtrs64bit() ? Mips::GPR64RegClass : Mips::GPR32RegClass;

868 TRI->getSpillAlign(RC));

869 RS->addScavengingFrameIndex(FI);

870}

871

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

MachineBasicBlock MachineBasicBlock::iterator MBBI

This file implements the BitVector class.

@ ZERO

Special weight used for cases with exact zero probability.

static Expected< BitVector > expand(StringRef S, StringRef Original)

Promote Memory to Register

static std::pair< unsigned, unsigned > getMFHiLoOpc(unsigned Src)

Definition MipsSEFrameLowering.cpp:47

static void setAliasRegs(MachineFunction &MF, BitVector &SavedRegs, unsigned Reg)

Mark Reg and all registers aliasing it in the bitset.

Definition MipsSEFrameLowering.cpp:808

This file declares the machine register scavenger class.

SI optimize exec mask operations pre RA

static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)

This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

LLVM_ABI StringRef getValueAsString() const

Return the attribute's value as a string.

Helper class for creating CFI instructions and inserting them into MIR.

void buildDefCFAOffset(int64_t Offset, MCSymbol *Label=nullptr) const

void buildDefCFARegister(MCRegister Reg) const

void buildOffset(MCRegister Reg, int64_t Offset) const

void setInsertPoint(MachineBasicBlock::iterator IP)

The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...

Attribute getFnAttribute(Attribute::AttrKind Kind) const

Return the attribute for the given attribute kind.

bool hasFnAttribute(Attribute::AttrKind Kind) const

Return true if the function has the attribute.

const MCInstrDesc & get(unsigned Opcode) const

Return the machine instruction descriptor that corresponds to the specified instruction opcode.

MCRegAliasIterator enumerates all registers aliasing Reg.

Wrapper class representing physical registers. Should be passed by value.

LLVM_ABI instr_iterator erase(instr_iterator I)

Remove an instruction from the instruction list and delete it.

MachineInstrBundleIterator< MachineInstr > iterator

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

bool hasVarSizedObjects() const

This method may be called any time after instruction selection is complete to determine if the stack ...

uint64_t getStackSize() const

Return the number of bytes that must be allocated to hold all of the fixed size frame objects.

bool adjustsStack() const

Return true if this function adjusts the stack – e.g., when calling another function.

bool isReturnAddressTaken() const

This method may be called any time after instruction selection is complete to determine if there is a...

Align getMaxAlign() const

Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...

uint64_t getMaxCallFrameSize() const

Return the maximum size of a call frame that must be allocated for an outgoing function call.

int64_t getOffsetAdjustment() const

Return the correction for frame offsets.

LLVM_ABI int CreateSpillStackObject(uint64_t Size, Align Alignment)

Create a new statically sized stack object that represents a spill slot, returning a nonnegative iden...

const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const

Returns a reference to call saved info vector for the current function.

int64_t getObjectOffset(int ObjectIdx) const

Return the assigned stack offset of the specified object from the incoming stack pointer.

bool isFixedObjectIndex(int ObjectIdx) const

Returns true if the specified index corresponds to a fixed stack object.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

Function & getFunction()

Return the LLVM function that this machine code represents.

Ty * getInfo()

getInfo - Keep track of various per-function pieces of information for backends that would like to do...

const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const

Add a new virtual register operand.

const MachineOperand & getOperand(unsigned i) const

bool isReg() const

isReg - Tests if this is a MO_Register operand.

getReg - Returns the register number.

LLVM_ABI Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")

createVirtualRegister - Create and return a new virtual register in the function with the specified r...

MipsFrameLowering(const MipsSubtarget &sti, Align Alignment)

bool hasBP(const MachineFunction &MF) const

uint64_t estimateStackSize(const MachineFunction &MF) const

const MipsSubtarget & STI

MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...

int getEhDataRegFI(unsigned Reg) const

int getISRRegFI(Register Reg) const

bool callsEhReturn() const

void createEhDataRegsFI(MachineFunction &MF)

void createISRRegFI(MachineFunction &MF)

void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override

virtual void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, int64_t Offset, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const =0

virtual const TargetRegisterClass * intRegClass(unsigned Size) const =0

Return GPR register class.

void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override

This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...

Definition MipsSEFrameLowering.cpp:815

MipsSEFrameLowering(const MipsSubtarget &STI)

Definition MipsSEFrameLowering.cpp:394

StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override

getFrameIndexReference - This method should return the base register and offset used to reference a f...

Definition MipsSEFrameLowering.cpp:733

bool hasReservedCallFrame(const MachineFunction &MF) const override

hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...

Definition MipsSEFrameLowering.cpp:797

bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override

spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...

Definition MipsSEFrameLowering.cpp:748

void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override

emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.

Definition MipsSEFrameLowering.cpp:397

void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override

Definition MipsSEFrameLowering.cpp:647

const MipsInstrInfo * getInstrInfo() const override

Reloc::Model getRelocationModel() const

Wrapper class representing virtual and physical registers.

StackOffset holds a fixed and a scalable offset in bytes.

int64_t getFixed() const

Returns the fixed component of the stack.

StringRef - Represent a constant reference to a string, i.e.

unsigned getStackAlignment() const

getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...

bool hasFP(const MachineFunction &MF) const

hasFP - Return true if the specified function should have a dedicated frame pointer register.

virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const

This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...

int getOffsetOfLocalArea() const

getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...

TargetInstrInfo - Interface to description of machine instruction set.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

virtual const TargetRegisterInfo * getRegisterInfo() const =0

Return the target's register information.

@ Kill

The last use of a register.

This is an optimization pass for GlobalISel generic memory operations.

auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)

Get the size of a range.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

constexpr bool isInt(int64_t x)

Checks if an integer fits into the given bit width.

const MipsFrameLowering * createMipsSEFrameLowering(const MipsSubtarget &ST)

Definition MipsSEFrameLowering.cpp:873

LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)

unsigned getKillRegState(bool B)

DWARFExpression::Operation Op

constexpr bool isIntN(unsigned N, int64_t x)

Checks if an signed integer fits into the given (dynamic) bit width.

unsigned Log2(Align A)

Returns the log2 of the alignment.

void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)

Implement std::swap in terms of BitVector swap.

constexpr uint64_t value() const

This is a hole in the type system and should not be abused.