MipsSubtarget.h Source File (original) (raw)

13#ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H

14#define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H

29#define GET_SUBTARGETINFO_HEADER

30#include "MipsGenSubtargetInfo.inc"

32namespace llvm {

33class StringRef;

35class MipsTargetMachine;

38 virtual void anchor();

40 enum MipsArchEnum {

41 MipsDefault,

42 Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,

43 Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6

44 };

46 enum class CPU { Others, P5600, I6400, I6500 };

49 static bool DspWarningPrinted;

52 static bool MSAWarningPrinted;

55 static bool CRCWarningPrinted;

58 static bool GINVWarningPrinted;

61 static bool MIPS1WarningPrinted;

64 static bool VirtWarningPrinted;

67 MipsArchEnum MipsArchVersion;

70 CPU ProcImpl = CPU::Others;

73 bool IsLittle;

76 bool IsSoftFloat;

81 bool IsSingleFloat;

84 bool IsFPXX;

87 bool NoABICalls;

90 bool Abs2008;

93 bool IsFP64bit;

97 bool UseOddSPReg;

100 bool IsNaN2008bit;

101

102

103 bool IsGP64bit;

104

105

106 bool IsPTR64bit;

107

108

109 bool HasVFPU;

110

111

112 bool HasCnMips;

113

114

115 bool HasCnMipsP;

116

117

118 bool IsLinux;

119

120

121 bool UseSmallSection;

122

123

124

125

126 bool HasMips3_32;

127

128

129 bool HasMips3_32r2;

130

131

132 bool HasMips4_32;

133

134

135 bool HasMips4_32r2;

136

137

138 bool HasMips5_32r2;

139

140

141 bool InMips16Mode;

142

143

144 bool InMips16HardFloat;

145

146

147 bool InMicroMipsMode;

148

149

150 bool HasDSP, HasDSPR2, HasDSPR3;

151

152

153 bool Has3D;

154

155

156 bool AllowMixed16_32;

157

158

159

160

161 bool Os16;

162

163

164 bool HasMSA;

165

166

167 bool UseTCCInDIV;

168

169

170 bool HasSym32;

171

172

173 bool HasEVA;

174

175

176

177 bool DisableMadd4;

178

179

180 bool HasMT;

181

182

183 bool HasCRC;

184

185

186 bool HasVirt;

187

188

189 bool HasGINV;

190

191

192

193 bool UseIndirectJumpsHazard;

194

195

196 bool UseLongCalls = false;

197

198

199 bool UseXGOT = false;

200

201

202 bool StrictAlign;

203

204

205

206 Align stackAlignment;

207

208

210

212

213

214

215 enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;

216

218

220

221 std::unique_ptr TSInfo;

222 std::unique_ptr InstrInfo;

223 std::unique_ptr FrameLowering;

224 std::unique_ptr TLInfo;

225

226public:

228

230 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;

232

238

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249

251

252 bool hasMips1() const { return MipsArchVersion >= Mips1; }

253 bool hasMips2() const { return MipsArchVersion >= Mips2; }

254 bool hasMips3() const { return MipsArchVersion >= Mips3; }

255 bool hasMips4() const { return MipsArchVersion >= Mips4; }

256 bool hasMips5() const { return MipsArchVersion >= Mips5; }

260 return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||

262 }

264 return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||

266 }

268 return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||

270 }

272 return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||

274 }

276 return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||

278 }

279 bool hasMips64() const { return MipsArchVersion >= Mips64; }

280 bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }

281 bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }

282 bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; }

283 bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }

284

287

288 bool isLittle() const { return IsLittle; }

290 bool isFPXX() const { return IsFPXX; }

294 bool isNaN2008() const { return IsNaN2008bit; }

297 bool isGP32bit() const { return !IsGP64bit; }

305 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }

306 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }

307 bool hasVFPU() const { return HasVFPU; }

310 return InMips16Mode;

311 }

312

313

314

315

319 bool inMicroMipsMode() const { return InMicroMipsMode && !InMips16Mode; }

323 bool hasDSP() const { return HasDSP; }

324 bool hasDSPR2() const { return HasDSPR2; }

325 bool hasDSPR3() const { return HasDSPR3; }

326 bool has3D() const { return Has3D; }

327 bool hasMSA() const { return HasMSA; }

329 bool hasEVA() const { return HasEVA; }

330 bool hasMT() const { return HasMT; }

331 bool hasCRC() const { return HasCRC; }

332 bool hasVirt() const { return HasVirt; }

333 bool hasGINV() const { return HasGINV; }

335 return UseIndirectJumpsHazard && hasMips32r2();

336 }

338

340

342

344

345 bool useXGOT() const { return UseXGOT; }

346

350

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354

357

358 bool os16() const { return Os16; }

359

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390

393 return FrameLowering.get();

394 }

396 return &InstrInfo->getRegisterInfo();

397 }

399 return TLInfo.get();

400 }

402 return &InstrItins;

403 }

404

406

407protected:

408

413

414public:

419};

420}

421

422#endif

Analysis containing CSE Info

This file describes how to lower LLVM calls to machine code calls.

Interface for Targets to specify which operations they can successfully select and how the others sho...

Itinerary data supplied by a subtarget to be used by a target.

Tracks which library functions to use for a particular subtarget.

Definition MipsSubtarget.h:37

bool hasMips32r6() const

Definition MipsSubtarget.h:275

void initLibcallLoweringInfo(LibcallLoweringInfo &Info) const override

bool isXRaySupported() const override

Definition MipsSubtarget.h:362

const LegalizerInfo * getLegalizerInfo() const override

static bool useConstantIslands()

bool hasMips4() const

Definition MipsSubtarget.h:255

bool hasMips64r2() const

Definition MipsSubtarget.h:280

bool isFP64bit() const

Definition MipsSubtarget.h:291

bool isTargetELF() const

Definition MipsSubtarget.h:306

bool enablePostRAScheduler() const override

This overrides the PostRAScheduler bit in the SchedModel for each CPU.

bool isLittle() const

Definition MipsSubtarget.h:288

bool inMicroMipsMode() const

Definition MipsSubtarget.h:319

bool hasMips32r5() const

Definition MipsSubtarget.h:271

bool hasMips4_32() const

Definition MipsSubtarget.h:257

bool hasMT() const

Definition MipsSubtarget.h:330

bool isGP32bit() const

Definition MipsSubtarget.h:297

std::unique_ptr< InstructionSelector > InstSelector

Definition MipsSubtarget.h:412

bool hasVirt() const

Definition MipsSubtarget.h:332

bool hasMips32r3() const

Definition MipsSubtarget.h:267

bool useSoftFloat() const

Definition MipsSubtarget.h:341

bool hasDSPR2() const

Definition MipsSubtarget.h:324

const MipsInstrInfo * getInstrInfo() const override

Definition MipsSubtarget.h:391

bool useIndirectJumpsHazard() const

Definition MipsSubtarget.h:334

bool hasMips64r6() const

Definition MipsSubtarget.h:283

bool isNaN2008() const

Definition MipsSubtarget.h:294

bool useOddSPReg() const

Definition MipsSubtarget.h:292

MipsSubtarget & initializeSubtargetDependencies(StringRef CPU, StringRef FS, const TargetMachine &TM)

const CallLowering * getCallLowering() const override

std::unique_ptr< RegisterBankInfo > RegBankInfo

Definition MipsSubtarget.h:411

bool allowMixed16_32() const

Definition MipsSubtarget.h:355

bool hasVFPU() const

Definition MipsSubtarget.h:307

bool inMips16Mode() const

Definition MipsSubtarget.h:308

bool hasMips5() const

Definition MipsSubtarget.h:256

bool hasMips64() const

Definition MipsSubtarget.h:279

~MipsSubtarget() override

bool hasMips32() const

Definition MipsSubtarget.h:259

bool isPTR32bit() const

Definition MipsSubtarget.h:300

bool hasSym32() const

Definition MipsSubtarget.h:301

bool isABI_FPXX() const

Definition MipsSubtarget.h:237

bool useXGOT() const

Definition MipsSubtarget.h:345

bool inAbs2008Mode() const

Definition MipsSubtarget.h:295

std::unique_ptr< CallLowering > CallLoweringInfo

Definition MipsSubtarget.h:409

void setHelperClassesMips16()

bool noOddSPReg() const

Definition MipsSubtarget.h:293

const MipsRegisterInfo * getRegisterInfo() const override

Definition MipsSubtarget.h:395

bool isABICalls() const

Definition MipsSubtarget.h:289

bool os16() const

Definition MipsSubtarget.h:358

void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)

ParseSubtargetFeatures - Parses features string setting specified subtarget options.

bool disableMadd4() const

Definition MipsSubtarget.h:328

const RegisterBankInfo * getRegBankInfo() const override

bool hasCnMips() const

Definition MipsSubtarget.h:285

bool hasEVA() const

Definition MipsSubtarget.h:329

static const RTLIB::LibcallImpl HardFloatLibCalls[34]

Definition MipsSubtarget.h:250

bool systemSupportsUnalignedAccess() const

Does the system support unaligned memory access.

Definition MipsSubtarget.h:381

bool isPositionIndependent() const

bool isGP64bit() const

Definition MipsSubtarget.h:296

bool hasExtractInsert() const

Features related to the presence of specific instructions.

Definition MipsSubtarget.h:352

bool enableLongBranchPass() const

Definition MipsSubtarget.h:347

void setHelperClassesMipsSE()

bool inMicroMips32r6Mode() const

Definition MipsSubtarget.h:320

bool hasMips32r2() const

Definition MipsSubtarget.h:263

bool isTargetCOFF() const

Definition MipsSubtarget.h:305

bool hasDSP() const

Definition MipsSubtarget.h:323

bool hasMips4_32r2() const

Definition MipsSubtarget.h:258

Align getStackAlignment() const

Definition MipsSubtarget.h:368

bool isTargetWindows() const

Definition MipsSubtarget.h:360

const InstrItineraryData * getInstrItineraryData() const override

Definition MipsSubtarget.h:401

InstructionSelector * getInstructionSelector() const override

const SelectionDAGTargetInfo * getSelectionDAGInfo() const override

bool hasMSA() const

Definition MipsSubtarget.h:327

bool isSingleFloat() const

Definition MipsSubtarget.h:304

std::unique_ptr< LegalizerInfo > Legalizer

Definition MipsSubtarget.h:410

bool hasGINV() const

Definition MipsSubtarget.h:333

bool inMips16ModeDefault() const

Definition MipsSubtarget.h:309

bool useLongCalls() const

Definition MipsSubtarget.h:343

unsigned getGPRSizeInBytes() const

Definition MipsSubtarget.h:298

bool hasCRC() const

Definition MipsSubtarget.h:331

bool useSmallSection() const

Definition MipsSubtarget.h:337

const MipsTargetLowering * getTargetLowering() const override

Definition MipsSubtarget.h:398

bool inMips16HardFloat() const

Definition MipsSubtarget.h:316

bool hasCnMipsP() const

Definition MipsSubtarget.h:286

bool hasMTHC1() const

Definition MipsSubtarget.h:353

bool has3D() const

Definition MipsSubtarget.h:326

bool hasStandardEncoding() const

Definition MipsSubtarget.h:339

void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override

bool hasMips64r5() const

Definition MipsSubtarget.h:282

MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little, const MipsTargetMachine &TM, MaybeAlign StackAlignOverride)

This constructor initializes the data members to match that of the specified triple.

bool hasMips3() const

Definition MipsSubtarget.h:254

bool hasMips1() const

Definition MipsSubtarget.h:252

Reloc::Model getRelocationModel() const

bool isFPXX() const

Definition MipsSubtarget.h:290

bool isPTR64bit() const

Definition MipsSubtarget.h:299

bool hasMips2() const

Definition MipsSubtarget.h:253

bool hasMips64r3() const

Definition MipsSubtarget.h:281

bool hasDSPR3() const

Definition MipsSubtarget.h:325

CodeGenOptLevel getOptLevelToEnablePostRAScheduler() const override

const MipsABIInfo & getABI() const

const TargetFrameLowering * getFrameLowering() const override

Definition MipsSubtarget.h:392

Holds all the information related to register banks.

Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...

StringRef - Represent a constant reference to a string, i.e.

Information about stack frame layout on the target.

Primary interface to the complete machine description for the target machine.

Triple - Helper class for working with autoconf configuration names.

This is an optimization pass for GlobalISel generic memory operations.

CodeGenOptLevel

Code generation optimization level.

This struct is a compact representation of a valid (non-zero power of two) alignment.

This struct is a compact representation of a valid (power of two) or undefined (0) alignment.