NVPTXISelLowering.h Source File (original) (raw)

14#ifndef LLVM_LIB_TARGET_NVPTX_NVPTXISELLOWERING_H

15#define LLVM_LIB_TARGET_NVPTX_NVPTXISELLOWERING_H

22namespace llvm {

30public:

37 unsigned Intrinsic) const override;

54 Align InitialAlign,

68 unsigned AS,

73 if (!SrcTy->isIntegerTy() || !DstTy->isIntegerTy())

74 return false;

75 return SrcTy->getPrimitiveSizeInBits() == 64 &&

77 }

80 EVT VT) const override {

83 return MVT::i1;

84 }

87 std::pair<unsigned, const TargetRegisterClass *>

92 bool isVarArg,

103

106 std::optional FirstVAArg,

107 const CallBase &CB, unsigned UniqueCallSite) const;

108

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115 std::vector &Ops,

117

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122 return MVT::i32;

123 }

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142 int &ExtraSteps, bool &UseOneConst,

143 bool Reciprocal) const override;

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150 EVT) const override {

151 return true;

152 }

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181 return true;

182 }

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195 EVT ToVT) const override;

196

198 const APInt &DemandedElts,

200 unsigned Depth = 0) const override;

202 const APInt &DemandedElts,

204 TargetLoweringOpt &TLO,

205 unsigned Depth = 0) const override;

206

207private:

208 const NVPTXSubtarget &STI;

209 mutable unsigned GlobalUniqueCallSite;

210

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251 unsigned getNumRegisters(LLVMContext &Context, EVT VT,

252 std::optional RegisterVT) const override;

253 bool

255 SDValue *Parts, unsigned NumParts, MVT PartVT,

256 std::optionalCallingConv::ID CC) const override;

257

260 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;

261

262 Align getArgumentAlignment(const CallBase *CB, Type *Ty, unsigned Idx,

264};

265

266}

267

268#endif

static SDValue LowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG)

static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)

static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)

static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)

static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST)

static SDValue LowerMLOAD(SDValue Op, SelectionDAG &DAG)

static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget)

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

Function Alias Analysis Results

Atomic ordering constants.

Analysis containing CSE Info

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG)

static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG)

This file describes how to lower LLVM code to machine code.

static SDValue LowerBITCAST(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)

static SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG)

ISD::FROUND is defined to round to nearest with ties rounding away from 0.

static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG)

Class for arbitrary precision integers.

an instruction that atomically reads a memory location, combines it with another value,...

Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...

A parsed version of the target data layout string in and methods for querying it.

Common base class shared among various IRBuilders.

This is an important class for using LLVM in a threaded context.

An instruction for reading from memory.

AtomicOrdering atomicOperationOrderAfterFenceSplit(const Instruction *I) const override

bool enableAggressiveFMAFusion(EVT VT) const override

Return true if target always benefits from combining into FMA for a given value type.

Definition NVPTXISelLowering.h:159

ConstraintType getConstraintType(StringRef Constraint) const override

getConstraintType - Given a constraint letter, return the type of constraint it is for this target.

SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override

This callback is invoked for operations that are unsupported by the target, which are registered to u...

const NVPTXTargetMachine * nvTM

Definition NVPTXISelLowering.h:118

bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallBase &I, MachineFunction &MF, unsigned Intrinsic) const override

Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...

bool SimplifyDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth=0) const override

Attempt to simplify any target nodes based on the demanded bits/elts, returning true on success.

NVPTXTargetLowering(const NVPTXTargetMachine &TM, const NVPTXSubtarget &STI)

std::string getPrototype(const DataLayout &DL, Type *, const ArgListTy &, const SmallVectorImpl< ISD::OutputArg > &, std::optional< unsigned > FirstVAArg, const CallBase &CB, unsigned UniqueCallSite) const

MVT getJumpTableRegTy(const DataLayout &) const override

Definition NVPTXISelLowering.h:155

unsigned getPreferredFPToIntOpcode(unsigned Op, EVT FromVT, EVT ToVT) const override

bool useF32FTZ(const MachineFunction &MF) const

SDValue LowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const

unsigned combineRepeatedFPDivisors() const override

Indicate whether this target prefers to combine FDIVs with the same divisor.

Definition NVPTXISelLowering.h:145

Align getFunctionArgumentAlignment(const Function *F, Type *Ty, unsigned Idx, const DataLayout &DL) const

SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &ExtraSteps, bool &UseOneConst, bool Reciprocal) const override

Hooks for building estimates in place of slower divisions and square roots.

SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override

This hook must be implemented to lower outgoing return values, described by the Outs array,...

SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override

This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...

AtomicExpansionKind shouldCastAtomicLoadInIR(LoadInst *LI) const override

Returns how the given (atomic) load should be cast by the IR-level AtomicExpand pass.

Definition NVPTXISelLowering.h:167

AtomicExpansionKind shouldCastAtomicStoreInIR(StoreInst *SI) const override

Returns how the given (atomic) store should be cast by the IR-level AtomicExpand pass into.

Definition NVPTXISelLowering.h:171

void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override

Lower the specified operand into the Ops vector.

SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const

bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override

Definition NVPTXISelLowering.h:178

Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override

bool isTruncateFree(Type *SrcTy, Type *DstTy) const override

Return true if it's free to truncate a value of type FromTy to type ToTy.

Definition NVPTXISelLowering.h:71

std::string getParamName(const Function *F, int Idx) const

TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override

Return the preferred vector type legalization action.

NVPTX::DivPrecisionLevel getDivF32Level(const MachineFunction &MF, const SDNode &N) const

bool shouldInsertFencesForAtomic(const Instruction *) const override

Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.

Align getFunctionParamOptimizedAlign(const Function *F, Type *ArgTy, const DataLayout &DL) const

getFunctionParamOptimizedAlign - since function arguments are passed via .param space,...

SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const

MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override

Return the type to use for a scalar shift opcode, given the shifted amount type.

Definition NVPTXISelLowering.h:121

EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx, EVT VT) const override

Return the ValueType of the result of SETCC operations.

Definition NVPTXISelLowering.h:79

std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override

Given a physical register constraint (e.g.

bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...

Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override

Inserts in the IR a target-specific intrinsic specifying a fence.

AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.

bool isCheapToSpeculateCtlz(Type *Ty) const override

Return true if it is cheap to speculate a call to intrinsic ctlz.

Definition NVPTXISelLowering.h:165

Align getFunctionByValParamAlign(const Function *F, Type *ArgTy, Align InitialAlign, const DataLayout &DL) const

Helper for computing alignment of a device function byval parameter.

bool allowFMA(MachineFunction &MF, CodeGenOptLevel OptLevel) const

bool usePrecSqrtF32(const SDNode *N=nullptr) const

unsigned getJumpTableEncoding() const override

Return the entry encoding for a jump table in the current function.

bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT) const override

Return true if an FMA operation is faster than a pair of fmul and fadd instructions.

Definition NVPTXISelLowering.h:149

SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override

This hook must be implemented to lower calls into the specified DAG.

void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override

Determine which of the bits specified in Mask are known to be either zero or one and return them in t...

Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...

Represents one node in the SelectionDAG.

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

An instruction for storing to memory.

StringRef - Represent a constant reference to a string, i.e.

LegalizeTypeAction

This enum indicates whether a types are legal for a target, and if not, what action should be used to...

AtomicExpansionKind

Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.

TargetLowering(const TargetLowering &)=delete

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

The instances of the Type class are immutable: once they are created, they are never changed.

LLVM_ABI TypeSize getPrimitiveSizeInBits() const LLVM_READONLY

Return the basic size of this type if it is a primitive type.

bool isIntegerTy() const

True if this is an instance of IntegerType.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

This namespace contains an enum with a value for every intrinsic/builtin function known by LLVM.

This is an optimization pass for GlobalISel generic memory operations.

CodeGenOptLevel

Code generation optimization level.

AtomicOrdering

Atomic ordering for LLVM's memory model.

DWARFExpression::Operation Op

@ Enabled

Convert any .debug_str_offsets tables to DWARF64 if needed.

This struct is a compact representation of a valid (non-zero power of two) alignment.

static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)

Returns the EVT that represents a vector NumElements in length, where each element is of type VT.

bool isVector() const

Return true if this is a vector value type.

unsigned getVectorNumElements() const

Given a vector type, return the number of elements it contains.

This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg + ScalableOffset*...