PPCISelLowering.h Source File (original) (raw)

14#ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H

15#define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H

32#include

33#include

35namespace llvm {

38 namespace PPC {

43 SelectionDAG &DAG);

48 SelectionDAG &DAG);

53 SelectionDAG &DAG);

58 unsigned ShuffleKind, SelectionDAG &DAG);

63 unsigned ShuffleKind, SelectionDAG &DAG);

68 unsigned ShuffleKind, SelectionDAG &DAG);

72 bool &Swap, bool IsLE);

93 bool &Swap, bool IsLE);

98 SelectionDAG &DAG);

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112 bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,

113 unsigned &InsertAtByte, bool &Swap, bool IsLE);

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119 SelectionDAG &DAG);

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172 }

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177 public:

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195 const override {

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211 }

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218 return MVT::i32;

219 }

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229 bool

231 unsigned ElemSizeInBits,

232 unsigned &Index) const override;

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254 unsigned Depth = 0) const override;

255

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258 EVT VT) const override;

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284 MaybeAlign EncodingAlignment = std::nullopt) const;

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331 const APInt &DemandedElts,

333 unsigned Depth = 0) const override;

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376 unsigned AtomicSize,

377 unsigned BinOpcode,

378 unsigned CmpOpcode = 0,

379 unsigned CmpPred = 0) const;

382 bool is8bit,

383 unsigned Opcode,

384 unsigned CmpOpcode = 0,

385 unsigned CmpPred = 0) const;

386

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405 AsmOperandInfo &info, const char *constraint) const override;

406

407 std::pair<unsigned, const TargetRegisterClass *>

409 StringRef Constraint, MVT VT) const override;

410

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418 std::vector &Ops,

420

423 if (ConstraintCode == "es")

425 else if (ConstraintCode == "Q")

427 else if (ConstraintCode == "Z")

429 else if (ConstraintCode == "Zy")

432 }

433

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441 Type *Ty, unsigned AS,

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469 Type *Ty) const override;

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479 EVT VT) const override {

480

481

482 if (Opc != ISD::LOAD && Opc != ISD::STORE)

483 return false;

484 if (VT != MVT::f32 && VT != MVT::f64)

485 return false;

486

487 return true;

488 }

489

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494

497 unsigned Intrinsic) const override;

498

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502 const AttributeList &FuncAttributes) const override;

503

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507 EVT VT, unsigned AddrSpace, Align Alignment = Align(1),

509 unsigned *Fast = nullptr) const override;

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516 EVT VT) const override;

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529 bool

531 unsigned DefinedValues) const override;

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553 return Ty->isArrayTy();

554 }

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570 bool ForCodeSize) const override;

571

577 unsigned JTI,

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594 unsigned NumParts, MVT PartVT, std::optionalCallingConv::ID CC)

595 const override;

596

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615 bool IsVarArg) const;

617

619

620 private:

621 struct ReuseLoadInfo {

626 bool IsDereferenceable = false;

627 bool IsInvariant = false;

630 const MDNode *Ranges = nullptr;

631

632 ReuseLoadInfo() = default;

633

636 if (IsDereferenceable)

638 if (IsInvariant)

640 return F;

641 }

642 };

643

644

645 std::map<PPC::AddrMode, SmallVector<unsigned, 16>> AddrModesMap;

646 void initializeAddrModeMap();

647

648 bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI,

649 SelectionDAG &DAG,

651

652 void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,

653 SelectionDAG &DAG, const SDLoc &dl) const;

654 SDValue LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG,

655 const SDLoc &dl) const;

656

657 bool directMoveIsProfitable(const SDValue &Op) const;

658 SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG,

659 const SDLoc &dl) const;

660

662 const SDLoc &dl) const;

663

664 SDValue LowerTRUNCATEVector(SDValue Op, SelectionDAG &DAG) const;

665

666 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;

667 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;

668

669 bool IsEligibleForTailCallOptimization(

672 const SmallVectorImplISD::InputArg &Ins) const;

673

674 bool IsEligibleForTailCallOptimization_64SVR4(

676 CallingConv::ID CallerCC, const CallBase *CB, bool isVarArg,

677 const SmallVectorImplISD::OutputArg &Outs,

678 const SmallVectorImplISD::InputArg &Ins, const Function *CallerFunc,

679 bool isCalleeExternalSymbol) const;

680

681 bool isEligibleForTCO(const GlobalValue *CalleeGV, CallingConv::ID CalleeCC,

683 bool isVarArg,

684 const SmallVectorImplISD::OutputArg &Outs,

685 const SmallVectorImplISD::InputArg &Ins,

686 const Function *CallerFunc,

687 bool isCalleeExternalSymbol) const;

688

689 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG &DAG, int SPDiff,

692 const SDLoc &dl) const;

693

694 SDValue getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, SDValue GA) const;

695

696 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;

698 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;

699 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;

700 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;

701 SDValue LowerGlobalTLSAddressAIX(SDValue Op, SelectionDAG &DAG) const;

702 SDValue LowerGlobalTLSAddressLinux(SDValue Op, SelectionDAG &DAG) const;

703 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;

708 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;

709 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;

714 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;

715 SDValue LowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;

716 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;

717 SDValue LowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;

723 const SDLoc &dl) const;

725 SDValue LowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;

726 SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;

730 SDValue LowerFunnelShift(SDValue Op, SelectionDAG &DAG) const;

731 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;

732 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;

733 SDValue LowerVPERM(SDValue Op, SelectionDAG &DAG, ArrayRef PermMask,

735 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;

736 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;

737 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;

739 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;

740 SDValue LowerIS_FPCLASS(SDValue Op, SelectionDAG &DAG) const;

741 SDValue LowerADDSUBO_CARRY(SDValue Op, SelectionDAG &DAG) const;

745 SelectionDAG &DAG) const;

746 SDValue lowerLibCallBasedOnType(const char *LibCallFloatName,

747 const char *LibCallDoubleName, SDValue Op,

748 SelectionDAG &DAG) const;

749 bool isLowringToMASSFiniteSafe(SDValue Op) const;

750 bool isLowringToMASSSafe(SDValue Op) const;

751 bool isScalarMASSConversionEnabled() const;

752 SDValue lowerLibCallBase(const char *LibCallDoubleName,

753 const char *LibCallFloatName,

754 const char *LibCallDoubleNameFinite,

755 const char *LibCallFloatNameFinite, SDValue Op,

756 SelectionDAG &DAG) const;

763 SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) const;

764 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;

769

772

773 SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const;

774 SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const;

775 SDValue LowerDMFVectorLoad(SDValue Op, SelectionDAG &DAG) const;

776 SDValue LowerDMFVectorStore(SDValue Op, SelectionDAG &DAG) const;

777 SDValue DMFInsert1024(const SmallVectorImpl &Pairs,

778 const SDLoc &dl, SelectionDAG &DAG) const;

779

782 const SmallVectorImplISD::InputArg &Ins,

783 const SDLoc &dl, SelectionDAG &DAG,

784 SmallVectorImpl &InVals) const;

785

786 SDValue FinishCall(CallFlags CFlags, const SDLoc &dl, SelectionDAG &DAG,

787 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,

789 SDValue &Callee, int SPDiff, unsigned NumBytes,

790 const SmallVectorImplISD::InputArg &Ins,

791 SmallVectorImpl &InVals,

792 const CallBase *CB) const;

793

796 const SmallVectorImplISD::InputArg &Ins,

797 const SDLoc &dl, SelectionDAG &DAG,

798 SmallVectorImpl &InVals) const override;

799

800 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,

801 SmallVectorImpl &InVals) const override;

802

803 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,

804 bool isVarArg,

805 const SmallVectorImplISD::OutputArg &Outs,

806 LLVMContext &Context, const Type *RetTy) const override;

807

809 const SmallVectorImplISD::OutputArg &Outs,

810 const SmallVectorImpl &OutVals,

811 const SDLoc &dl, SelectionDAG &DAG) const override;

812

813 SDValue extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,

814 SelectionDAG &DAG, SDValue ArgVal,

815 const SDLoc &dl) const;

816

817 SDValue LowerFormalArguments_AIX(

819 const SmallVectorImplISD::InputArg &Ins, const SDLoc &dl,

820 SelectionDAG &DAG, SmallVectorImpl &InVals) const;

821 SDValue LowerFormalArguments_64SVR4(

823 const SmallVectorImplISD::InputArg &Ins, const SDLoc &dl,

824 SelectionDAG &DAG, SmallVectorImpl &InVals) const;

825 SDValue LowerFormalArguments_32SVR4(

827 const SmallVectorImplISD::InputArg &Ins, const SDLoc &dl,

828 SelectionDAG &DAG, SmallVectorImpl &InVals) const;

829

832 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,

833 const SDLoc &dl) const;

834

836 const SmallVectorImplISD::OutputArg &Outs,

837 const SmallVectorImpl &OutVals,

838 const SmallVectorImplISD::InputArg &Ins,

839 const SDLoc &dl, SelectionDAG &DAG,

840 SmallVectorImpl &InVals,

841 const CallBase *CB) const;

843 const SmallVectorImplISD::OutputArg &Outs,

844 const SmallVectorImpl &OutVals,

845 const SmallVectorImplISD::InputArg &Ins,

846 const SDLoc &dl, SelectionDAG &DAG,

847 SmallVectorImpl &InVals,

848 const CallBase *CB) const;

850 const SmallVectorImplISD::OutputArg &Outs,

851 const SmallVectorImpl &OutVals,

852 const SmallVectorImplISD::InputArg &Ins,

853 const SDLoc &dl, SelectionDAG &DAG,

854 SmallVectorImpl &InVals,

855 const CallBase *CB) const;

856

857 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;

858 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;

860

875 SDValue combineVectorShuffle(ShuffleVectorSDNode *SVN,

876 SelectionDAG &DAG) const;

877 SDValue combineVReverseMemOP(ShuffleVectorSDNode *SVN, LSBaseSDNode *LSBase,

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886 int &RefinementSteps, bool &UseOneConstNR,

887 bool Reciprocal) const override;

889 int &RefinementSteps) const override;

890 SDValue getSqrtInputTest(SDValue Operand, SelectionDAG &DAG,

891 const DenormalMode &Mode) const override;

893 SelectionDAG &DAG) const override;

895

897 combineElementTruncationToVectorTruncation(SDNode *N,

899

901 SelectionDAG &DAG) const;

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907 SDValue lowerToVINSERTH(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;

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912 SDValue lowerToVINSERTB(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;

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916 SDValue lowerToXXSPLTI32DX(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;

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921 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;

922 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;

923

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926 PPC::AddrMode getAddrModeForFlags(unsigned Flags) const;

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932 unsigned computeMOFlags(const SDNode *Parent, SDValue N,

933 SelectionDAG &DAG) const;

934 };

935

936 namespace PPC {

937

938 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,

939 const TargetLibraryInfo *LibInfo);

940

941 }

942

947

951

952}

953

954#endif

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

Function Alias Analysis Results

This file contains the simple types necessary to represent the attributes associated with functions a...

Analysis containing CSE Info

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

static cl::opt< RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysisLegacy::AdvisorMode::Development, "development", "for training")))

This file describes how to lower LLVM code to machine code.

Class for arbitrary precision integers.

An instruction that atomically checks whether a specified value is in a memory location,...

an instruction that atomically reads a memory location, combines it with another value,...

Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...

This class represents a function call, abstracting a target machine's calling convention.

This is an important base class in LLVM.

A parsed version of the target data layout string in and methods for querying it.

This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...

FunctionLoweringInfo - This contains information that is global to a function that is used when lower...

Common base class shared among various IRBuilders.

This is an important class for using LLVM in a threaded context.

Context object for machine code objects.

Base class for the full range of assembler expressions which are needed for parsing.

uint64_t getScalarSizeInBits() const

unsigned getVectorNumElements() const

bool isScalableVector() const

Return true if this is a vector value type where the runtime length is machine dependent.

TypeSize getSizeInBits() const

Returns the size of the specified MVT in bits.

Representation of each machine instruction.

Flags

Flags values. These may be or'd together.

@ MODereferenceable

The memory access is dereferenceable (i.e., doesn't trap).

@ MOInvariant

The memory access always returns the same value (or traps).

A Module instance is used to store all the information related to an LLVM module.

MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override

Return the type to use for a scalar shift opcode, given the shifted amount type.

Definition PPCISelLowering.h:217

MachineBasicBlock * emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const

CCAssignFn * ccAssignFnForCall(CallingConv::ID CC, bool Return, bool IsVarArg) const

bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallBase &I, MachineFunction &MF, unsigned Intrinsic) const override

Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...

bool isTruncateFree(Type *Ty1, Type *Ty2) const override

isTruncateFree - Return true if it's free to truncate a value of type Ty1 to type Ty2.

Value * emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override

Perform a masked atomicrmw using a target-specific intrinsic.

MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override

This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...

bool isFPExtFree(EVT DestVT, EVT SrcVT) const override

Return true if an fpext operation is free (for instance, because single-precision floating-point numb...

PPC::AddrMode SelectForceXFormMode(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG) const

SelectForceXFormMode - Given the specified address, force it to be represented as an indexed [r+r] op...

Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override

bool hasInlineStackProbe(const MachineFunction &MF) const override

MachineBasicBlock * emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const

bool isCheapToSpeculateCtlz(Type *Ty) const override

Return true if it is cheap to speculate a call to intrinsic ctlz.

Definition PPCISelLowering.h:225

bool supportsTailCallFor(const CallBase *CB) const

bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override

Return true if folding a constant offset with the given GlobalAddress is legal.

MachineBasicBlock * emitProbedAlloca(MachineInstr &MI, MachineBasicBlock *MBB) const

bool isZExtFree(SDValue Val, EVT VT2) const override

Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...

MachineBasicBlock * EmitPartwordAtomicBinary(MachineInstr &MI, MachineBasicBlock *MBB, bool is8bit, unsigned Opcode, unsigned CmpOpcode=0, unsigned CmpPred=0) const

SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, NegatibleCost &Cost, unsigned Depth=0) const override

Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate...

bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG, MaybeAlign EncodingAlignment) const

SelectAddressRegImm - Returns true if the address N can be represented by a base register plus a sign...

bool shouldInsertFencesForAtomic(const Instruction *I) const override

Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.

Definition PPCISelLowering.h:337

bool isCtlzFast() const override

Return true if ctlz instruction is fast.

Definition PPCISelLowering.h:234

bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const override

Returns true if an argument of type Ty needs to be passed in a contiguous block of registers in calli...

Definition PPCISelLowering.h:543

bool isSelectSupported(SelectSupportKind Kind) const override

Definition PPCISelLowering.h:181

SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const

bool isCheapToSpeculateCttz(Type *Ty) const override

Return true if it is cheap to speculate a call to intrinsic cttz.

Definition PPCISelLowering.h:221

bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, std::optional< CallingConv::ID > CC) const override

Target-specific splitting of values into parts that fit a register storing a legal type.

void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override

LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.

void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...

bool hasMultipleConditionRegisters(EVT VT) const override

Does the target have multiple (allocatable) condition registers that can be used to store the results...

TargetLowering::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.

Align getByValTypeAlignment(Type *Ty, const DataLayout &DL) const override

getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the ca...

bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG, MaybeAlign EncodingAlignment=std::nullopt) const

SelectAddressRegReg - Given the specified addressed, check to see if it can be more efficiently repre...

MachineBasicBlock * EmitAtomicBinary(MachineInstr &MI, MachineBasicBlock *MBB, unsigned AtomicSize, unsigned BinOpcode, unsigned CmpOpcode=0, unsigned CmpPred=0) const

bool hasAndNotCompare(SDValue) const override

Return true if the target should transform: (X & Y) == Y ---> (~X & Y) == 0 (X & Y) !...

Definition PPCISelLowering.h:242

SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode * > &Created) const override

Targets may override this function to provide custom SDIV lowering for power-of-2 denominators.

Value * emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override

Perform a store-conditional operation to Addr.

void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override

Determine which of the bits specified in Mask are known to be either zero or one and return them in t...

bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const

SelectAddressRegRegOnly - Given the specified addressed, force it to be represented as an indexed [r+...

bool useSoftFloat() const override

SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override

Returns relocation base for the given PIC jumptable.

Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const override

Perform a masked cmpxchg using a target-specific intrinsic.

ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override

Examine constraint string and operand type and determine a weight value.

bool enableAggressiveFMAFusion(EVT VT) const override

Return true if target always benefits from combining into FMA for a given value type.

Return the register ID of the name passed in.

bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override

Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...

InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const override

Definition PPCISelLowering.h:422

unsigned getJumpTableEncoding() const override

Return the entry encoding for a jump table in the current function.

bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override

isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...

bool preferIncOfAddToSubOfNot(EVT VT) const override

These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR...

bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override

Returns true if it is beneficial to convert a load of a constant to just the constant itself.

const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override

Returns a 0 terminated array of registers that can be safely used as scratch registers.

bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override

getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mod...

bool isProfitableToHoist(Instruction *I) const override

isProfitableToHoist - Check if it is profitable to hoist instruction I to its dominator block.

bool convertSelectOfConstantsToMath(EVT VT) const override

Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...

Definition PPCISelLowering.h:471

bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override

Returns true if the target can instruction select the specified FP immediate natively.

bool convertSetCCLogicToBitwiseLogic(EVT VT) const override

Use bitwise logic to make pairs of compares more efficient.

Definition PPCISelLowering.h:248

Value * emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const override

Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.

ConstraintType getConstraintType(StringRef Constraint) const override

getConstraintType - Given a constraint, return the type of constraint it is for this target.

const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override

This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase,...

bool shallExtractConstSplatVectorElementToStore(Type *VectorTy, unsigned ElemSizeInBits, unsigned &Index) const override

Return true if the target shall perform extract vector element and store given that the vector is kno...

bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override

Return true if it is profitable for dag combiner to transform a floating point op of specified opcode...

Definition PPCISelLowering.h:478

bool isEqualityCmpFoldedWithSignedCmp() const override

Return true if instruction generated for equality comparison is folded with instruction generated for...

Definition PPCISelLowering.h:238

TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override

getPreferredVectorAction - The code we generate when vector types are legalized by promoting the inte...

Definition PPCISelLowering.h:194

EVT getOptimalMemOpType(LLVMContext &Context, const MemOp &Op, const AttributeList &FuncAttributes) const override

It returns EVT::Other if the type should be determined using generic target-independent logic.

SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override

This method will be invoked for all target nodes and for any target-independent nodes that the target...

SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const

void CollectTargetIntrinsicOperands(const CallInst &I, SmallVectorImpl< SDValue > &Ops, SelectionDAG &DAG) const override

unsigned getStackProbeSize(const MachineFunction &MF) const

PPCTargetLowering(const PPCTargetMachine &TM, const PPCSubtarget &STI)

TargetLowering::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.

bool useLoadStackGuardNode(const Module &M) const override

Override to support customized stack guard loading.

bool shouldKeepZExtForFP16Conv() const override

Does this target require the clearing of high-order bits in a register passed to the fp16 to fp conve...

Definition PPCISelLowering.h:534

bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override

isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster than a pair of fmul and fadd i...

bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override

Is unaligned memory access allowed for the given type, and is it fast relative to software emulation.

bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override

bool SelectAddressRegImm34(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG) const

Similar to the 16-bit case but for instructions that take a 34-bit displacement field (prefixed loads...

std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override

Given a physical register constraint (e.g.

If a physical register, this returns the register that receives the exception typeid on entry to a la...

bool isJumpTableRelative() const override

If a physical register, this returns the register that receives the exception address on entry to an ...

SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override

LowerOperation - Provide custom lowering hooks for some operations.

PPC::AddrMode SelectOptimalAddrMode(const SDNode *Parent, SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG, MaybeAlign Align) const

SelectOptimalAddrMode - Based on a node N and it's Parent (a MemSDNode), compute the address flags of...

bool SelectAddressPCRel(SDValue N, SDValue &Base) const

SelectAddressPCRel - Represent the specified address as pc relative to be represented as [pc+imm].

EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override

getSetCCResultType - Return the ISD::SETCC ValueType

bool SelectAddressEVXRegReg(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const

SelectAddressEVXRegReg - Given the specified addressed, check to see if it can be more efficiently re...

bool isLegalICmpImmediate(int64_t Imm) const override

isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate,...

bool isAccessedAsGotIndirect(SDValue N) const

Align getPrefLoopAlignment(MachineLoop *ML) const override

Return the preferred loop alignment.

FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) const override

createFastISel - This method returns a target-specific FastISel object, or null if the target does no...

bool shouldInlineQuadwordAtomics() const

Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override

Inserts in the IR a target-specific intrinsic specifying a fence.

bool isLegalAddImmediate(int64_t Imm) const override

isLegalAddImmediate - Return true if the specified immediate is legal add immediate,...

Common code between 32-bit and 64-bit PowerPC targets.

Wrapper class representing virtual and physical registers.

Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...

Represents one node in the SelectionDAG.

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

StringRef - Represent a constant reference to a string, i.e.

Provides information about what library functions are available for the current target.

LegalizeTypeAction

This enum indicates whether a types are legal for a target, and if not, what action should be used to...

SelectSupportKind

Enum that describes what type of support for selects the target has.

virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const

Return the preferred vector type legalization action.

Sched::Preference getSchedulingPreference() const

Return target scheduling preference.

AtomicExpansionKind

Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.

NegatibleCost

Enum that specifies when a float negation is beneficial.

virtual InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const

TargetLowering(const TargetLowering &)=delete

virtual unsigned combineRepeatedFPDivisors() const

Indicate whether this target prefers to combine FDIVs with the same divisor.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

The instances of the Type class are immutable: once they are created, they are never changed.

LLVM Value Representation.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ Fast

Attempts to make calls as fast as possible (e.g.

@ C

The default llvm calling convention, compatible with C.

MemIndexedMode

MemIndexedMode enum - This enum defines the load / store indexed addressing modes.

LoadExtType

LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).

This namespace contains an enum with a value for every intrinsic/builtin function known by LLVM.

Define some predicates that are used for node matching.

SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG)

get_VSPLTI_elt - If this is a build_vector of constants which can be formed by using a vspltis[bhw] i...

bool isXXBRDShuffleMask(ShuffleVectorSDNode *N)

isXXBRDShuffleMask - Return true if this is a shuffle mask suitable for a XXBRD instruction.

FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo)

bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)

isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VRGH* instruction with the ...

bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)

isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a VPKUDUM instruction.

bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven, unsigned ShuffleKind, SelectionDAG &DAG)

isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for a VMRGEW or VMRGOW instructi...

AddrMode

Definition PPCISelLowering.h:163

@ AM_DForm

Definition PPCISelLowering.h:165

@ AM_None

Definition PPCISelLowering.h:164

@ AM_DQForm

Definition PPCISelLowering.h:167

@ AM_PrefixDForm

Definition PPCISelLowering.h:168

@ AM_XForm

Definition PPCISelLowering.h:169

@ AM_PCRel

Definition PPCISelLowering.h:170

@ AM_DSForm

Definition PPCISelLowering.h:166

bool isXXBRQShuffleMask(ShuffleVectorSDNode *N)

isXXBRQShuffleMask - Return true if this is a shuffle mask suitable for a XXBRQ instruction.

bool isXXBRWShuffleMask(ShuffleVectorSDNode *N)

isXXBRWShuffleMask - Return true if this is a shuffle mask suitable for a XXBRW instruction.

bool isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, bool &Swap, bool IsLE)

isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable for a XXPERMDI instruction.

bool isXXBRHShuffleMask(ShuffleVectorSDNode *N)

isXXBRHShuffleMask - Return true if this is a shuffle mask suitable for a XXBRH instruction.

unsigned getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize, SelectionDAG &DAG)

getSplatIdxForPPCMnemonics - Return the splat index as a value that is appropriate for PPC mnemonics ...

bool isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, bool &Swap, bool IsLE)

isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable for a XXSLDWI instruction.

int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)

isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift amount, otherwise return -1.

bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)

isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VRGL* instruction with the ...

MemOpFlags

Definition PPCISelLowering.h:128

@ MOF_SubtargetP10

Definition PPCISelLowering.h:158

@ MOF_ScalarFloat

Definition PPCISelLowering.h:151

@ MOF_None

Definition PPCISelLowering.h:129

@ MOF_RPlusSImm16Mult16

Definition PPCISelLowering.h:141

@ MOF_ZExt

Definition PPCISelLowering.h:133

@ MOF_NotAddNorCst

Definition PPCISelLowering.h:137

@ MOF_RPlusSImm16

Definition PPCISelLowering.h:138

@ MOF_NoExt

Definition PPCISelLowering.h:134

@ MOF_Vector

Definition PPCISelLowering.h:152

@ MOF_Vector256

Definition PPCISelLowering.h:153

@ MOF_SubtargetBeforeP9

Definition PPCISelLowering.h:156

@ MOF_DoubleWordInt

Definition PPCISelLowering.h:150

@ MOF_PCRel

Definition PPCISelLowering.h:144

@ MOF_RPlusR

Definition PPCISelLowering.h:143

@ MOF_SubWordInt

Definition PPCISelLowering.h:148

@ MOF_RPlusSImm34

Definition PPCISelLowering.h:142

@ MOF_RPlusSImm16Mult4

Definition PPCISelLowering.h:140

@ MOF_SExt

Definition PPCISelLowering.h:132

@ MOF_AddrIsSImm32

Definition PPCISelLowering.h:145

@ MOF_SubtargetP9

Definition PPCISelLowering.h:157

@ MOF_RPlusLo

Definition PPCISelLowering.h:139

@ MOF_WordInt

Definition PPCISelLowering.h:149

@ MOF_SubtargetSPE

Definition PPCISelLowering.h:159

bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, unsigned &InsertAtByte, bool &Swap, bool IsLE)

isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by the XXINSERTW instruction intr...

bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize)

isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a singl...

bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)

isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a VPKUWUM instruction.

bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)

isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a VPKUHUM instruction.

This is an optimization pass for GlobalISel generic memory operations.

bool checkConvertToNonDenormSingle(APFloat &ArgAPFloat)

bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, Type *OrigTy, CCState &State)

CCAssignFn - This function assigns a location for Val, updating State to reflect the change.

bool isIntS16Immediate(SDNode *N, int16_t &Imm)

isIntS16Immediate - This method tests to see if the node is either a 32-bit or 64-bit immediate,...

bool convertToNonDenormSingle(APInt &ArgAPInt)

class LLVM_GSL_OWNER SmallVector

Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...

AtomicOrdering

Atomic ordering for LLVM's memory model.

bool isIntS34Immediate(SDNode *N, int64_t &Imm)

isIntS34Immediate - This method tests if value of node given can be accurately represented as a sign ...

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

DWARFExpression::Operation Op

A collection of metadata nodes that might be associated with a memory access used by the alias-analys...

This struct is a compact representation of a valid (non-zero power of two) alignment.

bool isScalarInteger() const

Return true if this is an integer, but not a vector.

This class contains a discriminated union of information about pointers in memory operands,...

This struct is a compact representation of a valid (power of two) or undefined (0) alignment.

Structure that collects some common arguments that get passed around between the functions for call l...

Definition PPCISelLowering.h:598

const bool IsPatchPoint

Definition PPCISelLowering.h:602

const bool IsIndirect

Definition PPCISelLowering.h:603

const bool IsVarArg

Definition PPCISelLowering.h:601

const bool HasNest

Definition PPCISelLowering.h:604

const bool NoMerge

Definition PPCISelLowering.h:605

CallFlags(CallingConv::ID CC, bool IsTailCall, bool IsVarArg, bool IsPatchPoint, bool IsIndirect, bool HasNest, bool NoMerge)

Definition PPCISelLowering.h:607

const bool IsTailCall

Definition PPCISelLowering.h:600

const CallingConv::ID CallConv

Definition PPCISelLowering.h:599