PPCInstPrinter.cpp Source File (original) (raw)

27using namespace llvm;

29#define DEBUG_TYPE "asm-printer"

35 cl::desc("Use full register names when printing assembly"));

40 cl::desc("Prints full register names with vs{31-63} as v{0-31}"));

46 cl::desc("Prints full register names with percent"));

48#define PRINT_ALIAS_INSTR

49#include "PPCGenAsmWriter.inc"

63 if (TT.isOSAIX() &&

64 (MI->getOpcode() == PPC::ADDIS8 || MI->getOpcode() == PPC::ADDIS) &&

65 MI->getOperand(2).isExpr()) {

66 assert((MI->getOperand(0).isReg() && MI->getOperand(1).isReg()) &&

67 "The first and the second operand of an addis instruction"

68 " should be registers.");

71 "The third operand of an addis instruction should be a symbol "

72 "reference expression if it is an expression at all.");

74 O << "\taddis ";

76 O << ", ";

78 O << "(";

80 O << ")";

81 return;

82 }

87 unsigned LastOp = MI->getNumOperands() - 1;

88 if (MI->getNumOperands() > 1) {

89 const MCOperand &Operand = MI->getOperand(LastOp);

90 if (Operand.isExpr()) {

97 if (MI->getOpcode() == PPC::PLDpc) {

99 O << "\n";

100 Symbol.print(O, &MAI);

101 O << ":";

102 return;

103 } else {

104 O << "\t.reloc ";

105 Symbol.print(O, &MAI);

106 O << "-8,R_PPC64_PCREL_OPT,.-(";

107 Symbol.print(O, &MAI);

108 O << "-8)\n";

109 }

110 }

111 }

112 }

113

114

115 if (MI->getOpcode() == PPC::RLWINM) {

116 unsigned char SH = MI->getOperand(2).getImm();

117 unsigned char MB = MI->getOperand(3).getImm();

118 unsigned char ME = MI->getOperand(4).getImm();

119 bool useSubstituteMnemonic = false;

120 if (SH <= 31 && MB == 0 && ME == (31-SH)) {

121 O << "\tslwi "; useSubstituteMnemonic = true;

122 }

123 if (SH <= 31 && MB == (32-SH) && ME == 31) {

124 O << "\tsrwi "; useSubstituteMnemonic = true;

125 SH = 32-SH;

126 }

127 if (useSubstituteMnemonic) {

129 O << ", ";

131 O << ", " << (unsigned int)SH;

132

134 return;

135 }

136 }

137

138 if (MI->getOpcode() == PPC::RLDICR ||

139 MI->getOpcode() == PPC::RLDICR_32) {

140 unsigned char SH = MI->getOperand(2).getImm();

141 unsigned char ME = MI->getOperand(3).getImm();

142

143 if (63-SH == ME) {

144 O << "\tsldi ";

146 O << ", ";

148 O << ", " << (unsigned int)SH;

150 return;

151 }

152 }

153

154

155

156

157

158

159

160

161

162

163

164 if ((MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) &&

165 (!TT.isOSAIX() || STI.hasFeature(PPC::FeatureModernAIXAs))) {

166 unsigned char TH = MI->getOperand(0).getImm();

167 O << "\tdcbt";

168 if (MI->getOpcode() == PPC::DCBTST)

169 O << "st";

170 if (TH == 16)

171 O << "t";

172 O << " ";

173

174 bool IsBookE = STI.hasFeature(PPC::FeatureBookE);

175 if (IsBookE && TH != 0 && TH != 16)

176 O << (unsigned int) TH << ", ";

177

179 O << ", ";

181

182 if (!IsBookE && TH != 0 && TH != 16)

183 O << ", " << (unsigned int) TH;

184

186 return;

187 }

188

189 if (MI->getOpcode() == PPC::DCBF) {

190 unsigned char L = MI->getOperand(0).getImm();

191 if (!L || L == 1 || L == 3 || L == 4 || L == 6) {

192 O << "\tdcb";

193 if (L != 6)

194 O << "f";

195 if (L == 1)

196 O << "l";

197 if (L == 3)

198 O << "lp";

199 if (L == 4)

200 O << "ps";

201 if (L == 6)

202 O << "stps";

203 O << " ";

204

206 O << ", ";

208

210 return;

211 }

212 }

213

217}

218

222 unsigned Code = MI->getOperand(OpNo).getImm();

223

224 if (Modifier == "cc") {

229 O << "lt";

230 return;

234 O << "le";

235 return;

239 O << "eq";

240 return;

244 O << "ge";

245 return;

249 O << "gt";

250 return;

254 O << "ne";

255 return;

259 O << "un";

260 return;

264 O << "nu";

265 return;

269 }

271 }

272

273 if (Modifier == "pm") {

283 return;

292 O << "-";

293 return;

302 O << "+";

303 return;

307 }

309 }

310

311 assert(Modifier == "reg" &&

312 "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");

314}

315

319 unsigned Code = MI->getOperand(OpNo).getImm();

320 if (Code == 2)

321 O << "-";

322 else if (Code == 3)

323 O << "+";

324}

325

329 unsigned int Value = MI->getOperand(OpNo).getImm();

330 assert(Value <= 1 && "Invalid u1imm argument!");

331 O << (unsigned int)Value;

332}

333

337 unsigned int Value = MI->getOperand(OpNo).getImm();

338 assert(Value <= 3 && "Invalid u2imm argument!");

339 O << (unsigned int)Value;

340}

341

345 unsigned int Value = MI->getOperand(OpNo).getImm();

346 assert(Value <= 8 && "Invalid u3imm argument!");

347 O << (unsigned int)Value;

348}

349

353 unsigned int Value = MI->getOperand(OpNo).getImm();

354 assert(Value <= 15 && "Invalid u4imm argument!");

355 O << (unsigned int)Value;

356}

357

361 int Value = MI->getOperand(OpNo).getImm();

364}

365

369 unsigned int Value = MI->getOperand(OpNo).getImm();

370 assert(Value == 0 && "Operand must be zero");

371 O << (unsigned int)Value;

372}

373

377 unsigned int Value = MI->getOperand(OpNo).getImm();

378 assert(Value <= 31 && "Invalid u5imm argument!");

379 O << (unsigned int)Value;

380}

381

385 unsigned int Value = MI->getOperand(OpNo).getImm();

386 assert(Value <= 63 && "Invalid u6imm argument!");

387 O << (unsigned int)Value;

388}

389

393 unsigned int Value = MI->getOperand(OpNo).getImm();

394 assert(Value <= 127 && "Invalid u7imm argument!");

395 O << (unsigned int)Value;

396}

397

398

399

400

404 unsigned char Value = MI->getOperand(OpNo).getImm();

405 O << (unsigned int)Value;

406}

407

411 unsigned short Value = MI->getOperand(OpNo).getImm();

412 assert(Value <= 1023 && "Invalid u10imm argument!");

413 O << (unsigned short)Value;

414}

415

419 unsigned short Value = MI->getOperand(OpNo).getImm();

420 assert(Value <= 4095 && "Invalid u12imm argument!");

421 O << (unsigned short)Value;

422}

423

427 if (MI->getOperand(OpNo).isImm())

428 O << (short)MI->getOperand(OpNo).getImm();

429 else

431}

432

436 if (MI->getOperand(OpNo).isImm()) {

437 long long Value = MI->getOperand(OpNo).getImm();

439 O << (long long)Value;

440 } else

442}

443

447 if (MI->getOperand(OpNo).isImm()) {

448 long long Value = MI->getOperand(OpNo).getImm();

450 O << (long long)Value;

451 }

452 else

454}

455

459 if (MI->getOperand(OpNo).isImm())

460 O << (unsigned short)MI->getOperand(OpNo).getImm();

461 else

463}

464

466 unsigned OpNo,

469 if (->getOperand(OpNo).isImm())

471 int32_t Imm = SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);

474 if (!TT.isPPC64())

475 Target &= 0xffffffff;

477 } else {

478

479

480

481 if (!TT.isOSAIX())

482 O << ".";

483 else

484 O << "$";

485

486 if (Imm >= 0)

487 O << "+";

488 O << Imm;

489 }

490}

491

495 if (->getOperand(OpNo).isImm())

497

499 if (!TT.isPPC64())

500 Imm = static_cast<uint32_t>(Imm);

502}

503

506 MCRegister CCReg = MI->getOperand(OpNo).getReg();

507 unsigned RegNo;

508 switch (CCReg.id()) {

510 case PPC::CR0: RegNo = 0; break;

511 case PPC::CR1: RegNo = 1; break;

512 case PPC::CR2: RegNo = 2; break;

513 case PPC::CR3: RegNo = 3; break;

514 case PPC::CR4: RegNo = 4; break;

515 case PPC::CR5: RegNo = 5; break;

516 case PPC::CR6: RegNo = 6; break;

517 case PPC::CR7: RegNo = 7; break;

518 }

519 O << (0x80 >> RegNo);

520}

521

526 O << '(';

527 if (MI->getOperand(OpNo+1).getReg() == PPC::R0)

528 O << "0";

529 else

531 O << ')';

532}

533

537 O << MI->getOperand(OpNo).getImm();

538 O << '(';

540 O << ')';

541}

542

547 O << '(';

549 O << ')';

550}

551

556 O << '(';

558 O << ')';

559}

560

564

565

566

567 if (MI->getOperand(OpNo).getReg() == PPC::R0)

568 O << "0";

569 else

571 O << ", ";

573}

574

577

578

581 const MCExpr *Rhs = nullptr;

584 Rhs = BinExpr->getRHS();

585 } else

587

589

590

591

592

594 O << '@' << MAI.getSpecifierName(RefExp->getKind());

595 O << '(';

597 O << ')';

600 O << '@' << MAI.getSpecifierName(RefExp->getKind());

601 if (Rhs) {

604 MAI.printExpr(Tmp, *Rhs);

605 if (isdigit(Buf[0]))

606 O << '+';

607 O << Buf;

608 }

609}

610

611

612

613bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const {

616 return false;

617

619 default:

620 return false;

621 case 'r':

622 case 'f':

623 case 'q':

624 case 'v':

625 case 'c':

626 return true;

627 }

628}

629

630

631

632const char *

633PPCInstPrinter::getVerboseConditionRegName(MCRegister Reg,

634 unsigned RegEncoding) const {

636 return nullptr;

638 return nullptr;

639 const char *CRBits[] = {

640 "lt", "gt", "eq", "un",

641 "4*cr1+lt", "4*cr1+gt", "4*cr1+eq", "4*cr1+un",

642 "4*cr2+lt", "4*cr2+gt", "4*cr2+eq", "4*cr2+un",

643 "4*cr3+lt", "4*cr3+gt", "4*cr3+eq", "4*cr3+un",

644 "4*cr4+lt", "4*cr4+gt", "4*cr4+eq", "4*cr4+un",

645 "4*cr5+lt", "4*cr5+gt", "4*cr5+eq", "4*cr5+un",

646 "4*cr6+lt", "4*cr6+gt", "4*cr6+eq", "4*cr6+un",

647 "4*cr7+lt", "4*cr7+gt", "4*cr7+eq", "4*cr7+un"

648 };

649 return CRBits[RegEncoding];

650}

651

652

653

654bool PPCInstPrinter::showRegistersWithPrefix() const {

656}

657

661 if (Op.isReg()) {

665

667 RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg));

670 if (showRegistersWithPercentPrefix(RegName))

671 O << "%";

672 if (!showRegistersWithPrefix())

674

676 return;

677 }

678

679 if (Op.isImm()) {

680 O << Op.getImm();

681 return;

682 }

683

684 assert(Op.isExpr() && "unknown operand kind in printOperand");

685 MAI.printExpr(O, *Op.getExpr());

686}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static cl::opt< bool > ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false), cl::desc("Prints full register names with vs{31-63} as v{0-31}"))

static cl::opt< bool > FullRegNamesWithPercent("ppc-reg-with-percent-prefix", cl::Hidden, cl::init(false), cl::desc("Prints full register names with percent"))

static cl::opt< bool > FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false), cl::desc("Use full register names when printing assembly"))

bool useFullRegisterNames() const

Binary assembler expressions.

Base class for the full range of assembler expressions which are needed for parsing.

format_object< int64_t > formatHex(int64_t Value) const

const MCRegisterInfo & MRI

void printAnnotation(raw_ostream &OS, StringRef Annot)

Utility function for printing annotations.

bool PrintBranchImmAsAddress

If true, a branch immediate (e.g.

Instances of this class represent a single low-level machine instruction.

Instances of this class represent operands of the MCInst class.

const MCExpr * getExpr() const

Wrapper class representing physical registers. Should be passed by value.

constexpr unsigned id() const

Generic base class for all target subtargets.

bool hasFeature(unsigned Feature) const

Represent a reference to a symbol from inside an expression.

const MCSymbol & getSymbol() const

VariantKind getKind() const

MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...

StringRef getName() const

getName - Get the symbol name.

void printMemRegImm34PCRel(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition PPCInstPrinter.cpp:543

void printcrbitm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition PPCInstPrinter.cpp:504

void printU6ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition PPCInstPrinter.cpp:382

void printS32ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition PPCInstPrinter.cpp:433

bool printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS)

void printMemRegReg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition PPCInstPrinter.cpp:561

void printU1ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition PPCInstPrinter.cpp:326

void printPredicateOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O, StringRef Modifier={})

Definition PPCInstPrinter.cpp:219

void printU4ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition PPCInstPrinter.cpp:350

void printS34ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition PPCInstPrinter.cpp:444

void printS16ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition PPCInstPrinter.cpp:424

void printRegName(raw_ostream &OS, MCRegister Reg) override

Print the assembler register name.

Definition PPCInstPrinter.cpp:51

void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition PPCInstPrinter.cpp:658

void printU12ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition PPCInstPrinter.cpp:416

void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override

Print the specified MCInst to the specified raw_ostream.

Definition PPCInstPrinter.cpp:56

void printU5ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition PPCInstPrinter.cpp:374

void printMemRegImm34(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition PPCInstPrinter.cpp:552

void printU7ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition PPCInstPrinter.cpp:390

static const char * getRegisterName(MCRegister Reg)

void printU16ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition PPCInstPrinter.cpp:456

void printMemRegImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition PPCInstPrinter.cpp:522

void printImmZeroOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition PPCInstPrinter.cpp:366

void printATBitsAsHint(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition PPCInstPrinter.cpp:316

void printAbsBranchOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition PPCInstPrinter.cpp:492

void printBranchOperand(const MCInst *MI, uint64_t Address, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition PPCInstPrinter.cpp:465

void printU3ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition PPCInstPrinter.cpp:342

void printU8ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition PPCInstPrinter.cpp:401

void printTLSCall(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition PPCInstPrinter.cpp:575

void printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O)

void printS5ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition PPCInstPrinter.cpp:358

void printMemRegImmHash(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition PPCInstPrinter.cpp:534

void printU2ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition PPCInstPrinter.cpp:334

void printU10ImmOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)

Definition PPCInstPrinter.cpp:408

SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...

StringRef - Represent a constant reference to a string, i.e.

OSType getOS() const

Get the parsed operating system type of this triple.

LLVM Value Representation.

This class implements an extremely fast bulk output stream that can only output to a stream.

A raw_ostream that writes to an SmallVector or SmallString.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

Predicate

Predicate - These are "(BI << 5) | BO" for various predicates.

const char * stripRegisterPrefix(const char *RegName)

stripRegisterPrefix - This method strips the character prefix from a register name so that only the n...

MCRegister getRegNumForOperand(const MCInstrDesc &Desc, MCRegister Reg, unsigned OpNo)

getRegNumForOperand - some operands use different numbering schemes for the same registers.

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

constexpr bool isInt(int64_t x)

Checks if an integer fits into the given bit width.

decltype(auto) dyn_cast(const From &Val)

dyn_cast - Return the argument parameter cast to the specified type.

MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)

bool isa(const From &Val)

isa - Return true if the parameter to the template is an instance of one of the template type argu...

DWARFExpression::Operation Op

constexpr int32_t SignExtend32(uint32_t X)

Sign-extend the number in the bottom B bits of X to a 32-bit integer.

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

static uint16_t getSpecifier(const MCSymbolRefExpr *SRE)