PPCTargetMachine.cpp Source File (original) (raw)

46#include

47#include

48#include

49#include

51using namespace llvm;

56 cl::desc("enable coalescing of duplicate branches for PPC"));

59 cl::desc("Disable CTR loops for PPC"));

63 cl::desc("Disable PPC loop instr form prep"));

71 cl::desc("Disable VSX Swap Removal for PPC"));

75 cl::desc("Disable machine peepholes for PPC"));

79 cl::desc("Enable optimizations on complex GEPs"),

84 cl::desc("enable software prefetching on PPC"),

89 cl::desc("Add extra TOC register dependencies"),

94 cl::desc("Enable the machine combiner pass"),

99 cl::desc("Expand eligible cr-logical binary ops to branches"),

101

103 "enable-ppc-gen-scalar-mass", cl::init(false),

104 cl::desc("Enable lowering math functions to their corresponding MASS "

105 "(scalar) entries"),

107

110 cl::desc("Enable the global merge pass"));

111

115 cl::desc("Maximum global merge offset"));

116

119

124

126#ifndef NDEBUG

128#endif

150}

151

154 std::string FullFS = std::string(FS);

155

156

158 if (!FullFS.empty())

159 FullFS = "+64bit," + FullFS;

160 else

161 FullFS = "+64bit";

162 }

163

165 if (!FullFS.empty())

166 FullFS = "+crbits," + FullFS;

167 else

168 FullFS = "+crbits";

169 }

170

172 if (!FullFS.empty())

173 FullFS = "+invariant-function-descriptors," + FullFS;

174 else

175 FullFS = "+invariant-function-descriptors";

176 }

177

178 if (TT.isOSAIX()) {

179 if (!FullFS.empty())

180 FullFS = "+aix," + FullFS;

181 else

182 FullFS = "+aix";

183 }

184

185 return FullFS;

186}

187

188static std::unique_ptr createTLOF(const Triple &TT) {

189 if (TT.isOSAIX())

190 return std::make_unique();

191

192 return std::make_unique();

193}

194

197 if (Options.MCOptions.getABIName().starts_with("elfv1"))

199 else if (Options.MCOptions.getABIName().starts_with("elfv2"))

201

203 "Unknown target-abi option!");

204

205 switch (TT.getArch()) {

209 if (TT.isPPC64ELFv2ABI())

211 else

213 default:

215 }

216}

217

219 std::optionalReloc::Model RM) {

220 if (TT.isOSAIX() && RM && *RM != Reloc::PIC_)

221 report_fatal_error("invalid relocation model, AIX only supports PIC",

222 false);

223

224 if (RM)

225 return *RM;

226

227

228 if (TT.getArch() == Triple::ppc64 || TT.isOSAIX())

230

231

233}

234

237 bool JIT) {

238 if (CM) {

240 report_fatal_error("Target does not support the tiny CodeModel", false);

242 report_fatal_error("Target does not support the kernel CodeModel", false);

243 return *CM;

244 }

245

246 if (JIT)

248 if (TT.isOSAIX())

250

251 assert(TT.isOSBinFormatELF() && "All remaining PPC OSes are ELF based.");

252

253 if (TT.isArch32Bit())

255

256 assert(TT.isArch64Bit() && "Unsupported PPC architecture.");

258}

259

260

266

267 if (ST.hasStoreFusion())

269 if (ST.hasFusion())

271

272 return DAG;

273}

274

278 ScheduleDAGMI *DAG = ST.usePPCPostRASchedStrategy()

281

282 if (ST.hasStoreFusion())

284 if (ST.hasFusion())

286 return DAG;

287}

288

289

290

291

292

296 std::optionalReloc::Model RM,

297 std::optionalCodeModel::Model CM,

300 TT.computeDataLayout(Options.MCOptions.ABIName),

308}

309

311

314 Attribute CPUAttr = F.getFnAttribute("target-cpu");

315 Attribute TuneAttr = F.getFnAttribute("tune-cpu");

316 Attribute FSAttr = F.getFnAttribute("target-features");

317

318 std::string CPU =

320 std::string TuneCPU =

322 std::string FS =

324

325

326

327

328

329

330 bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();

331

332

333 if (SoftFloat)

334 FS += FS.empty() ? "-hard-float" : ",-hard-float";

335

336 auto &I = SubtargetMap[CPU + TuneCPU + FS];

337 if () {

338

339

340

342 I = std::make_unique(

344

345

346

347

348

349

351 }

352 return I.get();

353}

354

359

364

365

366

367

368

369namespace {

370

371

373public:

376

377

380 }

381

384 }

385

386 void addIRPasses() override;

387 bool addPreISel() override;

388 bool addILPOpts() override;

389 bool addInstSelector() override;

390 void addMachineSSAOptimization() override;

391 void addPreRegAlloc() override;

392 void addPreSched2() override;

393 void addPreEmitPass() override;

394 void addPreEmitPass2() override;

395

396 bool addIRTranslator() override;

397 bool addLegalizeMachineIR() override;

398 bool addRegBankSelect() override;

399 bool addGlobalInstructionSelect() override;

400};

401

402}

403

405 return new PPCPassConfig(*this, PM);

406}

407

408void PPCPassConfig::addIRPasses() {

412

413

415

416

417

422 }

423

424

427

429

430

431

433

434

436

437

439 }

440

442}

443

444bool PPCPassConfig::addPreISel() {

445

446

451 true));

452

455

458

459 return false;

460}

461

462bool PPCPassConfig::addILPOpts() {

464

467

468 return true;

469}

470

471bool PPCPassConfig::addInstSelector() {

472

473 addPass(createPPCISelDag(getPPCTargetMachine(), getOptLevel()));

474

475#ifndef NDEBUG

478#endif

479

481 return false;

482}

483

484void PPCPassConfig::addMachineSSAOptimization() {

485

486

489

490

491

495

496

497 if (TM->getTargetTriple().getArch() == Triple::ppc64le &&

500

503

504

508 }

509}

510

511void PPCPassConfig::addPreRegAlloc() {

516 }

517

518

519 if (getPPCTargetMachine().isPositionIndependent()) {

520

521

522

523

526 }

529

532}

533

534void PPCPassConfig::addPreSched2() {

537}

538

539void PPCPassConfig::addPreEmitPass() {

541

544}

545

546void PPCPassConfig::addPreEmitPass2() {

547

548

549

551

553}

554

559

562 "Unable to determine endianness");

564}

565

571

574 "Run PowerPC PreRA specific scheduler",

576

579 "Run PowerPC PostRA specific scheduler",

581

582

583bool PPCPassConfig::addIRTranslator() {

585 return false;

586}

587

588bool PPCPassConfig::addLegalizeMachineIR() {

590 return false;

591}

592

593bool PPCPassConfig::addRegBankSelect() {

595 return false;

596}

597

598bool PPCPassConfig::addGlobalInstructionSelect() {

600 return false;

601}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static cl::opt< bool > EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden, cl::desc("Enable optimizations on complex GEPs"), cl::init(false))

static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)

static Reloc::Model getEffectiveRelocModel()

This file contains the simple types necessary to represent the attributes associated with functions a...

static cl::opt< bool > DisableMIPeephole("disable-bpf-peephole", cl::Hidden, cl::desc("Disable machine peepholes for BPF"))

static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")

static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

#define LLVM_EXTERNAL_VISIBILITY

static cl::opt< unsigned > GlobalMergeMaxOffset("global-merge-max-offset", cl::Hidden, cl::desc("Set maximum offset for global merge pass"), cl::init(0))

static cl::opt< bool > EnableGlobalMerge("enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"), cl::init(true))

This file declares the IRTranslator pass.

static cl::opt< bool > VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early", cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"))

static cl::opt< bool > EnableMachineCombinerPass("ppc-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)

static MachineSchedRegistry PPCPostRASchedRegistry("ppc-postra", "Run PowerPC PostRA specific scheduler", createPPCPostMachineScheduler)

static cl::opt< bool > DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden, cl::desc("Disable CTR loops for PPC"))

static cl::opt< bool > DisableMIPeephole("disable-ppc-peephole", cl::Hidden, cl::desc("Disable machine peepholes for PPC"))

static cl::opt< bool > EnableExtraTOCRegDeps("enable-ppc-extra-toc-reg-deps", cl::desc("Add extra TOC register dependencies"), cl::init(true), cl::Hidden)

LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCTarget()

Definition PPCTargetMachine.cpp:118

static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT, const TargetOptions &Options)

Definition PPCTargetMachine.cpp:195

static cl::opt< bool > EnablePrefetch("enable-ppc-prefetching", cl::desc("enable software prefetching on PPC"), cl::init(false), cl::Hidden)

static cl::opt< bool > EnablePPCGenScalarMASSEntries("enable-ppc-gen-scalar-mass", cl::init(false), cl::desc("Enable lowering math functions to their corresponding MASS " "(scalar) entries"), cl::Hidden)

static cl::opt< bool > ReduceCRLogical("ppc-reduce-cr-logicals", cl::desc("Expand eligible cr-logical binary ops to branches"), cl::init(true), cl::Hidden)

static cl::opt< bool > EnableGEPOpt("ppc-gep-opt", cl::Hidden, cl::desc("Enable optimizations on complex GEPs"), cl::init(true))

static ScheduleDAGInstrs * createPPCPostMachineScheduler(MachineSchedContext *C)

Definition PPCTargetMachine.cpp:276

static CodeModel::Model getEffectivePPCCodeModel(const Triple &TT, std::optional< CodeModel::Model > CM, bool JIT)

Definition PPCTargetMachine.cpp:236

static cl::opt< bool > DisableInstrFormPrep("disable-ppc-instr-form-prep", cl::Hidden, cl::desc("Disable PPC loop instr form prep"))

static std::string computeFSAdditions(StringRef FS, CodeGenOptLevel OL, const Triple &TT)

Definition PPCTargetMachine.cpp:152

static MachineSchedRegistry PPCPreRASchedRegistry("ppc-prera", "Run PowerPC PreRA specific scheduler", createPPCMachineScheduler)

static cl::opt< unsigned > GlobalMergeMaxOffset("ppc-global-merge-max-offset", cl::Hidden, cl::init(0x7fff), cl::desc("Maximum global merge offset"))

static cl::opt< bool > DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden, cl::desc("Disable VSX Swap Removal for PPC"))

static cl::opt< bool > EnableBranchCoalescing("enable-ppc-branch-coalesce", cl::Hidden, cl::desc("enable coalescing of duplicate branches for PPC"))

static ScheduleDAGInstrs * createPPCMachineScheduler(MachineSchedContext *C)

Definition PPCTargetMachine.cpp:261

static cl::opt< bool > EnableGlobalMerge("ppc-global-merge", cl::Hidden, cl::init(false), cl::desc("Enable the global merge pass"))

This file a TargetTransformInfoImplBase conforming object specific to the PPC target machine.

This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...

const GCNTargetMachine & getTM(const GCNSubtarget *STI)

Target-Independent Code Generator Pass Configuration Options pass.

This pass exposes codegen information to IR-level passes.

static std::unique_ptr< TargetLoweringObjectFile > createTLOF()

Functions, function parameters, and return types can have attributes to indicate how they should be t...

LLVM_ABI StringRef getValueAsString() const

Return the attribute's value as a string.

bool isValid() const

Return true if the attribute is any kind of attribute.

CodeGenTargetMachineImpl(const Target &T, StringRef DataLayoutString, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOptLevel OL)

This pass is responsible for selecting generic machine instructions to target-specific instructions.

MachineSchedRegistry provides a selection of available machine instruction schedulers.

Common code between 32-bit and 64-bit PowerPC targets.

ScheduleDAGInstrs * createPostMachineScheduler(MachineSchedContext *C) const override

Similar to createMachineScheduler but used when postRA machine scheduling is enabled.

Definition PPCTargetMachine.cpp:361

const PPCSubtarget * getSubtargetImpl() const =delete

~PPCTargetMachine() override

bool isLittleEndian() const

Definition PPCTargetMachine.cpp:560

PPCTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)

Definition PPCTargetMachine.cpp:293

TargetTransformInfo getTargetTransformInfo(const Function &F) const override

Get a TargetTransformInfo implementation for the target.

Definition PPCTargetMachine.cpp:556

ScheduleDAGInstrs * createMachineScheduler(MachineSchedContext *C) const override

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this ...

Definition PPCTargetMachine.cpp:356

TargetPassConfig * createPassConfig(PassManagerBase &PM) override

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...

Definition PPCTargetMachine.cpp:404

MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override

Create the target's instance of MachineFunctionInfo.

Definition PPCTargetMachine.cpp:566

PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...

static LLVM_ABI PassRegistry * getPassRegistry()

getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...

This pass implements the reg bank selector pass used in the GlobalISel pipeline.

A ScheduleDAG for scheduling lists of MachineInstr.

ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...

ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...

StringRef - Represent a constant reference to a string, i.e.

std::string str() const

str - Get the contents as an std::string.

CodeGenOptLevel getOptLevel() const

Returns the optimization level: None, Less, Default, or Aggressive.

Triple TargetTriple

Triple string, CPU name, and target feature strings the TargetMachine instance is created with.

const Triple & getTargetTriple() const

std::unique_ptr< const MCSubtargetInfo > STI

void resetTargetOptions(const Function &F) const

Reset the target options based on the function's attributes.

Target-Independent Code Generator Pass Configuration Options.

virtual void addIRPasses()

Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...

virtual void addMachineSSAOptimization()

addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.

TargetSubtargetInfo - Generic base class for all target subtargets.

This pass provides access to the codegen interfaces that are needed for IR-level transformations.

Target - Wrapper for Target specific information.

Triple - Helper class for working with autoconf configuration names.

int getNumOccurrences() const

PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...

@ C

The default llvm calling convention, compatible with C.

template class LLVM_TEMPLATE_ABI opt< bool >

initializer< Ty > init(const Ty &Val)

This is an optimization pass for GlobalISel generic memory operations.

ScheduleDAGMILive * createSchedLive(MachineSchedContext *C)

Create the standard converging machine scheduler.

FunctionPass * createPPCPreEmitPeepholePass()

Target & getThePPC64LETarget()

void initializePPCTLSDynamicCallPass(PassRegistry &)

FunctionPass * createPPCLoopInstrFormPrepPass(PPCTargetMachine &TM)

void initializePPCVSXFMAMutatePass(PassRegistry &)

void initializePPCLowerMASSVEntriesPass(PassRegistry &)

LLVM_ABI Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false, bool MergeConstantByDefault=false, bool MergeConstAggressiveByDefault=false)

GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...

LLVM_ABI char & PostRASchedulerID

PostRAScheduler - This pass performs post register allocation scheduling.

Target & getThePPC32Target()

FunctionPass * createPPCCTRLoopsPass()

LLVM_ABI char & MachineSchedulerID

MachineScheduler - This pass schedules machine instructions.

FunctionPass * createPPCTLSDynamicCallPass()

LLVM_ABI char & PostMachineSchedulerID

PostMachineScheduler - This pass schedules machine instructions postRA.

LLVM_ABI Pass * createLICMPass()

FunctionPass * createPPCEarlyReturnPass()

void initializePPCPreEmitPeepholePass(PassRegistry &)

LLVM_ABI char & EarlyIfConverterLegacyID

EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.

FunctionPass * createPPCExpandAtomicPseudoPass()

void initializePPCTOCRegDepsPass(PassRegistry &)

void initializePPCReduceCRLogicalsPass(PassRegistry &)

LLVM_ABI char & MachineCombinerID

This pass performs instruction combining using trace metrics to estimate critical-path and resource d...

static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)

ScheduleDAGMI * createSchedPostRA(MachineSchedContext *C)

Create a generic scheduler with no vreg liveness or DAG mutation passes.

void initializePPCCTRLoopsVerifyPass(PassRegistry &)

FunctionPass * createPPCVSXSwapRemovalPass()

void initializePPCAIXAsmPrinterPass(PassRegistry &)

void initializePPCCTRLoopsPass(PassRegistry &)

ModulePass * createPPCLowerMASSVEntriesPass()

LLVM_ABI std::unique_ptr< ScheduleDAGMutation > createStoreClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ReorderWhileClustering=false)

If ReorderWhileClustering is set to true, no attempt will be made to reduce reordering due to store c...

LLVM_ABI FunctionPass * createLoopDataPrefetchPass()

LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)

void initializePPCDAGToDAGISelLegacyPass(PassRegistry &)

ModulePass * createPPCGenScalarMASSEntriesPass()

void initializePPCEarlyReturnPass(PassRegistry &)

CodeGenOptLevel

Code generation optimization level.

void initializePPCGenScalarMASSEntriesPass(PassRegistry &)

FunctionPass * createPPCReduceCRLogicalsPass()

FunctionPass * createPPCISelDag(PPCTargetMachine &TM, CodeGenOptLevel OL)

createPPCISelDag - This pass converts a legalized DAG into a PowerPC-specific DAG,...

void initializePPCExpandAtomicPseudoPass(PassRegistry &)

LLVM_ABI FunctionPass * createSeparateConstOffsetFromGEPPass(bool LowerGEP=false)

FunctionPass * createPPCBranchCoalescingPass()

createPPCBranchCoalescingPass - returns an instance of the Branch Coalescing Pass

Target & getThePPC64Target()

void initializePPCVSXWACCCopyPass(PassRegistry &)

void initializePPCLinuxAsmPrinterPass(PassRegistry &)

LLVM_ABI void initializeGlobalISel(PassRegistry &)

Initialize all passes linked into the GlobalISel library.

void initializePPCBSelPass(PassRegistry &)

LLVM_ABI char & MachinePipelinerID

This pass performs software pipelining on machine instructions.

FunctionPass * createPPCTOCRegDepsPass()

FunctionPass * createPPCCTRLoopsVerify()

void initializePPCBranchCoalescingPass(PassRegistry &)

void initializePPCBoolRetToIntPass(PassRegistry &)

void initializePPCMIPeepholePass(PassRegistry &)

std::unique_ptr< ScheduleDAGMutation > createPowerPCMacroFusionDAGMutation()

Note that you have to add: DAG.addMutation(createPowerPCMacroFusionDAGMutation()); to PPCTargetMachin...

void initializePPCVSXSwapRemovalPass(PassRegistry &)

LLVM_ABI char & LiveVariablesID

LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...

Target & getThePPC32LETarget()

LLVM_ABI char & IfConverterID

IfConverter - This pass performs machine code if conversion.

void initializePPCLoopInstrFormPrepPass(PassRegistry &)

FunctionPass * createPPCVSXWACCCopyPass()

LLVM_ABI char & TwoAddressInstructionPassID

TwoAddressInstruction - This pass reduces two-address instructions to use two operands.

LLVM_ABI FunctionPass * createAtomicExpandLegacyPass()

AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...

BumpPtrAllocatorImpl<> BumpPtrAllocator

The standard BumpPtrAllocator which just uses the default template parameters.

LLVM_ABI FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)

FunctionPass * createPPCBranchSelectionPass()

FunctionPass * createPPCBoolRetToIntPass()

LLVM_ABI char & DeadMachineInstructionElimID

DeadMachineInstructionElim - This pass removes dead machine instructions.

LLVM_ABI FunctionPass * createHardwareLoopsLegacyPass()

Create Hardware Loop pass.

FunctionPass * createPPCMIPeepholePass()

MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...

static FuncInfoTy * create(BumpPtrAllocator &Allocator, const Function &F, const SubtargetTy *STI)

Factory function: default behavior is to call new using the supplied allocator.

MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...

RegisterTargetMachine - Helper template for registering a target machine implementation,...