R600InstrInfo.h Source File (original) (raw)

14#ifndef LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H

15#define LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H

20#define GET_INSTRINFO_HEADER

21#define GET_INSTRINFO_OPERAND_ENUM

22#include "R600GenInstrInfo.inc"

24namespace llvm {

33class DFAPacketizer;

34class MachineFunction;

35class MachineInstr;

36class MachineInstrBuilder;

37class R600Subtarget;

40private:

44 std::vector<std::pair<int, unsigned>>

46 unsigned &ConstCount) const;

50 unsigned ValueReg, unsigned Address,

51 unsigned OffsetReg,

52 unsigned AddrChan) const;

56 unsigned ValueReg, unsigned Address,

57 unsigned OffsetReg,

58 unsigned AddrChan) const;

59public:

77 bool KillSrc, bool RenamableDest = false,

78 bool RenamableSrc = false) const override;

83 bool isCubeOp(unsigned opcode) const;

86 bool isALUInstr(unsigned Opcode) const;

88 bool isLDSInstr(unsigned Opcode) const;

99 bool isExport(unsigned Opcode) const;

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113 int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;

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124 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,

125 const std::vectorR600InstrInfo::BankSwizzle &Swz,

126 const std::vector<std::pair<int, unsigned> > &TransSrcs,

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130 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,

131 std::vectorR600InstrInfo::BankSwizzle &SwzCandidate,

132 const std::vector<std::pair<int, unsigned> > &TransSrcs,

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146 std::vector &BS,

147 bool isLastAluTrans) const;

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160 bool isMov(unsigned Opcode) const;

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171 bool AllowModify) const override;

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176 int *BytesAdded = nullptr) const override;

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179 int *BytesRemoved = nullptr) const override;

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189 unsigned ExtraPredCycles,

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193 unsigned NumTCycles, unsigned ExtraTCycles,

195 unsigned NumFCycles, unsigned ExtraFCycles,

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199 bool SkipDead) const override;

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211 unsigned *PredCost = nullptr) const override;

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247 unsigned ValueReg, unsigned Address,

248 unsigned OffsetReg) const;

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255 unsigned ValueReg, unsigned Address,

256 unsigned OffsetReg) const;

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269 unsigned Opcode,

270 unsigned DstReg,

271 unsigned Src0Reg,

272 unsigned Src1Reg = 0) const;

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276 unsigned Slot,

277 unsigned DstReg) const;

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281 unsigned DstReg,

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286 unsigned DstReg, unsigned SrcReg) const;

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296 int getOperandIdx(unsigned Opcode, R600::OpName Op) const;

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312 unsigned Flag = 0) const;

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325};

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333}

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335#endif

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

MachineBasicBlock MachineBasicBlock::iterator MBBI

Interface definition for R600RegisterInfo.

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

Itinerary data supplied by a subtarget to be used by a target.

MachineInstrBundleIterator< MachineInstr > iterator

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

bool usesVertexCache(unsigned Opcode) const

MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opcode, unsigned DstReg, unsigned Src0Reg, unsigned Src1Reg=0) const

buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers ini...

bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override

void addFlag(MachineInstr &MI, unsigned SrcIdx, unsigned Flag) const

Add one of the MO_FLAG* flags to the operand at SrcIdx.

bool usesAddressRegister(MachineInstr &MI) const

unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const

Calculate the "Indirect Address" for the given RegIndex and Channel.

bool hasInstrModifiers(unsigned Opcode) const

const R600RegisterInfo & getRegisterInfo() const

Definition R600InstrInfo.h:71

R600InstrInfo(const R600Subtarget &)

bool isMov(unsigned Opcode) const

bool isRegisterLoad(const MachineInstr &MI) const

Definition R600InstrInfo.h:322

int getIndirectIndexBegin(const MachineFunction &MF) const

bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override

bool usesTextureCache(unsigned Opcode) const

unsigned isLegalUpTo(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, const std::vector< R600InstrInfo::BankSwizzle > &Swz, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const

returns how many MIs (whose inputs are represented by IGSrcs) can be packed in the same Instruction G...

unsigned int getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override

const TargetRegisterClass * getIndirectAddrRegClass() const

void clearFlag(MachineInstr &MI, unsigned SrcIdx, unsigned Flag) const

Clear the specified flag on the instruction.

MachineInstr * buildMovImm(MachineBasicBlock &BB, MachineBasicBlock::iterator I, unsigned DstReg, uint64_t Imm) const

bool definesAddressRegister(MachineInstr &MI) const

unsigned getMaxAlusPerClause() const

bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override

int getOperandIdx(const MachineInstr &MI, R600::OpName Op) const

Get the index of Op in the MachineInstr.

bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override

bool canBeConsideredALU(const MachineInstr &MI) const

bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override

bool fitsConstReadLimitations(const std::vector< MachineInstr * > &) const

An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+.

bool isFlagSet(const MachineInstr &MI, unsigned SrcIdx, unsigned Flag) const

Determine if the specified Flag is set on operand at SrcIdx.

bool isVector(const MachineInstr &MI) const

Vector instructions are instructions that must fill all instruction slots within an instruction group...

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

bool mustBeLastInClause(unsigned Opcode) const

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

BankSwizzle

Definition R600InstrInfo.h:60

@ ALU_VEC_012_SCL_210

Definition R600InstrInfo.h:61

@ ALU_VEC_021_SCL_122

Definition R600InstrInfo.h:62

@ ALU_VEC_102_SCL_221

Definition R600InstrInfo.h:64

@ ALU_VEC_210

Definition R600InstrInfo.h:66

@ ALU_VEC_120_SCL_212

Definition R600InstrInfo.h:63

@ ALU_VEC_201

Definition R600InstrInfo.h:65

int getIndirectIndexEnd(const MachineFunction &MF) const

bool isTransOnly(unsigned Opcode) const

DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const override

bool isReductionOp(unsigned opcode) const

bool isRegisterStore(const MachineInstr &MI) const

Definition R600InstrInfo.h:318

bool isCubeOp(unsigned opcode) const

bool isLDSInstr(unsigned Opcode) const

void reserveIndirectRegisters(BitVector &Reserved, const MachineFunction &MF, const R600RegisterInfo &TRI) const

Reserve the registers that may be accessed using indirect addressing.

void setImmOperand(MachineInstr &MI, R600::OpName Op, int64_t Imm) const

Helper function for setting instruction flag values.

bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override

bool isPredicable(const MachineInstr &MI) const override

bool isPredicated(const MachineInstr &MI) const override

bool expandPostRAPseudo(MachineInstr &MI) const override

bool isLDSRetInstr(unsigned Opcode) const

int getSelIdx(unsigned Opcode, unsigned SrcIdx) const

MachineOperand & getFlagOp(MachineInstr &MI, unsigned SrcIdx=0, unsigned Flag=0) const

unsigned int getPredicationCost(const MachineInstr &) const override

MachineInstr * buildSlotOfVectorInstruction(MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg) const

bool readsLDSSrcReg(const MachineInstr &MI) const

bool FindSwizzleForVectorSlot(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const

Enumerate all possible Swizzle sequence to find one that can meet all read port requirements.

bool fitsReadPortLimitations(const std::vector< MachineInstr * > &MIs, const DenseMap< unsigned, unsigned > &PV, std::vector< BankSwizzle > &BS, bool isLastAluTrans) const

Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first ...

bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override

bool isALUInstr(unsigned Opcode) const

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

bool isVectorOnly(unsigned Opcode) const

bool isExport(unsigned Opcode) const

SmallVector< std::pair< MachineOperand *, int64_t >, 3 > getSrcs(MachineInstr &MI) const

MachineInstr * buildMovInstr(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const

Wrapper class representing virtual and physical registers.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

TargetSubtargetInfo - Generic base class for all target subtargets.

Definition R600InstrInfo.h:26

@ REGISTER_STORE

Definition R600InstrInfo.h:28

@ REGISTER_LOAD

Definition R600InstrInfo.h:29

Definition R600InstrInfo.h:327

int getLDSNoRetOp(uint16_t Opcode)

This is an optimization pass for GlobalISel generic memory operations.

decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)

DWARFExpression::Operation Op