LLVM: llvm::R600InstrInfo Class Reference (original) (raw)

#include "[Target/AMDGPU/R600InstrInfo.h](R600InstrInfo%5F8h%5Fsource.html)"

Public Member Functions
R600InstrInfo (const R600Subtarget &)
const R600RegisterInfo & getRegisterInfo () const
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
bool isLegalToSplitMBBAt (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override
bool isReductionOp (unsigned opcode) const
bool isCubeOp (unsigned opcode) const
bool isALUInstr (unsigned Opcode) const
bool hasInstrModifiers (unsigned Opcode) const
bool isLDSInstr (unsigned Opcode) const
bool isLDSRetInstr (unsigned Opcode) const
bool canBeConsideredALU (const MachineInstr &MI) const
bool isTransOnly (unsigned Opcode) const
bool isTransOnly (const MachineInstr &MI) const
bool isVectorOnly (unsigned Opcode) const
bool isVectorOnly (const MachineInstr &MI) const
bool isExport (unsigned Opcode) const
bool usesVertexCache (unsigned Opcode) const
bool usesVertexCache (const MachineInstr &MI) const
bool usesTextureCache (unsigned Opcode) const
bool usesTextureCache (const MachineInstr &MI) const
bool mustBeLastInClause (unsigned Opcode) const
bool usesAddressRegister (MachineInstr &MI) const
bool definesAddressRegister (MachineInstr &MI) const
bool readsLDSSrcReg (const MachineInstr &MI) const
int getSelIdx (unsigned Opcode, unsigned SrcIdx) const
SmallVector< std::pair< MachineOperand *, int64_t >, 3 > getSrcs (MachineInstr &MI) const
unsigned isLegalUpTo (const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, const std::vector< R600InstrInfo::BankSwizzle > &Swz, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
returns how many MIs (whose inputs are represented by IGSrcs) can be packed in the same Instruction Group while meeting read port limitations given a Swz swizzle sequence.
bool FindSwizzleForVectorSlot (const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
Enumerate all possible Swizzle sequence to find one that can meet all read port requirements.
bool fitsReadPortLimitations (const std::vector< MachineInstr * > &MIs, const DenseMap< unsigned, unsigned > &PV, std::vector< BankSwizzle > &BS, bool isLastAluTrans) const
Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first (in lexical order) BankSwizzle affectation starting from the one already provided in the Instruction Group MIs that fits Read Port limitations in BS if available.
bool fitsConstReadLimitations (const std::vector< MachineInstr * > &) const
An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+.
bool fitsConstReadLimitations (const std::vector< unsigned > &) const
Same but using const index set instead of MI set.
bool isVector (const MachineInstr &MI) const
Vector instructions are instructions that must fill all instruction slots within an instruction group.
bool isMov (unsigned Opcode) const
DFAPacketizer * CreateTargetScheduleState (const TargetSubtargetInfo &) const override
bool reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
bool analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
unsigned insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
unsigned removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool isPredicated (const MachineInstr &MI) const override
bool isPredicable (const MachineInstr &MI) const override
bool isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
bool isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
bool isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) const override
bool ClobbersPredicate (MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
bool isProfitableToUnpredicate (MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
bool PredicateInstruction (MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
unsigned int getPredicationCost (const MachineInstr &) const override
unsigned int getInstrLatency (const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
bool expandPostRAPseudo (MachineInstr &MI) const override
void reserveIndirectRegisters (BitVector &Reserved, const MachineFunction &MF, const R600RegisterInfo &TRI) const
Reserve the registers that may be accessed using indirect addressing.
unsigned calculateIndirectAddress (unsigned RegIndex, unsigned Channel) const
Calculate the "Indirect Address" for the given RegIndex and Channel.
const TargetRegisterClass * getIndirectAddrRegClass () const
int getIndirectIndexBegin (const MachineFunction &MF) const
int getIndirectIndexEnd (const MachineFunction &MF) const
MachineInstrBuilder buildIndirectWrite (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const
Build instruction(s) for an indirect register write.
MachineInstrBuilder buildIndirectRead (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const
Build instruction(s) for an indirect register read.
unsigned getMaxAlusPerClause () const
MachineInstrBuilder buildDefaultInstruction (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opcode, unsigned DstReg, unsigned Src0Reg, unsigned Src1Reg=0) const
buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers initialized to their default values.
MachineInstr * buildSlotOfVectorInstruction (MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg) const
MachineInstr * buildMovImm (MachineBasicBlock &BB, MachineBasicBlock::iterator I, unsigned DstReg, uint64_t Imm) const
MachineInstr * buildMovInstr (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const
int getOperandIdx (const MachineInstr &MI, R600::OpName Op) const
Get the index of Op in the MachineInstr.
int getOperandIdx (unsigned Opcode, R600::OpName Op) const
Get the index of Op for the given Opcode.
void setImmOperand (MachineInstr &MI, R600::OpName Op, int64_t Imm) const
Helper function for setting instruction flag values.
void addFlag (MachineInstr &MI, unsigned SrcIdx, unsigned Flag) const
Add one of the MO_FLAG* flags to the operand at SrcIdx.
bool isFlagSet (const MachineInstr &MI, unsigned SrcIdx, unsigned Flag) const
Determine if the specified Flag is set on operand at SrcIdx.
MachineOperand & getFlagOp (MachineInstr &MI, unsigned SrcIdx=0, unsigned Flag=0) const
void clearFlag (MachineInstr &MI, unsigned SrcIdx, unsigned Flag) const
Clear the specified flag on the instruction.
bool isRegisterStore (const MachineInstr &MI) const
bool isRegisterLoad (const MachineInstr &MI) const

Definition at line 39 of file R600InstrInfo.h.

◆ BankSwizzle

Enumerator
ALU_VEC_012_SCL_210
ALU_VEC_021_SCL_122
ALU_VEC_120_SCL_212
ALU_VEC_102_SCL_221
ALU_VEC_201
ALU_VEC_210

Definition at line 60 of file R600InstrInfo.h.

◆ addFlag()

Add one of the MO_FLAG* flags to the operand at SrcIdx.

Definition at line 1424 of file R600InstrInfo.cpp.

References clearFlag(), llvm::get(), getFlagOp(), llvm::MachineOperand::getImm(), HAS_NATIVE_OPERANDS, MI, MO_FLAG_LAST, MO_FLAG_MASK, MO_FLAG_NOT_LAST, NUM_MO_FLAGS, and llvm::MachineOperand::setImm().

Referenced by insertBranch().

◆ analyzeBranch()

Definition at line 637 of file R600InstrInfo.cpp.

References Cond, llvm::MachineOperand::CreateReg(), llvm::MachineOperand::getMBB(), getOpcode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, isBranch(), isJump(), isPredicateSetter(), MBB, and TBB.

◆ buildDefaultInstruction()

◆ buildIndirectRead()

Build instruction(s) for an indirect register read.

Returns

The instruction that performs the indirect register read

Definition at line 1108 of file R600InstrInfo.cpp.

References llvm::Address, I, and MBB.

◆ buildIndirectWrite()

Build instruction(s) for an indirect register write.

Returns

The instruction that performs the indirect register write

Definition at line 1076 of file R600InstrInfo.cpp.

References llvm::Address, I, and MBB.

◆ buildMovImm()

◆ buildMovInstr()

◆ buildSlotOfVectorInstruction()

Definition at line 1274 of file R600InstrInfo.cpp.

References assert(), buildDefaultInstruction(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), getOperandIdx(), llvm::MachineOperand::getReg(), getSlotedOps(), I, llvm::MachineOperand::isImm(), MBB, MI, llvm::AMDGPUSubtarget::R700, llvm::MachineOperand::setImm(), setImmOperand(), and llvm::MachineOperand::setReg().

◆ calculateIndirectAddress()

Calculate the "Indirect Address" for the given RegIndex and Channel.

We model indirect addressing using a virtual address space that can be accessed with loads and stores. The "Indirect Address" is the memory address in this virtual address space that maps to the given RegIndex and Channel.

Definition at line 979 of file R600InstrInfo.cpp.

References assert().

Referenced by expandPostRAPseudo().

◆ canBeConsideredALU()

◆ clearFlag()

◆ ClobbersPredicate()

◆ copyPhysReg()

Definition at line 38 of file R600InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), buildDefaultInstruction(), contains(), llvm::RegState::Define, DL, llvm::MachineInstr::getOperand(), getOperandIdx(), llvm::R600RegisterInfo::getSubRegFromChannel(), I, llvm::RegState::Implicit, MBB, MI, and llvm::MachineOperand::setIsKill().

◆ CreateTargetScheduleState()

◆ definesAddressRegister()

◆ expandPostRAPseudo()

◆ FindSwizzleForVectorSlot()

bool R600InstrInfo::FindSwizzleForVectorSlot ( const std::vector< std::vector< std::pair< int, unsigned > > > & IGSrcs,
std::vector< R600InstrInfo::BankSwizzle > & SwzCandidate,
const std::vector< std::pair< int, unsigned > > & TransSrcs,
R600InstrInfo::BankSwizzle TransSwz ) const

◆ fitsConstReadLimitations() [1/2]

An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+.

This function check if MI set in input meet this limitations

Definition at line 572 of file R600InstrInfo.cpp.

References contains(), fitsConstReadLimitations(), getSrcs(), llvm::SmallSet< T, N, C >::insert(), isALUInstr(), MI, and llvm::SmallSet< T, N, C >::size().

Referenced by fitsConstReadLimitations().

◆ fitsConstReadLimitations() [2/2]

bool R600InstrInfo::fitsConstReadLimitations ( const std::vector< unsigned > & Consts ) const

◆ fitsReadPortLimitations()

◆ getFlagOp()

Parameters

SrcIdx The register source to set the flag on (e.g src0, src1, src2)
Flag The flag being set.

Returns

the operand containing the flags for this instruction.

Definition at line 1359 of file R600InstrInfo.cpp.

References assert(), llvm::get(), GET_FLAG_OPERAND_IDX, getOperandIdx(), HAS_NATIVE_OPERANDS, llvm::MachineOperand::isImm(), MI, MO_FLAG_ABS, MO_FLAG_CLAMP, MO_FLAG_LAST, MO_FLAG_MASK, MO_FLAG_NEG, MO_FLAG_NOT_LAST, and R600_InstFlag::OP3.

Referenced by addFlag(), and clearFlag().

◆ getIndirectAddrRegClass()

◆ getIndirectIndexBegin()

◆ getIndirectIndexEnd()

◆ getInstrLatency()

◆ getMaxAlusPerClause()

unsigned R600InstrInfo::getMaxAlusPerClause ( ) const

◆ getOperandIdx() [1/2]

Get the index of Op in the MachineInstr.

Returns

-1 if the Instruction does not contain the specified [Op](namespacellvm.html#ab471937b9a227e70c7fe8bd9604014d6).

Definition at line 1338 of file R600InstrInfo.cpp.

References getOperandIdx(), and MI.

Referenced by buildSlotOfVectorInstruction(), copyPhysReg(), fitsReadPortLimitations(), getFlagOp(), getOperandIdx(), getSelIdx(), getSrcs(), isLDSRetInstr(), PredicateInstruction(), and setImmOperand().

◆ getOperandIdx() [2/2]

int R600InstrInfo::getOperandIdx ( unsigned Opcode,
R600::OpName Op ) const

◆ getPredicationCost()

◆ getRegisterInfo()

◆ getSelIdx()

Returns

The operand Index for the Sel operand given an index to one of the instruction's src operands.

Definition at line 224 of file R600InstrInfo.cpp.

References getOperandIdx().

◆ getSrcs()

◆ hasInstrModifiers()

bool R600InstrInfo::hasInstrModifiers ( unsigned Opcode ) const

◆ insertBranch()

Definition at line 720 of file R600InstrInfo.cpp.

References addFlag(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), Cond, DL, findFirstPredicateSetterFrom(), FindLastAluClause(), llvm::get(), llvm::getImm(), llvm::MachineInstr::getOperand(), llvm::RegState::Kill, MBB, MO_FLAG_PUSH, llvm::MachineOperand::setImm(), and TBB.

◆ isALUInstr()

◆ isCubeOp()

◆ isExport()

◆ isFlagSet()

Determine if the specified Flag is set on operand at SrcIdx.

References MI.

◆ isLDSInstr()

◆ isLDSRetInstr()

◆ isLegalToSplitMBBAt()

◆ isLegalUpTo()

◆ isMov()

◆ isPredicable()

◆ isPredicated()

◆ isProfitableToDupForIfCvt()

◆ isProfitableToIfCvt() [1/2]

◆ isProfitableToIfCvt() [2/2]

◆ isProfitableToUnpredicate()

◆ isReductionOp()

◆ isRegisterLoad()

◆ isRegisterStore()

◆ isTransOnly() [1/2]

◆ isTransOnly() [2/2]

◆ isVector()

◆ isVectorOnly() [1/2]

◆ isVectorOnly() [2/2]

◆ mustBeLastInClause()

bool R600InstrInfo::mustBeLastInClause ( unsigned Opcode ) const

◆ PredicateInstruction()

◆ readsLDSSrcReg()

◆ removeBranch()

◆ reserveIndirectRegisters()

◆ reverseBranchCondition()

◆ setImmOperand()

void R600InstrInfo::setImmOperand ( MachineInstr & MI,
R600::OpName Op,
int64_t Imm ) const

◆ usesAddressRegister()

◆ usesTextureCache() [1/2]

◆ usesTextureCache() [2/2]

bool R600InstrInfo::usesTextureCache ( unsigned Opcode ) const

◆ usesVertexCache() [1/2]

◆ usesVertexCache() [2/2]

bool R600InstrInfo::usesVertexCache ( unsigned Opcode ) const

The documentation for this class was generated from the following files: