R600MCCodeEmitter.cpp Source File (original) (raw)

26using namespace llvm;

28namespace {

31 const MCRegisterInfo &MRI;

32 const MCInstrInfo &MCII;

34public:

35 R600MCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri)

36 : MRI(mri), MCII(mcii) {}

37 R600MCCodeEmitter(const R600MCCodeEmitter &) = delete;

38 R600MCCodeEmitter &operator=(const R600MCCodeEmitter &) = delete;

41 void encodeInstruction(const MCInst &MI, SmallVectorImpl &CB,

42 SmallVectorImpl &Fixups,

43 const MCSubtargetInfo &STI) const override;

46 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,

47 SmallVectorImpl &Fixups,

48 const MCSubtargetInfo &STI) const;

50private:

51 void emit(uint32_t value, SmallVectorImpl &CB) const;

52 void emit(uint64_t value, SmallVectorImpl &CB) const;

56 uint64_t getBinaryCodeForInstr(const MCInst &MI,

57 SmallVectorImpl &Fixups,

58 const MCSubtargetInfo &STI) const;

59};

61}

82 return new R600MCCodeEmitter(MCII, *Ctx.getRegisterInfo());

83}

85void R600MCCodeEmitter::encodeInstruction(const MCInst &MI,

90 if (MI.getOpcode() == R600::RETURN ||

91 MI.getOpcode() == R600::FETCH_CLAUSE ||

92 MI.getOpcode() == R600::ALU_CLAUSE ||

93 MI.getOpcode() == R600::BUNDLE ||

94 MI.getOpcode() == R600::KILL) {

95 return;

96 }

98 uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups, STI);

99 uint32_t InstWord2 = MI.getOperand(2).getImm();

100 if (!(STI.hasFeature(R600::FeatureCaymanISA))) {

101 InstWord2 |= 1 << 19;

102 }

103

104 emit(InstWord01, CB);

105 emit(InstWord2, CB);

106 emit((uint32_t)0, CB);

108 int64_t Sampler = MI.getOperand(14).getImm();

109

110 int64_t SrcSelect[4] = {

111 MI.getOperand(2).getImm(), MI.getOperand(3).getImm(),

112 MI.getOperand(4).getImm(), MI.getOperand(5).getImm()};

113 int64_t Offsets[3] = {MI.getOperand(6).getImm() & 0x1F,

114 MI.getOperand(7).getImm() & 0x1F,

115 MI.getOperand(8).getImm() & 0x1F};

116

117 uint64_t Word01 = getBinaryCodeForInstr(MI, Fixups, STI);

118 uint32_t Word2 = Sampler << 15 | SrcSelect[ELEMENT_X] << 20 |

122

123 emit(Word01, CB);

124 emit(Word2, CB);

125 emit((uint32_t)0, CB);

126 } else {

127 uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI);

128 if ((STI.hasFeature(R600::FeatureR600ALUInst)) &&

131 uint64_t ISAOpCode = Inst & (0x3FFULL << 39);

132 Inst &= ~(0x3FFULL << 39);

133 Inst |= ISAOpCode << 1;

134 }

135 emit(Inst, CB);

136 }

137}

138

139void R600MCCodeEmitter::emit(uint32_t Value, SmallVectorImpl &CB) const {

141}

142

143void R600MCCodeEmitter::emit(uint64_t Value, SmallVectorImpl &CB) const {

145}

146

147unsigned R600MCCodeEmitter::getHWReg(MCRegister Reg) const {

149}

150

151uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,

152 const MCOperand &MO,

153 SmallVectorImpl &Fixups,

154 const MCSubtargetInfo &STI) const {

155 if (MO.isReg()) {

157 return MRI.getEncodingValue(MO.getReg());

159 }

160

162

163

164

165

166

167

168 const unsigned offset = (&MO == &MI.getOperand(0)) ? 0 : 4;

170 return 0;

171 }

172

175}

176

177#include "R600GenMCCodeEmitter.inc"

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static unsigned getHWReg(const SIInstrInfo *TII, const MachineInstr &RegInstr)

#define HAS_NATIVE_OPERANDS(Flags)

#define HW_REG_MASK

Defines for extracting register information from register encoding.

RegElement

Definition R600MCCodeEmitter.cpp:63

@ ELEMENT_W

Definition R600MCCodeEmitter.cpp:67

@ ELEMENT_Y

Definition R600MCCodeEmitter.cpp:65

@ ELEMENT_Z

Definition R600MCCodeEmitter.cpp:66

@ ELEMENT_X

Definition R600MCCodeEmitter.cpp:64

FCInstr

Definition R600MCCodeEmitter.cpp:70

@ FC_ENDLOOP

Definition R600MCCodeEmitter.cpp:75

@ FC_IF_PREDICATE

Definition R600MCCodeEmitter.cpp:71

@ FC_BGNLOOP

Definition R600MCCodeEmitter.cpp:74

@ FC_CONTINUE

Definition R600MCCodeEmitter.cpp:77

@ FC_ELSE

Definition R600MCCodeEmitter.cpp:72

@ FC_BREAK_PREDICATE

Definition R600MCCodeEmitter.cpp:76

@ FC_ENDIF

Definition R600MCCodeEmitter.cpp:73

Provides R600 specific target descriptions.

MCCodeEmitter - Generic instruction encoding interface.

Context object for machine code objects.

static MCFixup create(uint32_t Offset, const MCExpr *Value, MCFixupKind Kind, bool PCRel=false)

Consider bit fields if we need more flags.

Instances of this class represent a single low-level machine instruction.

Describe properties that are true of each instruction in the target description file.

Interface to description of machine instruction set.

const MCInstrDesc & get(unsigned Opcode) const

Return the machine instruction descriptor that corresponds to the specified instruction opcode.

MCRegister getReg() const

Returns the register number.

const MCExpr * getExpr() const

Generic base class for all target subtargets.

bool hasFeature(unsigned Feature) const

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

Offsets

Offsets in bytes from the start of the input buffer.

void write(void *memory, value_type value, endianness endian)

Write a value to memory with a particular endianness.

This is an optimization pass for GlobalISel generic memory operations.

FunctionAddr VTableAddr Value

MCCodeEmitter * createR600MCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)

Definition R600MCCodeEmitter.cpp:80

@ FK_SecRel_4

A four-byte section relative fixup.