RISCVCallLowering.cpp Source File (original) (raw)

25using namespace llvm;

27namespace {

30private:

37 bool IsRet;

39public:

40 RISCVOutgoingValueAssigner(RISCVCCAssignFn *RISCVAssignFn_, bool IsRet)

41 : CallLowering::OutgoingValueAssigner(nullptr),

42 RISCVAssignFn(RISCVAssignFn_), IsRet(IsRet) {}

44 bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,

46 const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags,

47 CCState &State) override {

48 if (RISCVAssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State, IsRet,

50 return true;

53 return false;

54 }

55};

58 RISCVOutgoingValueHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI,

59 MachineInstrBuilder MIB)

60 : OutgoingValueHandler(B, MRI), MIB(MIB),

61 Subtarget(MIRBuilder.getMF().getSubtarget()) {}

62 Register getStackAddress(uint64_t MemSize, int64_t Offset,

63 MachinePointerInfo &MPO,

64 ISD::ArgFlagsTy Flags) override {

65 MachineFunction &MF = MIRBuilder.getMF();

66 LLT p0 = LLT::pointer(0, Subtarget.getXLen());

67 LLT sXLen = LLT::scalar(Subtarget.getXLen());

69 if (!SPReg)

70 SPReg = MIRBuilder.buildCopy(p0, Register(RISCV::X2)).getReg(0);

72 auto OffsetReg = MIRBuilder.buildConstant(sXLen, Offset);

74 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);

77 return AddrReg.getReg(0);

78 }

80 void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,

81 const MachinePointerInfo &MPO,

82 const CCValAssign &VA) override {

83 MachineFunction &MF = MIRBuilder.getMF();

87 auto MMO =

91 Register ExtReg = extendRegister(ValVReg, VA);

92 MIRBuilder.buildStore(ExtReg, Addr, *MMO);

93 }

96 const CCValAssign &VA) override {

97 Register ExtReg = extendRegister(ValVReg, VA);

98 MIRBuilder.buildCopy(PhysReg, ExtReg);

100 }

101

102 unsigned assignCustomValue(CallLowering::ArgInfo &Arg,

104 std::function<void()> *Thunk) override {

105 const CCValAssign &VA = VAs[0];

106 if ((VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) ||

109

110 auto assignFunc = [=]() {

111 auto Trunc = MIRBuilder.buildAnyExt(LLT(VA.getLocVT()), Arg.Regs[0]);

112 MIRBuilder.buildCopy(PhysReg, Trunc);

114 };

115

116 if (Thunk) {

117 *Thunk = assignFunc;

118 return 1;

119 }

120

121 assignFunc();

122 return 1;

123 }

124

125 assert(VAs.size() >= 2 && "Expected at least 2 VAs.");

126 const CCValAssign &VAHi = VAs[1];

127

128 assert(VAHi.needsCustom() && "Value doesn't need custom handling");

130 "Values belong to different arguments");

131

134 "unexpected custom value");

135

138 MIRBuilder.buildUnmerge(NewRegs, Arg.Regs[0]);

139

142

143 MachinePointerInfo MPO;

144 Register StackAddr = getStackAddress(

146

147 assignValueToAddress(NewRegs[1], StackAddr, MemTy, MPO,

148 const_cast<CCValAssign &>(VAHi));

149 }

150

151 auto assignFunc = [=]() {

152 assignValueToReg(NewRegs[0], VA.getLocReg(), VA);

154 assignValueToReg(NewRegs[1], VAHi.getLocReg(), VAHi);

155 };

156

157 if (Thunk) {

158 *Thunk = assignFunc;

159 return 2;

160 }

161

162 assignFunc();

163 return 2;

164 }

165

166private:

167 MachineInstrBuilder MIB;

168

169

171

172 const RISCVSubtarget &Subtarget;

173};

174

176private:

177

178

179

181

182

183 bool IsRet;

184

185public:

186 RISCVIncomingValueAssigner(RISCVCCAssignFn *RISCVAssignFn_, bool IsRet)

187 : CallLowering::IncomingValueAssigner(nullptr),

188 RISCVAssignFn(RISCVAssignFn_), IsRet(IsRet) {}

189

190 bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,

192 const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags,

193 CCState &State) override {

195

197 MF.getInfo()->setIsVectorCall();

198

199 if (RISCVAssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State, IsRet,

201 return true;

202

204 return false;

205 }

206};

207

209 RISCVIncomingValueHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI)

210 : IncomingValueHandler(B, MRI),

211 Subtarget(MIRBuilder.getMF().getSubtarget()) {}

212

213 Register getStackAddress(uint64_t MemSize, int64_t Offset,

214 MachinePointerInfo &MPO,

215 ISD::ArgFlagsTy Flags) override {

216 MachineFrameInfo &MFI = MIRBuilder.getMF().getFrameInfo();

217

220 return MIRBuilder.buildFrameIndex(LLT::pointer(0, Subtarget.getXLen()), FI)

221 .getReg(0);

222 }

223

224 void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,

225 const MachinePointerInfo &MPO,

226 const CCValAssign &VA) override {

227 MachineFunction &MF = MIRBuilder.getMF();

230 MIRBuilder.buildLoad(ValVReg, Addr, *MMO);

231 }

232

234 const CCValAssign &VA) override {

235 markPhysRegUsed(PhysReg);

236 IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);

237 }

238

239 unsigned assignCustomValue(CallLowering::ArgInfo &Arg,

241 std::function<void()> *Thunk) override {

242 const CCValAssign &VA = VAs[0];

243 if ((VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) ||

246

247 markPhysRegUsed(PhysReg);

248

250 auto Copy = MIRBuilder.buildCopy(LocTy, PhysReg);

251

252 MIRBuilder.buildTrunc(Arg.Regs[0], Copy.getReg(0));

253 return 1;

254 }

255

256 assert(VAs.size() >= 2 && "Expected at least 2 VAs.");

257 const CCValAssign &VAHi = VAs[1];

258

259 assert(VAHi.needsCustom() && "Value doesn't need custom handling");

261 "Values belong to different arguments");

262

265 "unexpected custom value");

266

269

272

273 MachinePointerInfo MPO;

274 Register StackAddr = getStackAddress(

276

277 assignValueToAddress(NewRegs[1], StackAddr, MemTy, MPO,

278 const_cast<CCValAssign &>(VAHi));

279 }

280

281 assignValueToReg(NewRegs[0], VA.getLocReg(), VA);

283 assignValueToReg(NewRegs[1], VAHi.getLocReg(), VAHi);

284

285 MIRBuilder.buildMergeLikeInstr(Arg.Regs[0], NewRegs);

286

287 return 2;

288 }

289

290

291

292

293 virtual void markPhysRegUsed(MCRegister PhysReg) = 0;

294

295private:

296 const RISCVSubtarget &Subtarget;

297};

298

299struct RISCVFormalArgHandler : public RISCVIncomingValueHandler {

300 RISCVFormalArgHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI)

301 : RISCVIncomingValueHandler(B, MRI) {}

302

303 void markPhysRegUsed(MCRegister PhysReg) override {

304 MIRBuilder.getMRI()->addLiveIn(PhysReg);

305 MIRBuilder.getMBB().addLiveIn(PhysReg);

306 }

307};

308

309struct RISCVCallReturnHandler : public RISCVIncomingValueHandler {

310 RISCVCallReturnHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI,

311 MachineInstrBuilder &MIB)

312 : RISCVIncomingValueHandler(B, MRI), MIB(MIB) {}

313

314 void markPhysRegUsed(MCRegister PhysReg) override {

316 }

317

318 MachineInstrBuilder MIB;

319};

320

321}

322

325

326

333 return true;

344 return false;

345}

346

347

348

350 bool IsLowerArgs = false) {

351 if (T->isIntegerTy())

352 return true;

353 if (T->isHalfTy() || T->isFloatTy() || T->isDoubleTy() || T->isFP128Ty())

354 return true;

355 if (T->isPointerTy())

356 return true;

357 if (T->isArrayTy())

359 IsLowerArgs);

360

361 if (IsLowerArgs && T->isVectorTy() && Subtarget.hasVInstructions() &&

362 T->isScalableTy() &&

364 return true;

365 return false;

366}

367

368

369

370

372 bool IsLowerRetVal = false) {

373 if (T->isIntegerTy() || T->isFloatingPointTy() || T->isPointerTy())

374 return true;

375

376 if (T->isArrayTy())

378

379 if (T->isStructTy()) {

381 for (unsigned i = 0, e = StructT->getNumElements(); i != e; ++i)

383 return false;

384 return true;

385 }

386

387 if (IsLowerRetVal && T->isVectorTy() && Subtarget.hasVInstructions() &&

388 T->isScalableTy() &&

390 return true;

391

392 return false;

393}

394

398 assert(!Val == VRegs.empty() && "Return value without a vreg");

400

403 } else if (!VRegs.empty()) {

407 true))

408 return false;

409

414

416 setArgFlags(OrigRetInfo, AttributeList::ReturnIndex, DL, F);

417

420

421 RISCVOutgoingValueAssigner Assigner(

423 true);

424 RISCVOutgoingValueHandler Handler(MIRBuilder, MF.getRegInfo(), Ret);

426 MIRBuilder, CC, F.isVarArg()))

427 return false;

428 }

429

431 return true;

432}

433

437 bool IsVarArg) const {

439 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs,

441

442 for (unsigned I = 0, E = Outs.size(); I < E; ++I) {

445 true, nullptr))

446 return false;

447 }

448 return true;

449}

450

451

452

453void RISCVCallLowering::saveVarArgRegisters(

455 IncomingValueAssigner &Assigner, CCState &CCInfo) const {

458 unsigned XLenInBytes = Subtarget.getXLen() / 8;

464

465

466

467 int VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx);

468 int FI;

469

470

471

472 if (VarArgsSaveSize == 0) {

473 int VaArgOffset = Assigner.StackSize;

475 } else {

476 int VaArgOffset = -VarArgsSaveSize;

478

479

480

481

482 if (Idx % 2) {

484 VaArgOffset - static_cast<int>(XLenInBytes), true);

485 VarArgsSaveSize += XLenInBytes;

486 }

487

491

494 MRI.createGenericVirtualRegister(sXLen), XLenInBytes);

495

496

497

498 const MVT XLenVT = Subtarget.getXLenVT();

499 for (unsigned I = Idx; I < ArgRegs.size(); ++I) {

500 const Register VReg = MRI.createGenericVirtualRegister(sXLen);

502 VReg, ArgRegs[I],

505 auto MPO =

508 FIN = MIRBuilder.buildPtrAdd(MRI.createGenericVirtualRegister(p0),

509 FIN.getReg(0), Offset);

510 }

511 }

512

513

514

517}

518

524

526 for (auto &Arg : F.args()) {

528 true))

529 return false;

530 }

531

535

537

538

539

542

543 unsigned Index = 0;

544 for (auto &Arg : F.args()) {

545

546 ArgInfo AInfo(VRegs[Index], Arg.getType(), Index);

547 setArgFlags(AInfo, Index + AttributeList::FirstArgIndex, DL, F);

548

549

550

551

553

554 ++Index;

555 }

556

559 false);

560 RISCVFormalArgHandler Handler(MIRBuilder, MF.getRegInfo());

561

563 CCState CCInfo(CC, F.isVarArg(), MIRBuilder.getMF(), ArgLocs, F.getContext());

565 handleAssignments (Handler, SplitArgInfos, CCInfo, ArgLocs, MIRBuilder))

566 return false;

567

568 if (F.isVarArg())

569 saveVarArgRegisters(MIRBuilder, Handler, Assigner, CCInfo);

570

571 return true;

572}

573

579

582 for (auto &AInfo : Info.OrigArgs) {

584 return false;

585 if (AInfo.Flags[0].isByVal())

586 return false;

587 }

588

589 if (!Info.OrigRet.Ty->isVoidTy() &&

591 return false;

592

594 MIRBuilder.buildInstr(RISCV::ADJCALLSTACKDOWN);

595

597 for (auto &AInfo : Info.OrigArgs) {

598

599

600

602 }

603

604

605 Info.IsTailCall = false;

606

607

608 if (!Info.Callee.isReg())

610

612 MIRBuilder

614 : RISCV::PseudoCALL)

615 .add(Info.Callee);

617 Call.addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv));

618

619 RISCVOutgoingValueAssigner ArgAssigner(

621 false);

622 RISCVOutgoingValueHandler ArgHandler(MIRBuilder, MF.getRegInfo(), Call);

624 MIRBuilder, CC, Info.IsVarArg))

625 return false;

626

628

629 CallSeqStart.addImm(ArgAssigner.StackSize).addImm(0);

630 MIRBuilder.buildInstr(RISCV::ADJCALLSTACKUP)

631 .addImm(ArgAssigner.StackSize)

633

634

635

636

637 if (Call->getOperand(0).isReg())

641 Call->getDesc(), Call->getOperand(0), 0);

642

643 if (Info.CanLowerReturn && !Info.OrigRet.Ty->isVoidTy()) {

646

647 RISCVIncomingValueAssigner RetAssigner(

649 true);

650 RISCVCallReturnHandler RetHandler(MIRBuilder, MF.getRegInfo(), Call);

652 MIRBuilder, CC, Info.IsVarArg))

653 return false;

654 }

655

656 if (!Info.CanLowerReturn)

657 insertSRetLoads(MIRBuilder, Info.OrigRet.Ty, Info.OrigRet.Regs,

658 Info.DemoteRegister, Info.DemoteStackIndex);

659

660 return true;

661}

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

Analysis containing CSE Info

This file declares the MachineIRBuilder class.

Promote Memory to Register

static bool isSupportedReturnType(Type *T)

static bool isSupportedArgumentType(Type *T)

static bool isLegalElementTypeForRVV(Type *EltTy, const RISCVSubtarget &Subtarget)

Return true if scalable vector with ScalarTy is legal for lowering.

Definition RISCVCallLowering.cpp:327

This file describes how to lower LLVM calls to machine code calls.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

size_t size() const

size - Get the array size.

bool empty() const

empty - Check if the array is empty.

CCState - This class holds information needed while lowering arguments and return values.

MachineFunction & getMachineFunction() const

unsigned getFirstUnallocated(ArrayRef< MCPhysReg > Regs) const

getFirstUnallocated - Return the index of the first unallocated register in the set,...

uint64_t getStackSize() const

Returns the size of the currently allocated portion of the stack.

static CCValAssign getReg(unsigned ValNo, MVT ValVT, MCRegister Reg, MVT LocVT, LocInfo HTP, bool IsCustom=false)

int64_t getLocMemOffset() const

unsigned getValNo() const

void insertSRetLoads(MachineIRBuilder &MIRBuilder, Type *RetTy, ArrayRef< Register > VRegs, Register DemoteReg, int FI) const

Load the returned value from the stack into virtual registers in VRegs.

bool handleAssignments(ValueHandler &Handler, SmallVectorImpl< ArgInfo > &Args, CCState &CCState, SmallVectorImpl< CCValAssign > &ArgLocs, MachineIRBuilder &MIRBuilder, ArrayRef< Register > ThisReturnRegs={}) const

Use Handler to insert code to handle the argument/return values represented by Args.

void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, SmallVectorImpl< uint64_t > *Offsets=nullptr) const

Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.

void insertSRetIncomingArgument(const Function &F, SmallVectorImpl< ArgInfo > &SplitArgs, Register &DemoteReg, MachineRegisterInfo &MRI, const DataLayout &DL) const

Insert the hidden sret ArgInfo to the beginning of SplitArgs.

bool determineAndHandleAssignments(ValueHandler &Handler, ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, bool IsVarArg, ArrayRef< Register > ThisReturnRegs={}) const

Invoke ValueAssigner::assignArg on each of the given Args and then use Handler to move them to the as...

void insertSRetStores(MachineIRBuilder &MIRBuilder, Type *RetTy, ArrayRef< Register > VRegs, Register DemoteReg) const

Store the return value given by VRegs into stack starting at the offset specified in DemoteReg.

bool determineAssignments(ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, CCState &CCInfo) const

Analyze the argument list in Args, using Assigner to populate CCInfo.

CallLowering(const TargetLowering *TLI)

void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const

A parsed version of the target data layout string in and methods for querying it.

unsigned getAllocaAddrSpace() const

FunctionLoweringInfo - This contains information that is global to a function that is used when lower...

DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg allocated to hold a pointer to ...

bool CanLowerReturn

CanLowerReturn - true iff the function's return value can be lowered to registers.

LLVMContext & getContext() const

getContext - Return a reference to the LLVMContext associated with this function.

static constexpr LLT scalar(unsigned SizeInBits)

Get a low-level scalar or aggregate "bag of bits".

static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)

Get a low-level pointer in the given address space.

constexpr TypeSize getSizeInBytes() const

Returns the total size of the type in bytes, i.e.

bool isInteger() const

Return true if this is an integer or a vector integer type.

bool isScalableVector() const

Return true if this is a vector value type where the runtime length is machine dependent.

static LLVM_ABI MVT getVT(Type *Ty, bool HandleUnknown=false)

Return the value type corresponding to the specified type.

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

LLVM_ABI int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)

Create a new object at a fixed location on the stack.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)

getMachineMemOperand - Allocate a new MachineMemOperand.

MachineFrameInfo & getFrameInfo()

getFrameInfo - Return the frame info object for the current function.

MachineRegisterInfo & getRegInfo()

getRegInfo - Return information about the registers currently in use.

const DataLayout & getDataLayout() const

Return the DataLayout attached to the Module associated to this MF.

Function & getFunction()

Return the LLVM function that this machine code represents.

Ty * getInfo()

getInfo - Keep track of various per-function pieces of information for backends that would like to do...

Helper class to build MachineInstr.

MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)

Insert an existing instruction at the insertion point.

MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)

Build and insert Res = G_PTR_ADD Op0, Op1.

MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)

Build and insert G_STORE Val, Addr, MMO.

MachineInstrBuilder buildInstr(unsigned Opcode)

Build and insert = Opcode .

MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)

Build and insert Res = G_FRAME_INDEX Idx.

MachineFunction & getMF()

Getter for the function we currently build.

MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)

Build but don't insert = Opcode .

virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)

Build and insert Res = G_CONSTANT Val.

const MachineInstrBuilder & addImm(int64_t Val) const

Add a new immediate operand.

const MachineInstrBuilder & add(const MachineOperand &MO) const

@ MOLoad

The memory access reads data.

@ MOStore

The memory access writes data.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

bool lowerReturn(MachineIRBuilder &MIRBuiler, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI) const override

This hook behaves as the extended lowerReturn function, but for targets that do not support swifterro...

Definition RISCVCallLowering.cpp:395

bool canLowerReturn(MachineFunction &MF, CallingConv::ID CallConv, SmallVectorImpl< BaseArgInfo > &Outs, bool IsVarArg) const override

This hook must be implemented to check whether the return values described by Outs can fit into the r...

Definition RISCVCallLowering.cpp:434

bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override

This hook must be implemented to lower the given call instruction, including argument and return valu...

Definition RISCVCallLowering.cpp:574

bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register > > VRegs, FunctionLoweringInfo &FLI) const override

This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...

Definition RISCVCallLowering.cpp:519

RISCVCallLowering(const RISCVTargetLowering &TLI)

Definition RISCVCallLowering.cpp:323

RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...

void setVarArgsFrameIndex(int Index)

void setVarArgsSaveSize(int Size)

RISCVABI::ABI getTargetABI() const

bool hasVInstructionsI64() const

bool hasVInstructionsF64() const

bool hasVInstructionsBF16Minimal() const

bool hasVInstructionsF16Minimal() const

const RISCVRegisterBankInfo * getRegBankInfo() const override

bool hasVInstructions() const

const RISCVRegisterInfo * getRegisterInfo() const override

const RISCVInstrInfo * getInstrInfo() const override

bool hasVInstructionsF32() const

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

The instances of the Type class are immutable: once they are created, they are never changed.

bool isPointerTy() const

True if this is an instance of PointerType.

bool isFloatTy() const

Return true if this is 'float', a 32-bit IEEE fp type.

bool isBFloatTy() const

Return true if this is 'bfloat', a 16-bit bfloat type.

bool isHalfTy() const

Return true if this is 'half', a 16-bit IEEE fp type.

bool isDoubleTy() const

Return true if this is 'double', a 64-bit IEEE fp type.

bool isIntegerTy() const

True if this is an instance of IntegerType.

unsigned getNumOperands() const

LLVM Value Representation.

Type * getType() const

All values are typed, get the type of this value.

constexpr char Align[]

Key for Kernel::Arg::Metadata::mAlign.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ Fast

Attempts to make calls as fast as possible (e.g.

ArrayRef< MCPhysReg > getArgGPRs(const RISCVABI::ABI ABI)

@ Implicit

Not emitted register (e.g. carry, or temporary result).

This is an optimization pass for GlobalISel generic memory operations.

bool CC_RISCV_FastCC(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsRet, Type *OrigTy)

LLVM_ABI Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)

Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...

bool RISCVCCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsRet, Type *OrigTy)

RISCVCCAssignFn - This target-specific function extends the default CCValAssign with additional infor...

bool CC_RISCV(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsRet, Type *OrigTy)

ArrayRef(const T &OneElt) -> ArrayRef< T >

decltype(auto) cast(const From &Val)

cast - Return the argument parameter cast to the specified type.

Align commonAlignment(Align A, uint64_t Offset)

Returns the alignment that satisfies both alignments.

LLVM_ABI Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)

SmallVector< Register, 4 > Regs

SmallVector< ISD::ArgFlagsTy, 4 > Flags

Base class for ValueHandlers used for arguments coming into the current function, or for return value...

void assignValueToReg(Register ValVReg, Register PhysReg, const CCValAssign &VA) override

Provides a default implementation for argument handling.

Base class for ValueHandlers used for arguments passed to a function call, or for return values.

static LLVM_ABI MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)

Stack pointer relative access.

static LLVM_ABI MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)

Return a MachinePointerInfo record that refers to the specified FrameIndex.