LLVM: lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp Source File (original) (raw)

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21using namespace llvm;

22#define DEBUG_TYPE "riscv-dead-defs"

23#define RISCV_DEAD_REG_DEF_NAME "RISC-V Dead register definitions"

24

25STATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced");

26

27namespace {

29public:

30 static char ID;

31

33 bool runOnMachineFunction(MachineFunction &MF) override;

34 void getAnalysisUsage(AnalysisUsage &AU) const override {

36 AU.addRequired();

38 AU.addRequired();

40 AU.addPreserved();

43 }

44

46};

47}

48

49char RISCVDeadRegisterDefinitions::ID = 0;

52

54 return new RISCVDeadRegisterDefinitions();

55}

56

57bool RISCVDeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {

59 return false;

60

62 LiveIntervals &LIS = getAnalysis().getLIS();

63 LLVM_DEBUG(dbgs() << "***** RISCVDeadRegisterDefinitions *****\n");

64

65 bool MadeChange = false;

66 for (MachineBasicBlock &MBB : MF) {

67 for (MachineInstr &MI : MBB) {

68

69

70 const MCInstrDesc &Desc = MI.getDesc();

71 if (Desc.mayLoad() && Desc.mayStore() &&

72 Desc.hasUnmodeledSideEffects() &&

73 MI.getOpcode() != RISCV::PseudoVSETVLI &&

74 MI.getOpcode() != RISCV::PseudoVSETIVLI)

75 continue;

76 for (int I = 0, E = Desc.getNumDefs(); I != E; ++I) {

77 MachineOperand &MO = MI.getOperand(I);

79 continue;

80

81 if (MI.isRegTiedToUseOperand(I)) {

82 LLVM_DEBUG(dbgs() << " Ignoring, def is tied operand.\n");

83 continue;

84 }

87 continue;

88 LLVM_DEBUG(dbgs() << " Dead def operand #" << I << " in:\n ";

92 if (RC && RC->contains(RISCV::X0)) {

93 X0Reg = RISCV::X0;

94 } else if (RC && RC->contains(RISCV::X0_W)) {

95 X0Reg = RISCV::X0_W;

96 } else if (RC && RC->contains(RISCV::X0_H)) {

97 X0Reg = RISCV::X0_H;

98 } else if (RC && RC->contains(RISCV::X0_Pair)) {

99 X0Reg = RISCV::X0_Pair;

100 } else {

101 LLVM_DEBUG(dbgs() << " Ignoring, register is not a GPR.\n");

102 continue;

103 }

107 LLVM_DEBUG(dbgs() << " Replacing with zero register. New:\n ";

109 ++NumDeadDefsReplaced;

110 MadeChange = true;

111 }

112 }

113 }

114

115 return MadeChange;

116}

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")

Promote Memory to Register

#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)

#define RISCV_DEAD_REG_DEF_NAME

Definition RISCVDeadRegisterDefinitions.cpp:23

This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...

#define STATISTIC(VARNAME, DESC)

AnalysisUsage & addRequired()

AnalysisUsage & addPreserved()

Add the specified Pass class to the set of analyses preserved by this pass.

LLVM_ABI void setPreservesCFG()

This function should be called by the pass, iff they do not:

FunctionPass class - This class is used to implement most global optimizations.

bool hasInterval(Register Reg) const

void removeInterval(Register Reg)

Interval removal.

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

Function & getFunction()

Return the LLVM function that this machine code represents.

bool isReg() const

isReg - Tests if this is a MO_Register operand.

LLVM_ABI void setReg(Register Reg)

Change the register this operand corresponds to.

bool isEarlyClobber() const

Register getReg() const

getReg - Returns the register number.

virtual void print(raw_ostream &OS, const Module *M) const

print - Print out the internal state of the pass.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum) const

Given a machine instruction descriptor, returns the register class constraint for OpNum,...

bool contains(Register Reg) const

Return true if the specified register is included in this register class.

virtual const TargetInstrInfo * getInstrInfo() const

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

This is an optimization pass for GlobalISel generic memory operations.

FunctionPass * createRISCVDeadRegisterDefinitionsPass()

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.