RISCVISelLowering.h Source File (original) (raw)

14#ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H

15#define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H

22#include

24namespace llvm {

32public:

40 unsigned Intrinsic) const override;

42 unsigned AS,

60 unsigned OldShiftOpcode, unsigned NewShiftOpcode,

66 bool ForCodeSize) const override;

68 unsigned Index) const override;

70 bool isIntDivCheap(EVT VT, AttributeList Attr) const override;

82 EVT VT) const override;

85 unsigned

87 std::optional RegisterVT = std::nullopt) const override;

93 EVT VT) const override;

97 EVT &IntermediateVT,

98 unsigned &NumIntermediates,

99 MVT &RegisterVT) const override;

100

102 unsigned SelectOpcode, SDValue X,

104

105

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111

112

113

114

115 if ((LTy.isFloatingPoint() && HTy.isInteger()) ||

117 return true;

118

119

120

121

122 return false;

123 }

124

125 bool

127 unsigned DefinedValues) const override;

128

130

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143

145

147 const APInt &DemandedElts,

148 TargetLoweringOpt &TLO) const override;

149

152 const APInt &DemandedElts,

154 unsigned Depth) const override;

156 const APInt &DemandedElts,

158 unsigned Depth) const override;

159

161 const APInt &DemandedElts,

163 TargetLoweringOpt &TLO,

164 unsigned Depth) const override;

165

167 const APInt &DemandedElts,

170 unsigned Depth) const override;

171

173

176

179

180 bool

182 const MemSDNode &NodeY) const override;

183

185

188

189 std::pair<unsigned, const TargetRegisterClass *>

191 StringRef Constraint, MVT VT) const override;

192

194 std::vector &Ops,

196

200

203

205 EVT VT) const override;

206

208 bool MathUsed) const override {

209 if (VT == MVT::i8 || VT == MVT::i16)

210 return false;

211

213 }

214

216 unsigned AddrSpace) const override {

217

218

219 return NumElem >= 4;

220 }

221

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244 EVT VT) const override;

245

249

252

254 unsigned KeptBits) const override;

255

258 unsigned ExpansionFactor) const override {

262 ExpansionFactor);

263 }

264

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288

290 bool IsVarArg,

295 bool IsVarArg,

304

306 Type *Ty) const override;

310

313

315 SDValue ConstNode) const override;

316

330

331

332

334 EVT VT, unsigned AddrSpace = 0, Align Alignment = Align(1),

336 unsigned *Fast = nullptr) const override;

337

339 const AttributeList &FuncAttributes) const override;

340

343 unsigned NumParts, MVT PartVT, std::optionalCallingConv::ID CC)

344 const override;

345

348 unsigned NumParts, MVT PartVT, EVT ValueVT,

349 std::optionalCallingConv::ID CC) const override;

350

351

353

355 inline static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize,

356 unsigned MinSize) {

357

358

359

360

361

363 }

364

365

366

367 static std::pair<unsigned, unsigned>

369

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371

378

382 static std::pair<unsigned, unsigned>

384 unsigned InsertExtractIdx,

387

389

391

393

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398 unsigned uid,

400

402

411

413 uint64_t ElemSize) const override {

414

415 return Scale == 1;

416 }

417

418

419

421

422

423

425 Align Alignment, unsigned AddrSpace,

427

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439

443 const APInt &GapMask) const override;

444

447 const APInt &GapMask) const override;

448

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480 SDValue N1) const override;

481

482

483

484

486 unsigned &Index);

487

488private:

494 bool IsRet, CallLoweringInfo *CLI,

496

497 template

499 bool IsExternWeak = false) const;

501 bool UseGOT) const;

504

521 int64_t ExtTrueVal) const;

533 bool IsVP) const;

575

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598 bool isEligibleForTailCallOptimization(

601

602

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604 void validateCCReservedRegs(

605 const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs,

607

609

611

612 bool shouldExpandGetVectorLength(EVT TripCountVT, unsigned VF,

613 bool IsScalable) const override;

614

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619

620

621 bool mergeStoresAfterLegalization(EVT VT) const override;

622

623

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626

627 bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override {

628 return false;

629 }

630

631

632

633

634 bool shouldMergeStoreOfLoadsOverCall(EVT SrcVT, EVT MergedVT) const override {

635 return !MergedVT.isVector() || SrcVT.isVector();

636 }

637

638

639

641

642 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,

643 SmallVectorImpl<SDNode *> &Created) const override;

644

645 bool shouldFoldSelectWithSingleBitTest(EVT VT,

646 const APInt &AndMask) const override;

647

649

652

653 std::pair<const TargetRegisterClass *, uint8_t>

654 findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const override;

655};

656

658

673

674using namespace RISCV;

675

676#define GET_RISCVVIntrinsicsTable_DECL

677#include "RISCVGenSearchableTables.inc"

678#undef GET_RISCVVIntrinsicsTable_DECL

679

680}

681

682}

683

684#endif

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

const TargetInstrInfo & TII

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

MachineBasicBlock MachineBasicBlock::iterator MBBI

Function Alias Analysis Results

Analysis containing CSE Info

const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]

static SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG)

static bool useRVVForFixedLengthVectorVT(MVT VT, const RISCVSubtarget &Subtarget)

const SmallVectorImpl< MachineOperand > & Cond

static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")

static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")

This file describes how to lower LLVM code to machine code.

static SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const VETargetLowering &TLI, const VESubtarget *Subtarget)

static SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const VETargetLowering &TLI, const VESubtarget *Subtarget)

static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)

Class for arbitrary precision integers.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

An instruction that atomically checks whether a specified value is in a memory location,...

an instruction that atomically reads a memory location, combines it with another value,...

CCState - This class holds information needed while lowering arguments and return values.

Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...

This class represents a function call, abstracting a target machine's calling convention.

This is the shared class of boolean and integer constants.

This is an important base class in LLVM.

A parsed version of the target data layout string in and methods for querying it.

bool hasMinSize() const

Optimize this function for minimum size (-Oz).

Common base class shared among various IRBuilders.

A wrapper class for inspecting calls to intrinsic functions.

This is an important class for using LLVM in a threaded context.

This class is used to represent ISD::LOAD nodes.

Context object for machine code objects.

Base class for the full range of assembler expressions which are needed for parsing.

static MVT getScalableVectorVT(MVT VT, unsigned NumElements)

TypeSize getSizeInBits() const

Returns the size of the specified MVT in bits.

MVT getVectorElementType() const

Instructions::iterator instr_iterator

Function & getFunction()

Return the LLVM function that this machine code represents.

Representation of each machine instruction.

Flags

Flags values. These may be or'd together.

This is an abstract virtual class for memory operations.

static std::pair< unsigned, unsigned > computeVLMAXBounds(MVT ContainerVT, const RISCVSubtarget &Subtarget)

static std::pair< unsigned, unsigned > decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT, unsigned InsertExtractIdx, const RISCVRegisterInfo *TRI)

ArrayRef< MCPhysReg > getRoundingControlRegisters() const override

Returns a 0 terminated array of rounding control registers that can be attached into strict FP call.

static MVT getM1VT(MVT VT)

Given a vector (either fixed or scalable), return the scalable vector corresponding to a vector regis...

Definition RISCVISelLowering.h:372

InstructionCost getVRGatherVVCost(MVT VT) const

Return the cost of a vrgather.vv instruction for the type VT.

bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const

static unsigned getSubregIndexByMVT(MVT VT, unsigned Index)

Value * getIRStackGuard(IRBuilderBase &IRB) const override

If the target has a standard location for the stack protector cookie, returns the address of that loc...

bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override

Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) satur...

bool storeOfVectorConstantIsCheap(bool IsZero, EVT MemVT, unsigned NumElem, unsigned AddrSpace) const override

Return true if it is expected to be cheaper to do a store of vector constant with the given size and ...

Definition RISCVISelLowering.h:215

InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const override

SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override

This hook must be implemented to lower outgoing return values, described by the Outs array,...

unsigned getMaxSupportedInterleaveFactor() const override

Get the maximum supported factor for interleaved memory accesses.

Definition RISCVISelLowering.h:436

bool mayBeEmittedAsTailCall(const CallInst *CI) const override

Return true if the target may be able emit the call instruction as a tail call.

RISCVTargetLowering(const TargetMachine &TM, const RISCVSubtarget &STI)

MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override

This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...

Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override

Inserts in the IR a target-specific intrinsic specifying a fence.

ISD::NodeType getExtendForAtomicOps() const override

Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...

Definition RISCVISelLowering.h:246

bool isTruncateFree(Type *SrcTy, Type *DstTy) const override

Return true if it's free to truncate a value of type FromTy to type ToTy.

bool preferZeroCompareBranch() const override

Return true if the heuristic to prefer icmp eq zero should be used in code gen prepare.

Definition RISCVISelLowering.h:231

bool shouldRemoveExtendFromGSIndex(SDValue Extend, EVT DataVT) const override

Value * emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override

Perform a masked atomicrmw using a target-specific intrinsic.

bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override

Returns true if the target allows unaligned memory accesses of the specified type.

const Constant * getTargetConstantFromLoad(LoadSDNode *LD) const override

This method returns the constant pool value that will be loaded by LD.

const RISCVSubtarget & getSubtarget() const

Definition RISCVISelLowering.h:36

bool lowerDeinterleaveIntrinsicToLoad(Instruction *Load, Value *Mask, IntrinsicInst *DI) const override

Lower a deinterleave intrinsic to a target specific load intrinsic.

TargetLowering::ShiftLegalizationStrategy preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const override

Definition RISCVISelLowering.h:257

SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override

This method will be invoked for all target nodes and for any target-independent nodes that the target...

bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override

Return true if folding a constant offset with the given GlobalAddress is legal.

void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override

Determine which of the bits specified in Mask are known to be either zero or one and return them in t...

bool preferScalarizeSplat(SDNode *N) const override

bool shouldExtendTypeInLibCall(EVT Type) const override

Returns true if arguments should be extended in lib calls.

bool isLegalAddImmediate(int64_t Imm) const override

Return true if the specified immediate is legal add immediate, that is the target has add instruction...

bool shouldSignExtendTypeInLibCall(Type *Ty, bool IsSigned) const override

Returns true if arguments should be sign-extended in lib calls.

const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override

InstructionCost getVRGatherVICost(MVT VT) const

Return the cost of a vrgather.vi (or vx) instruction for the type VT.

bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override

Return true if it is beneficial to convert a load of a constant to just the constant itself.

bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, TargetLoweringOpt &TLO) const override

bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override

bool lowerInterleavedStore(Instruction *Store, Value *Mask, ShuffleVectorInst *SVI, unsigned Factor, const APInt &GapMask) const override

Lower an interleaved store into a vssegN intrinsic.

MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override

Return the register type for a given MVT, ensuring vectors are treated as a series of gpr sized integ...

bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override

Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...

bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context, const Type *RetTy) const override

This hook should be implemented to check whether the return values described by the Outs array can fi...

bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override

Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...

bool hasAndNotCompare(SDValue Y) const override

Return true if the target should transform: (X & Y) == Y ---> (~X & Y) == 0 (X & Y) !...

bool shouldScalarizeBinop(SDValue VecOp) const override

Try to convert an extract element of a vector binary operation into an extract element followed by a ...

ISD::NodeType getExtendForAtomicRMWArg(unsigned Op) const override

Returns how the platform's atomic rmw operations expect their input argument to be extended (ZERO_EXT...

bool isDesirableToCommuteWithShift(const SDNode *N, CombineLevel Level) const override

Return true if it is profitable to move this shift by a constant amount through its operand,...

bool areTwoSDNodeTargetMMOFlagsMergeable(const MemSDNode &NodeX, const MemSDNode &NodeY) const override

Return true if it is valid to merge the TargetMMOFlags in two SDNodes.

bool hasBitTest(SDValue X, SDValue Y) const override

Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...

static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize, unsigned MinSize)

Definition RISCVISelLowering.h:355

bool shouldExpandCttzElements(EVT VT) const override

Return true if the @llvm.experimental.cttz.elts intrinsic should be expanded using generic code in Se...

bool isCheapToSpeculateCtlz(Type *Ty) const override

Return true if it is cheap to speculate a call to intrinsic ctlz.

Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const override

Perform a masked cmpxchg using a target-specific intrinsic.

bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override

Returns true if the target can instruction select the specified FP immediate natively.

bool convertSelectOfConstantsToMath(EVT VT) const override

Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops...

Definition RISCVISelLowering.h:225

InstructionCost getLMULCost(MVT VT) const

Return the cost of LMUL for linear operations.

bool supportKCFIBundles() const override

Return true if the target supports kcfi operand bundles.

Definition RISCVISelLowering.h:456

unsigned getJumpTableEncoding() const override

Return the entry encoding for a jump table in the current function.

bool isMulAddWithConstProfitable(SDValue AddNode, SDValue ConstNode) const override

Return true if it may be profitable to transform (mul (add x, c1), c2) -> (add (mul x,...

InstructionCost getVSlideVICost(MVT VT) const

Return the cost of a vslidedown.vi or vslideup.vi instruction for the type VT.

bool fallBackToDAGISel(const Instruction &Inst) const override

EVT getOptimalMemOpType(LLVMContext &Context, const MemOp &Op, const AttributeList &FuncAttributes) const override

Returns the target specific optimal type for load and store operations as a result of memset,...

EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override

Return the ValueType of the result of SETCC operations.

bool isCtpopFast(EVT VT) const override

Return true if ctpop instruction is fast.

unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override

This method can be implemented by targets that want to expose additional information about sign bits ...

MVT getContainerForFixedLengthVector(MVT VT) const

static unsigned getRegClassIDForVecVT(MVT VT)

If a physical register, this returns the register that receives the exception address on entry to an ...

TargetLowering::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override

Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.

bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override

Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...

std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override

Given a physical register constraint (e.g.

MachineBasicBlock * emitDynamicProbedAlloc(MachineInstr &MI, MachineBasicBlock *MBB) const

MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const override

This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...

SDValue computeVLMax(MVT VecVT, const SDLoc &DL, SelectionDAG &DAG) const

bool signExtendConstant(const ConstantInt *CI) const override

Return true if this constant should be sign extended when promoting to a larger type.

bool shouldTransformSignedTruncationCheck(EVT XVT, unsigned KeptBits) const override

Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be trun...

bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, unsigned OldShiftOpcode, unsigned NewShiftOpcode, SelectionDAG &DAG) const override

Given the pattern (X & (C l>>/<< Y)) ==/!= 0 return true if it should be transformed into: ((X <>...

bool hasInlineStackProbe(const MachineFunction &MF) const override

True if stack clash protection is enabled for this functions.

bool hasAndNot(SDValue Y) const override

Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...

Returns the register with the specified architectural or ABI name.

InstructionCost getVSlideVXCost(MVT VT) const

Return the cost of a vslidedown.vx or vslideup.vx instruction for the type VT.

bool isReassocProfitable(SelectionDAG &DAG, SDValue N0, SDValue N1) const override

Control the following reassociation of operands: (op (op x, c1), y) -> (op (op x, y),...

bool shouldFoldMaskToVariableShiftPair(SDValue Y) const override

There are two ways to clear extreme bits (either low or high): Mask: x & (-1 << y) (the instcombine c...

SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override

This callback is invoked for operations that are unsupported by the target, which are registered to u...

bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override

Return true if result of the specified node is used by a return node only.

bool softPromoteHalfType() const override

Definition RISCVISelLowering.h:77

bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override

Return true if an FMA operation is faster than a pair of fmul and fadd instructions.

TargetLowering::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override

Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.

If a physical register, this returns the register that receives the exception typeid on entry to a la...

bool convertSetCCLogicToBitwiseLogic(EVT VT) const override

Use bitwise logic to make pairs of compares more efficient.

Definition RISCVISelLowering.h:222

unsigned getCustomCtpopCost(EVT VT, ISD::CondCode Cond) const override

Return the maximum number of "x & (x - 1)" operations that can be done instead of deferring to a cust...

void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override

This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.

bool isShuffleMaskLegal(ArrayRef< int > M, EVT VT) const override

Return true if the given shuffle mask can be codegen'd directly, or if it should be stack expanded.

bool isCheapToSpeculateCttz(Type *Ty) const override

Return true if it is cheap to speculate a call to intrinsic cttz.

bool isLegalICmpImmediate(int64_t Imm) const override

Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...

ISD::NodeType getExtendForAtomicCmpSwapArg() const override

Returns how the platform's atomic compare and swap expects its comparison value to be extended (ZERO_...

bool lowerInterleavedLoad(Instruction *Load, Value *Mask, ArrayRef< ShuffleVectorInst * > Shuffles, ArrayRef< unsigned > Indices, unsigned Factor, const APInt &GapMask) const override

Lower an interleaved load into a vlsegN intrinsic.

bool lowerInterleaveIntrinsicToStore(Instruction *Store, Value *Mask, ArrayRef< Value * > InterleaveValues) const override

Lower an interleave intrinsic to a target specific store intrinsic.

bool isLegalScaleForGatherScatter(uint64_t Scale, uint64_t ElemSize) const override

Definition RISCVISelLowering.h:412

SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override

This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...

void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override

This callback is invoked when a node result type is illegal for the target, and the operation was reg...

unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override

Certain targets such as MIPS require that some types such as vectors are always broken down into scal...

bool isLegalElementTypeForRVV(EVT ScalarTy) const

bool isLegalFirstFaultLoad(EVT DataType, Align Alignment) const

Return true if a fault-only-first load of the given result type and alignment is legal.

bool isVScaleKnownToBeAPowerOfTwo() const override

Return true only if vscale must be a power of two.

int getLegalZfaFPImm(const APFloat &Imm, EVT VT) const

void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override

Lower the specified operand into the Ops vector.

bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, std::optional< CallingConv::ID > CC) const override

Target-specific splitting of values into parts that fit a register storing a legal type.

Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override

unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override

Return the number of registers for a given MVT, ensuring vectors are treated as a series of gpr sized...

ConstraintType getConstraintType(StringRef Constraint) const override

getConstraintType - Given a constraint letter, return the type of constraint it is for this target.

bool shouldConsiderGEPOffsetSplit() const override

Definition RISCVISelLowering.h:309

MachineInstr * EmitKCFICheck(MachineBasicBlock &MBB, MachineBasicBlock::instr_iterator &MBBI, const TargetInstrInfo *TII) const override

bool isLegalInterleavedAccessType(VectorType *VTy, unsigned Factor, Align Alignment, unsigned AddrSpace, const DataLayout &) const

Returns whether or not generating a interleaved load/store intrinsic for this type will be legal.

bool canCreateUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const override

Return true if Op can create undef or poison from non-undef & non-poison operands.

bool isIntDivCheap(EVT VT, AttributeList Attr) const override

Return true if integer divide is usually cheaper than a sequence of several shifts,...

LegalizeTypeAction getPreferredVectorAction(MVT VT) const override

Customize the preferred legalization strategy for certain types.

SDValue expandIndirectJTBranch(const SDLoc &dl, SDValue Value, SDValue Addr, int JTI, SelectionDAG &DAG) const override

Expands target specific indirect branch for the case of JumpTable expansion.

static unsigned getRegClassIDForLMUL(RISCVVType::VLMUL LMul)

unsigned getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const override

Return the number of registers for a given MVT, for inline assembly.

bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const override

Return true if it is cheaper to split the store of a merged int val from a pair of smaller values int...

Definition RISCVISelLowering.h:109

bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override

Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...

bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const override

Try to convert math with an overflow comparison into the corresponding DAG node operation.

Definition RISCVISelLowering.h:207

bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override

Returns true by value, base pointer and offset pointer and addressing mode by reference if the node's...

SDValue joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, std::optional< CallingConv::ID > CC) const override

Target-specific combining of register parts into its original value.

bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override

Return if the target supports combining a chain like:

bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override

Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.

bool isLegalStridedLoadStore(EVT DataType, Align Alignment) const

Return true if a stride load store of the given result type and alignment is legal.

bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallBase &I, MachineFunction &MF, unsigned Intrinsic) const override

Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...

static bool isSpreadMask(ArrayRef< int > Mask, unsigned Factor, unsigned &Index)

Match a mask which "spreads" the leading elements of a vector evenly across the result.

static RISCVVType::VLMUL getLMUL(MVT VT)

SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override

This hook must be implemented to lower calls into the specified DAG.

bool SimplifyDemandedBitsForTargetNode(SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth) const override

Attempt to simplify any target nodes based on the demanded bits/elts, returning true on success.

bool isZExtFree(SDValue Val, EVT VT2) const override

Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...

bool shouldFoldSelectWithIdentityConstant(unsigned BinOpcode, EVT VT, unsigned SelectOpcode, SDValue X, SDValue Y) const override

Return true if pulling a binary operation into a select with an identity constant is profitable.

unsigned getStackProbeSize(const MachineFunction &MF, Align StackAlign) const

bool shouldInsertFencesForAtomic(const Instruction *I) const override

Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.

Wrapper class representing virtual and physical registers.

Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...

Represents one node in the SelectionDAG.

Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.

This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...

MachineFunction & getMachineFunction() const

This instruction constructs a fixed permutation of two input vectors.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

StringRef - Represent a constant reference to a string, i.e.

TargetInstrInfo - Interface to description of machine instruction set.

virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT, bool MathUsed) const

Try to convert math with an overflow comparison into the corresponding DAG node operation.

ShiftLegalizationStrategy

Return the preferred strategy to legalize tihs SHIFT instruction, with ExpansionFactor being the recu...

virtual unsigned getMinimumJumpTableEntries() const

Return lower limit for number of blocks in a jump table.

virtual ShiftLegalizationStrategy preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, unsigned ExpansionFactor) const

AtomicExpansionKind

Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.

virtual MVT getVPExplicitVectorLengthTy() const

Returns the type to be used for the EVL/AVL operand of VP nodes: ISD::VP_ADD, ISD::VP_SUB,...

TargetLowering(const TargetLowering &)=delete

virtual unsigned combineRepeatedFPDivisors() const

Indicate whether this target prefers to combine FDIVs with the same divisor.

Primary interface to the complete machine description for the target machine.

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...

The instances of the Type class are immutable: once they are created, they are never changed.

LLVM Value Representation.

Base class of all SIMD vector types.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

@ Fast

Attempts to make calls as fast as possible (e.g.

@ C

The default llvm calling convention, compatible with C.

NodeType

ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.

@ SIGN_EXTEND

Conversion operators.

MemIndexedMode

MemIndexedMode enum - This enum defines the load / store indexed addressing modes.

CondCode

ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...

This namespace contains an enum with a value for every intrinsic/builtin function known by LLVM.

static constexpr unsigned RVVBitsPerBlock

This is an optimization pass for GlobalISel generic memory operations.

bool RISCVCCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State, bool IsRet, Type *OrigTy)

RISCVCCAssignFn - This target-specific function extends the default CCValAssign with additional infor...

AtomicOrdering

Atomic ordering for LLVM's memory model.

DWARFExpression::Operation Op

This struct is a compact representation of a valid (non-zero power of two) alignment.

bool isFloatingPoint() const

Return true if this is a FP or a vector FP type.

bool isScalarInteger() const

Return true if this is an integer, but not a vector.

bool isInteger() const

Return true if this is an integer or a vector integer type.

uint8_t VLOperand