LLVM: llvm::RISCV Namespace Reference (original) (raw)

Classes
struct	CPUInfo
struct	CPUModel
struct	NDSVLNPseudo
struct	RISCVMaskedPseudoInfo
struct	VLEPseudo
struct	VLSEGPseudo
struct	VLX_VSXPseudo
struct	VLXSEGPseudo
struct	VSEPseudo
struct	VSSEGPseudo
struct	VSXSEGPseudo
struct	VXMemOpInfo

Enumerations
enum	PartialMappingIdx { PMI_GPRB32 = 0 , PMI_GPRB64 = 1 , PMI_FPRB16 = 2 , PMI_FPRB32 = 3 , PMI_FPRB64 = 4 , PMI_VRB64 = 5 , PMI_VRB128 = 6 , PMI_VRB256 = 7 , PMI_VRB512 = 8 }
enum	ValueMappingIdx { InvalidIdx = 0 , GPRB32Idx = 1 , GPRB64Idx = 4 , FPRB16Idx = 7 , FPRB32Idx = 10 , FPRB64Idx = 13 , VRB64Idx = 16 , VRB128Idx = 19 , VRB256Idx = 22 , VRB512Idx = 25 }
enum	Fixups { fixup_riscv_hi20 = FirstTargetFixupKind , fixup_riscv_lo12_i, fixup_riscv_12_i, fixup_riscv_lo12_s, fixup_riscv_pcrel_hi20, fixup_riscv_pcrel_lo12_i, fixup_riscv_pcrel_lo12_s, fixup_riscv_jal, fixup_riscv_branch, fixup_riscv_rvc_jump, fixup_riscv_rvc_branch, fixup_riscv_rvc_imm, fixup_riscv_call, fixup_riscv_call_plt, fixup_riscv_qc_e_branch, fixup_riscv_qc_e_32, fixup_riscv_qc_abs20_u, fixup_riscv_qc_e_call_plt, fixup_riscv_nds_branch_10, fixup_riscv_invalid, NumTargetFixupKinds = fixup_riscv_invalid - FirstTargetFixupKind }
enum	{ S_None, S_LO = FirstTargetFixupKind , S_PCREL_LO, S_TPREL_LO, S_QC_ABS20 }
enum	CPUKind : unsigned

Functions
LLVM_ABI void	getFeaturesForCPU (StringRef CPU, SmallVectorImpl< std::string > &EnabledFeatures, bool NeedPlus=false)
LLVM_ABI bool	parseCPU (StringRef CPU, bool IsRV64)
LLVM_ABI bool	parseTuneCPU (StringRef CPU, bool IsRV64)
LLVM_ABI StringRef	getMArchFromMcpu (StringRef CPU)
LLVM_ABI void	fillValidCPUArchList (SmallVectorImpl< StringRef > &Values, bool IsRV64)
LLVM_ABI void	fillValidTuneCPUArchList (SmallVectorImpl< StringRef > &Values, bool IsRV64)
LLVM_ABI bool	hasFastScalarUnalignedAccess (StringRef CPU)
LLVM_ABI bool	hasFastVectorUnalignedAccess (StringRef CPU)
LLVM_ABI bool	hasValidCPUModel (StringRef CPU)
LLVM_ABI CPUModel	getCPUModel (StringRef CPU)
LLVM_ABI StringRef	getCPUNameFromCPUModel (const CPUModel &Model)
Specifier	parseSpecifierName (StringRef name)
StringRef	getSpecifierName (Specifier Kind)
ArrayRef< MCPhysReg >	getArgGPRs (const RISCVABI::ABI ABI)
bool	isRVVSpill (const MachineInstr &MI)
std::optional< std::pair< unsigned, unsigned > >	isRVVSpillForZvlsseg (unsigned Opcode)
bool	hasEqualFRM (const MachineInstr &MI1, const MachineInstr &MI2)
std::optional< unsigned >	getVectorLowDemandedScalarBits (unsigned Opcode, unsigned Log2SEW)
unsigned	getRVVMCOpcode (unsigned RVVPseudoOpcode)
unsigned	getDestLog2EEW (const MCInstrDesc &Desc, unsigned Log2SEW)
bool	isVLKnownLE (const MachineOperand &LHS, const MachineOperand &RHS)
	Given two VL operands, do we know that LHS <= RHS?
static const CPUInfo *	getCPUInfoByName (StringRef CPU)

Variables
static constexpr unsigned	RVVBitsPerBlock = 64
static constexpr unsigned	RVVBytesPerBlock = RVVBitsPerBlock / 8
const RegisterBankInfo::PartialMapping	PartMappings []
const RegisterBankInfo::ValueMapping	ValueMappings []
static constexpr int64_t	VLMaxSentinel = -1LL
static constexpr unsigned	FPMASK_Negative_Infinity = 0x001
static constexpr unsigned	FPMASK_Negative_Normal = 0x002
static constexpr unsigned	FPMASK_Negative_Subnormal = 0x004
static constexpr unsigned	FPMASK_Negative_Zero = 0x008
static constexpr unsigned	FPMASK_Positive_Zero = 0x010
static constexpr unsigned	FPMASK_Positive_Subnormal = 0x020
static constexpr unsigned	FPMASK_Positive_Normal = 0x040
static constexpr unsigned	FPMASK_Positive_Infinity = 0x080
static constexpr unsigned	FPMASK_Signaling_NaN = 0x100
static constexpr unsigned	FPMASK_Quiet_NaN = 0x200
constexpr CPUInfo	RISCVCPUInfo []

◆ Specifier

◆ anonymous enum

Enumerator
S_None
S_LO
S_PCREL_LO
S_TPREL_LO
S_QC_ABS20

Definition at line 38 of file RISCVMCAsmInfo.h.

◆ CPUKind

◆ Fixups

Enumerator
fixup_riscv_hi20
fixup_riscv_lo12_i
fixup_riscv_12_i
fixup_riscv_lo12_s
fixup_riscv_pcrel_hi20
fixup_riscv_pcrel_lo12_i
fixup_riscv_pcrel_lo12_s
fixup_riscv_jal
fixup_riscv_branch
fixup_riscv_rvc_jump
fixup_riscv_rvc_branch
fixup_riscv_rvc_imm
fixup_riscv_call
fixup_riscv_call_plt
fixup_riscv_qc_e_branch
fixup_riscv_qc_e_32
fixup_riscv_qc_abs20_u
fixup_riscv_qc_e_call_plt
fixup_riscv_nds_branch_10
fixup_riscv_invalid
NumTargetFixupKinds

Definition at line 18 of file RISCVFixupKinds.h.

◆ PartialMappingIdx

Enumerator
PMI_GPRB32
PMI_GPRB64
PMI_FPRB16
PMI_FPRB32
PMI_FPRB64
PMI_VRB64
PMI_VRB128
PMI_VRB256
PMI_VRB512

Definition at line 42 of file RISCVRegisterBankInfo.cpp.

◆ ValueMappingIdx

Enumerator
InvalidIdx
GPRB32Idx
GPRB64Idx
FPRB16Idx
FPRB32Idx
FPRB64Idx
VRB64Idx
VRB128Idx
VRB256Idx
VRB512Idx

Definition at line 95 of file RISCVRegisterBankInfo.cpp.

◆ fillValidCPUArchList()

◆ fillValidTuneCPUArchList()

◆ getArgGPRs()

◆ getCPUInfoByName()

◆ getCPUModel()

◆ getCPUNameFromCPUModel()

◆ getDestLog2EEW()

◆ getFeaturesForCPU()

◆ getMArchFromMcpu()

◆ getRVVMCOpcode()

◆ getSpecifierName()

◆ getVectorLowDemandedScalarBits()

◆ hasEqualFRM()

◆ hasFastScalarUnalignedAccess()

◆ hasFastVectorUnalignedAccess()

◆ hasValidCPUModel()

◆ isRVVSpill()

◆ isRVVSpillForZvlsseg()

◆ isVLKnownLE()

◆ parseCPU()

◆ parseSpecifierName()

◆ parseTuneCPU()

◆ FPMASK_Negative_Infinity

unsigned llvm::RISCV::FPMASK_Negative_Infinity = 0x001	staticconstexpr

◆ FPMASK_Negative_Normal

unsigned llvm::RISCV::FPMASK_Negative_Normal = 0x002	staticconstexpr

◆ FPMASK_Negative_Subnormal

unsigned llvm::RISCV::FPMASK_Negative_Subnormal = 0x004	staticconstexpr

◆ FPMASK_Negative_Zero

unsigned llvm::RISCV::FPMASK_Negative_Zero = 0x008	staticconstexpr

◆ FPMASK_Positive_Infinity

unsigned llvm::RISCV::FPMASK_Positive_Infinity = 0x080	staticconstexpr

◆ FPMASK_Positive_Normal

unsigned llvm::RISCV::FPMASK_Positive_Normal = 0x040	staticconstexpr

◆ FPMASK_Positive_Subnormal

unsigned llvm::RISCV::FPMASK_Positive_Subnormal = 0x020	staticconstexpr

◆ FPMASK_Positive_Zero

unsigned llvm::RISCV::FPMASK_Positive_Zero = 0x010	staticconstexpr

◆ FPMASK_Quiet_NaN

unsigned llvm::RISCV::FPMASK_Quiet_NaN = 0x200	staticconstexpr

◆ FPMASK_Signaling_NaN

unsigned llvm::RISCV::FPMASK_Signaling_NaN = 0x100	staticconstexpr

◆ PartMappings

Initial value:

= {

{0, 32, GPRBRegBank},

{0, 64, GPRBRegBank},

{0, 16, FPRBRegBank},

{0, 32, FPRBRegBank},

{0, 64, FPRBRegBank},

{0, 64, VRBRegBank},

{0, 128, VRBRegBank},

{0, 256, VRBRegBank},

{0, 512, VRBRegBank},

}

Definition at line 28 of file RISCVRegisterBankInfo.cpp.

◆ RISCVCPUInfo

CPUInfo llvm::RISCV::RISCVCPUInfo[]	constexpr

Initial value:

= {

#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID)

}

Definition at line 30 of file RISCVTargetParser.cpp.

Referenced by fillValidCPUArchList(), fillValidTuneCPUArchList(), getCPUInfoByName(), and getCPUNameFromCPUModel().

◆ RVVBitsPerBlock

unsigned llvm::RISCV::RVVBitsPerBlock = 64	staticconstexpr

Definition at line 51 of file RISCVTargetParser.h.

Referenced by computeKnownBitsFromOperator(), llvm::RISCVTargetLowering::computeVLMAX(), llvm::RISCVSubtarget::expandVScale(), getContainerForFixedLengthVector(), getLMUL1Ty(), llvm::RISCVTargetLowering::getM1VT(), llvm::RISCVTTIImpl::getMaxVScale(), llvm::RISCVTargetLowering::getRegClassIDForVecVT(), llvm::RISCVTTIImpl::getRegisterBitWidth(), llvm::RISCVTTIImpl::getRegUsageForType(), llvm::RISCVTargetMachine::getSubtargetImpl(), llvm::RISCVTTIImpl::getVScaleForTuning(), isTupleInsertInstr(), isValidEGW(), llvm::RISCVTargetLowering::isVScaleKnownToBeAPowerOfTwo(), llvm::RISCVInstrInfo::loadRegFromStackSlot(), lowerGetVectorLength(), llvm::RISCVTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::selectVLXSEG(), llvm::RISCVDAGToDAGISel::selectVSXSEG(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), llvm::RISCVInstrInfo::storeRegToStackSlot(), and llvm::RISCVSubtarget::useRVVForFixedLengthVectors().

◆ RVVBytesPerBlock

◆ ValueMappings

◆ VLMaxSentinel

int64_t llvm::RISCV::VLMaxSentinel = -1LL	staticconstexpr