RISCVPostLegalizerCombiner.cpp Source File (original) (raw)

32#define GET_GICOMBINER_DEPS

33#include "RISCVGenPostLegalizeGICombiner.inc"

34#undef GET_GICOMBINER_DEPS

36#define DEBUG_TYPE "riscv-postlegalizer-combiner"

38using namespace llvm;

40namespace {

42#define GET_GICOMBINER_TYPES

43#include "RISCVGenPostLegalizeGICombiner.inc"

44#undef GET_GICOMBINER_TYPES

50 if (MI.getOpcode() != TargetOpcode::G_STORE)

51 return false;

53 Register SrcReg = MI.getOperand(0).getReg();

55 return false;

58 if (!Def || Def->getOpcode() != TargetOpcode::G_FCONSTANT)

59 return false;

61 auto *CFP = Def->getOperand(1).getFPImm();

62 if (!CFP || !CFP->getValueAPF().isPosZero())

63 return false;

65 unsigned ValBits = MRI.getType(SrcReg).getSizeInBits();

66 if ((ValBits == 16 && !STI.hasStdExtZfh()) ||

67 (ValBits == 32 && !STI.hasStdExtF()) ||

68 (ValBits == 64 && (!STI.hasStdExtD() || !STI.is64Bit())))

69 return false;

71 MatchInfo = SrcReg;

72 return true;

73}

79 const unsigned XLen = STI.getXLen();

82 MI.getOperand(0).setReg(Zero.getReg(0));

85 if (Def && MRI.use_nodbg_empty(MatchInfo))

86 Def->eraseFromParent();

88#ifndef NDEBUG

89 unsigned ValBits = MRI.getType(MatchInfo).getSizeInBits();

91 "(XLEN={1}, ValBits={2}):\n {3}\n",

93#endif

94}

96class RISCVPostLegalizerCombinerImpl : public Combiner {

97protected:

98 const CombinerHelper Helper;

99 const RISCVPostLegalizerCombinerImplRuleConfig &RuleConfig;

100 const RISCVSubtarget &STI;

101

102public:

103 RISCVPostLegalizerCombinerImpl(

104 MachineFunction &MF, CombinerInfo &CInfo, const TargetPassConfig *TPC,

105 GISelValueTracking &VT, GISelCSEInfo *CSEInfo,

106 const RISCVPostLegalizerCombinerImplRuleConfig &RuleConfig,

107 const RISCVSubtarget &STI, MachineDominatorTree *MDT,

108 const LegalizerInfo *LI);

109

110 static const char *getName() { return "RISCVPostLegalizerCombiner"; }

111

112 bool tryCombineAll(MachineInstr &I) const override;

113

114private:

115#define GET_GICOMBINER_CLASS_MEMBERS

116#include "RISCVGenPostLegalizeGICombiner.inc"

117#undef GET_GICOMBINER_CLASS_MEMBERS

118};

119

120#define GET_GICOMBINER_IMPL

121#include "RISCVGenPostLegalizeGICombiner.inc"

122#undef GET_GICOMBINER_IMPL

123

124RISCVPostLegalizerCombinerImpl::RISCVPostLegalizerCombinerImpl(

127 const RISCVPostLegalizerCombinerImplRuleConfig &RuleConfig,

130 : Combiner(MF, CInfo, TPC, &VT, CSEInfo),

131 Helper(Observer, B, false, &VT, MDT, LI),

132 RuleConfig(RuleConfig), STI(STI),

134#include "RISCVGenPostLegalizeGICombiner.inc"

136{

137}

138

140public:

141 static char ID;

142

143 RISCVPostLegalizerCombiner();

144

146 return "RISCVPostLegalizerCombiner";

147 }

148

151

152private:

153 RISCVPostLegalizerCombinerImplRuleConfig RuleConfig;

154};

155}

156

157void RISCVPostLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {

168}

169

170RISCVPostLegalizerCombiner::RISCVPostLegalizerCombiner()

172 if (!RuleConfig.parseCommandLineOption())

174}

175

176bool RISCVPostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {

178 return false;

179 assert(MF.getProperties().hasLegalized() && "Expected a legalized function?");

180 auto *TPC = &getAnalysis();

182 bool EnableOpt =

184

186 const auto *LI = ST.getLegalizerInfo();

187

189 &getAnalysis().get(MF);

191 &getAnalysis().getDomTree();

193 getAnalysis().getCSEWrapper();

194 auto *CSEInfo = &Wrapper.get(TPC->getCSEConfig());

195

196 CombinerInfo CInfo( true, false,

197 nullptr, EnableOpt, F.hasOptSize(),

198 F.hasMinSize());

199 RISCVPostLegalizerCombinerImpl Impl(MF, CInfo, TPC, *VT, CSEInfo, RuleConfig,

200 ST, MDT, LI);

201 return Impl.combineMachineInstrs();

202}

203

204char RISCVPostLegalizerCombiner::ID = 0;

206 "Combine RISC-V MachineInstrs after legalization", false,

207 false)

211 "Combine RISC-V MachineInstrs after legalization", false,

213

215 return new RISCVPostLegalizerCombiner();

216}

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

#define GET_GICOMBINER_CONSTRUCTOR_INITS

amdgpu aa AMDGPU Address space based Alias Analysis Wrapper

static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")

Provides analysis for continuously CSEing during GISel passes.

This contains common combine transformations that may be used in a combine pass,or by the target else...

Option class for Targets to specify which operations are combined how and when.

This contains the base class for all Combiners generated by TableGen.

Provides analysis for querying information about KnownBits during GISel passes.

This file declares the MachineIRBuilder class.

#define INITIALIZE_PASS_DEPENDENCY(depName)

#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)

#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)

static StringRef getName(Value *V)

Target-Independent Code Generator Pass Configuration Options pass.

Represent the analysis usage information of a pass.

AnalysisUsage & addRequired()

AnalysisUsage & addPreserved()

Add the specified Pass class to the set of analyses preserved by this pass.

LLVM_ABI void setPreservesCFG()

This function should be called by the pass, iff they do not:

FunctionPass class - This class is used to implement most global optimizations.

The actual analysis pass wrapper.

Simple wrapper that does the following.

To use KnownBitsInfo analysis in a pass, KnownBitsInfo &Info = getAnalysis<GISelValueTrackingInfoAnal...

static constexpr LLT scalar(unsigned SizeInBits)

Get a low-level scalar or aggregate "bag of bits".

Analysis pass which computes a MachineDominatorTree.

DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...

MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...

void getAnalysisUsage(AnalysisUsage &AU) const override

getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.

virtual bool runOnMachineFunction(MachineFunction &MF)=0

runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...

const TargetSubtargetInfo & getSubtarget() const

getSubtarget - Return the subtarget for which this machine code is being compiled.

Function & getFunction()

Return the LLVM function that this machine code represents.

const MachineFunctionProperties & getProperties() const

Get the function properties.

const TargetMachine & getTarget() const

getTarget - Return the target machine this machine code is compiled with

Helper class to build MachineInstr.

Representation of each machine instruction.

MachineRegisterInfo - Keep track of information for virtual and physical registers,...

virtual StringRef getPassName() const

getPassName - Return a nice clean name for a pass.

Wrapper class representing virtual and physical registers.

constexpr bool isVirtual() const

Return true if the specified register number is in the virtual register namespace.

CodeGenOptLevel getOptLevel() const

Returns the optimization level: None, Less, Default, or Aggressive.

Target-Independent Code Generator Pass Configuration Options.

unsigned ID

LLVM IR allows to use arbitrary numbers as calling convention identifiers.

NodeAddr< DefNode * > Def

This is an optimization pass for GlobalISel generic memory operations.

FunctionPass * createRISCVPostLegalizerCombiner()

Definition RISCVPostLegalizerCombiner.cpp:214

auto formatv(bool Validate, const char *Fmt, Ts &&...Vals)

LLVM_ABI raw_ostream & dbgs()

dbgs() - This returns a reference to a raw_ostream for debugging messages.

LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)

LLVM_ABI void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU)

Modify analysis usage so it preserves passes required for the SelectionDAG fallback.