RISCVSubtarget.h Source File (original) (raw)

13#ifndef LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H

14#define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H

29#include

31#define GET_RISCV_MACRO_FUSION_PRED_DECL

32#include "RISCVGenMacroFusion.inc"

34#define GET_SUBTARGETINFO_HEADER

35#include "RISCVGenSubtargetInfo.inc"

37namespace llvm {

38class StringRef;

40namespace RISCVTuneInfoTable {

73};

75#define GET_RISCVTuneInfoTable_DECL

76#include "RISCVGenSearchableTables.inc"

77}

80public:

94private:

95 virtual void anchor();

97 RISCVProcFamilyEnum RISCVProcFamily = Others;

98 RISCVVRGatherCostModelEnum RISCVVRGatherCostModel = Quadratic;

100#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \

101 bool ATTRIBUTE = DEFAULT;

102#include "RISCVGenSubtargetInfo.inc"

103

104 unsigned XSfmmTE = 0;

105 unsigned ZvlLen = 0;

106 unsigned RVVVectorBitsMin;

107 unsigned RVVVectorBitsMax;

110 std::bitsetRISCV::NUM\_TARGET\_REGS UserReservedRegister;

111 const RISCVTuneInfoTable::RISCVTuneInfo *TuneInfo;

112

113 RISCVFrameLowering FrameLowering;

114 RISCVInstrInfo InstrInfo;

115 RISCVTargetLowering TLInfo;

116

117

118

119 RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT,

120 StringRef CPU,

121 StringRef TuneCPU,

122 StringRef FS,

123 StringRef ABIName);

124

125public:

126

127 RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU,

128 StringRef FS, StringRef ABIName, unsigned RVVVectorBitsMin,

130

132

133

134

136

138 return &FrameLowering;

139 }

142 return &InstrInfo.getRegisterInfo();

143 }

145 return &TLInfo;

146 }

147

149

151

153 return Align(TuneInfo->PrefFunctionAlignment);

154 }

156 return Align(TuneInfo->PrefLoopAlignment);

157 }

158

159

160

161

162

164

166

167#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \

168 bool GETTER() const { return ATTRIBUTE; }

169#include "RISCVGenSubtargetInfo.inc"

170

171 LLVM_DEPRECATED("Now Equivalent to hasStdExtZca", "hasStdExtZca")

175 return HasStdExtC || HasStdExtZcf || HasStdExtZce;

176 }

182 return HasStdExtZfhmin || HasStdExtZhinxmin;

183 }

185 return HasStdExtZfhmin || HasStdExtZfbfmin;

186 }

187

189 return HasStdExtZbb || HasVendorXTHeadBb ||

190 (HasVendorXCVbitmanip && !IsRV64);

191 }

193 return HasStdExtZbb || (HasVendorXCVbitmanip && !IsRV64);

194 }

196 return HasStdExtZbb || (HasVendorXCVbitmanip && !IsRV64);

197 }

199 return HasStdExtZbb || HasStdExtZbkb || HasVendorXTHeadBb;

200 }

201

202 bool hasBEXTILike() const { return HasStdExtZbs || HasVendorXTHeadBs; }

203

205 return HasStdExtZicond || HasVendorXVentanaCondOps;

206 }

207

209

210 return (hasConditionalCompressedMoveFusion() && hasStdExtZca()) ||

211 hasShortForwardBranchIALU();

212 }

213

215 if (ShAmt <= 0)

216 return false;

217 if (ShAmt <= 3)

218 return HasStdExtZba || HasVendorXAndesPerf || HasVendorXTHeadBa;

219 return ShAmt <= 31 && HasVendorXqciac;

220 }

221

222 bool is64Bit() const { return IsRV64; }

224 return is64Bit() ? MVT::i64 : MVT::i32;

225 }

227 return is64Bit() ? 64 : 32;

228 }

232 if (HasStdExtD)

233 return 64;

234

235 if (HasStdExtF)

236 return 32;

237

238 return 0;

239 }

240

242 return Align(enableUnalignedScalarMem() ? 1

243 : allowZilsd4ByteAlign() ? 4

244 : 8);

245 }

246

253 return VLen == 0 ? ZvlLen : VLen;

254 }

257 return VLen == 0 ? 65536 : VLen;

258 }

259

263 return std::nullopt;

264 return Min;

265 }

266

267

268

269

270 template Quantity expandVScale(Quantity X) const {

271 if (auto VLen = getRealVLen(); VLen && X.isScalable()) {

273 X = Quantity::getFixed(X.getKnownMinValue() * VScale);

274 }

275 return X;

276 }

277

285 assert(i.id() < RISCV::NUM_TARGET_REGS && "Register out of range");

286 return UserReservedRegister[i.id()];

287 }

288

289

290 bool isXRaySupported() const override { return hasStdExtD() && hasStdExtC(); }

291

292

298 return HasStdExtZvfbfmin || HasStdExtZvfbfa;

299 }

303

309

311 switch (NF) {

312 case 2:

313 return hasOptimizedNF2SegmentLoadStore();

314 case 3:

315 return hasOptimizedNF3SegmentLoadStore();

316 case 4:

317 return hasOptimizedNF4SegmentLoadStore();

318 case 5:

319 return hasOptimizedNF5SegmentLoadStore();

320 case 6:

321 return hasOptimizedNF6SegmentLoadStore();

322 case 7:

323 return hasOptimizedNF7SegmentLoadStore();

324 case 8:

325 return hasOptimizedNF8SegmentLoadStore();

326 default:

328 }

329 }

330

332

333

334

336 if (DLenFactor2)

337 return 2;

338 return 1;

339 }

340

341protected:

342

343 std::unique_ptr TSInfo;

344

345

347 mutable std::unique_ptr InstSelector;

348 mutable std::unique_ptr Legalizer;

349 mutable std::unique_ptr RegBankInfo;

350

351

352

353

354

357

358public:

364

365 bool isTargetAndroid() const { return getTargetTriple().isAndroid(); }

366 bool isTargetFuchsia() const { return getTargetTriple().isOSFuchsia(); }

367

369

370

371

373

376

378

380

382

383 bool useAA() const override;

384

386 return TuneInfo->CacheLineSize;

387 };

389 return TuneInfo->PrefetchDistance;

390 };

392 unsigned NumStridedMemAccesses,

393 unsigned NumPrefetches,

394 bool HasCall) const override {

395 return TuneInfo->MinPrefetchStride;

396 };

398 return TuneInfo->MaxPrefetchIterationsAhead;

399 };

401

403

405 return TuneInfo->TailDupAggressiveThreshold;

406 }

407

409 return OptSize ? TuneInfo->MaxStoresPerMemsetOptSize

410 : TuneInfo->MaxStoresPerMemset;

411 }

412

414 return TuneInfo->MaxGluedStoresPerMemcpy;

415 }

416

418 return OptSize ? TuneInfo->MaxStoresPerMemcpyOptSize

419 : TuneInfo->MaxStoresPerMemcpy;

420 }

421

423 return OptSize ? TuneInfo->MaxStoresPerMemmoveOptSize

424 : TuneInfo->MaxStoresPerMemmove;

425 }

426

428 return OptSize ? TuneInfo->MaxLoadsPerMemcmpOptSize

429 : TuneInfo->MaxLoadsPerMemcmp;

430 }

431

433 return TuneInfo->PostRASchedDirection;

434 }

435

438

441};

442}

443

444#endif

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

This file describes how to lower LLVM calls to machine code calls.

#define LLVM_DEPRECATED(MSG, FIX)

Interface for Targets to specify which operations they can successfully select and how the others sho...

static const unsigned MaxInterleaveFactor

Maximum vectorization interleave count.

This file declares the targeting of the RegisterBankInfo class for RISC-V.

static cl::opt< unsigned > RVVVectorLMULMax("riscv-v-fixed-length-vector-lmul-max", cl::desc("The maximum LMUL value to use for fixed length vectors. " "Fractional LMUL values are not supported."), cl::init(8), cl::Hidden)

static TableGen::Emitter::OptClass< SkeletonEmitter > X("gen-skeleton-class", "Generate example skeleton class")

This class provides the information for the target register banks.

RISCVABI::ABI getTargetABI() const

Definition RISCVSubtarget.h:278

unsigned getMinimumJumpTableEntries() const

RISCVVRGatherCostModelEnum

Definition RISCVSubtarget.h:89

@ NLog2N

Definition RISCVSubtarget.h:91

@ Quadratic

Definition RISCVSubtarget.h:90

bool hasStdExtCOrZca() const

Definition RISCVSubtarget.h:172

const LegalizerInfo * getLegalizerInfo() const override

void overrideSchedPolicy(MachineSchedPolicy &Policy, const SchedRegion &Region) const override

bool enableWritePrefetching() const override

Definition RISCVSubtarget.h:400

std::unique_ptr< LegalizerInfo > Legalizer

Definition RISCVSubtarget.h:348

unsigned getMaxLMULForFixedLengthVectors() const

bool hasVInstructionsI64() const

Definition RISCVSubtarget.h:294

unsigned getMaxPrefetchIterationsAhead() const override

Definition RISCVSubtarget.h:397

bool hasVInstructionsF64() const

Definition RISCVSubtarget.h:301

unsigned getMaxStoresPerMemcpy(bool OptSize) const

Definition RISCVSubtarget.h:417

bool hasStdExtDOrZdinx() const

Definition RISCVSubtarget.h:179

RISCVProcFamilyEnum

Definition RISCVSubtarget.h:82

@ VentanaVeyron

Definition RISCVSubtarget.h:85

@ MIPSP8700

Definition RISCVSubtarget.h:86

@ Others

Definition RISCVSubtarget.h:83

@ Andes45

Definition RISCVSubtarget.h:87

@ SiFive7

Definition RISCVSubtarget.h:84

unsigned getMaxLoadsPerMemcmp(bool OptSize) const

Definition RISCVSubtarget.h:427

bool hasStdExtZfhOrZhinx() const

Definition RISCVSubtarget.h:180

bool hasShlAdd(int64_t ShAmt) const

Definition RISCVSubtarget.h:214

bool useDFAforSMS() const override

Definition RISCVSubtarget.h:381

unsigned getTailDupAggressiveThreshold() const

Definition RISCVSubtarget.h:404

unsigned getRealMinVLen() const

Definition RISCVSubtarget.h:251

unsigned getMaxStoresPerMemset(bool OptSize) const

Definition RISCVSubtarget.h:408

bool useMIPSLoadStorePairs() const

Quantity expandVScale(Quantity X) const

If the ElementCount or TypeSize X is scalable and VScale (VLEN) is exactly known, returns X converted...

Definition RISCVSubtarget.h:270

bool useRVVForFixedLengthVectors() const

RISCVVRGatherCostModelEnum getVRGatherCostModel() const

Definition RISCVSubtarget.h:165

MISched::Direction getPostRASchedDirection() const

Definition RISCVSubtarget.h:432

bool hasREV8Like() const

Definition RISCVSubtarget.h:198

bool isTargetFuchsia() const

Definition RISCVSubtarget.h:366

bool hasVInstructionsBF16Minimal() const

Definition RISCVSubtarget.h:297

unsigned getDLenFactor() const

Definition RISCVSubtarget.h:335

bool hasCPOPLike() const

Definition RISCVSubtarget.h:195

MVT getXLenVT() const

Definition RISCVSubtarget.h:223

unsigned getMaxStoresPerMemmove(bool OptSize) const

Definition RISCVSubtarget.h:422

unsigned getMinRVVVectorSizeInBits() const

std::unique_ptr< InstructionSelector > InstSelector

Definition RISCVSubtarget.h:347

bool hasVInstructionsF16Minimal() const

Definition RISCVSubtarget.h:295

RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName, unsigned RVVVectorBitsMin, unsigned RVVVectorLMULMax, const TargetMachine &TM)

unsigned getMaxGluedStoresPerMemcpy() const

Definition RISCVSubtarget.h:413

unsigned getXLen() const

Definition RISCVSubtarget.h:226

bool hasConditionalMoveFusion() const

Definition RISCVSubtarget.h:208

bool hasCTZLike() const

Definition RISCVSubtarget.h:192

bool useMIPSCCMovInsn() const

bool hasVInstructionsF16() const

Definition RISCVSubtarget.h:296

bool hasVInstructionsBF16() const

Definition RISCVSubtarget.h:302

const RISCVRegisterBankInfo * getRegBankInfo() const override

const CallLowering * getCallLowering() const override

bool enableMachineScheduler() const override

Definition RISCVSubtarget.h:148

InstructionSelector * getInstructionSelector() const override

unsigned getMaxBuildIntsCost() const

Align getPrefLoopAlignment() const

Definition RISCVSubtarget.h:155

bool hasCLZLike() const

Definition RISCVSubtarget.h:188

std::unique_ptr< const SelectionDAGTargetInfo > TSInfo

Definition RISCVSubtarget.h:343

bool hasVInstructions() const

Definition RISCVSubtarget.h:293

bool useAA() const override

Enable use of alias analysis during code generation (during MI scheduling, DAGCombine,...

bool isRegisterReservedByUser(Register i) const override

Definition RISCVSubtarget.h:284

bool hasVInstructionsAnyF() const

Definition RISCVSubtarget.h:304

std::optional< unsigned > getRealVLen() const

Definition RISCVSubtarget.h:260

bool isXRaySupported() const override

Definition RISCVSubtarget.h:290

bool enableMachinePipeliner() const override

bool hasOptimizedSegmentLoadStore(unsigned NF) const

Definition RISCVSubtarget.h:310

bool useConstantPoolForLargeInts() const

bool hasStdExtCOrZcfOrZce() const

Definition RISCVSubtarget.h:174

Align getPrefFunctionAlignment() const

Definition RISCVSubtarget.h:152

~RISCVSubtarget() override

RISCVProcFamilyEnum getProcFamily() const

Returns RISC-V processor family.

Definition RISCVSubtarget.h:163

unsigned getMaxRVVVectorSizeInBits() const

bool hasStdExtZfhminOrZhinxmin() const

Definition RISCVSubtarget.h:181

unsigned getRealMaxVLen() const

Definition RISCVSubtarget.h:255

unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const override

Definition RISCVSubtarget.h:391

void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)

const RISCVRegisterInfo * getRegisterInfo() const override

Definition RISCVSubtarget.h:141

Align getZilsdAlign() const

Definition RISCVSubtarget.h:241

std::unique_ptr< RISCVRegisterBankInfo > RegBankInfo

Definition RISCVSubtarget.h:349

const RISCVInstrInfo * getInstrInfo() const override

Definition RISCVSubtarget.h:140

unsigned getCacheLineSize() const override

Definition RISCVSubtarget.h:385

std::unique_ptr< CallLowering > CallLoweringInfo

Definition RISCVSubtarget.h:346

bool hasBEXTILike() const

Definition RISCVSubtarget.h:202

bool hasStdExtCOrZcd() const

Definition RISCVSubtarget.h:173

bool hasVInstructionsFullMultiply() const

Definition RISCVSubtarget.h:305

const RISCVTargetLowering * getTargetLowering() const override

Definition RISCVSubtarget.h:144

bool enablePExtCodeGen() const

void overridePostRASchedPolicy(MachineSchedPolicy &Policy, const SchedRegion &Region) const override

bool hasVInstructionsF32() const

Definition RISCVSubtarget.h:300

unsigned getMaxInterleaveFactor() const

Definition RISCVSubtarget.h:306

bool hasCZEROLike() const

Definition RISCVSubtarget.h:204

bool enableSubRegLiveness() const override

unsigned getELen() const

Definition RISCVSubtarget.h:247

const SelectionDAGTargetInfo * getSelectionDAGInfo() const override

bool isTargetAndroid() const

Definition RISCVSubtarget.h:365

bool hasStdExtFOrZfinx() const

Definition RISCVSubtarget.h:178

bool enablePostRAScheduler() const override

Definition RISCVSubtarget.h:150

bool hasStdExtZvl() const

Definition RISCVSubtarget.h:177

bool isSoftFPABI() const

Definition RISCVSubtarget.h:279

bool hasHalfFPLoadStoreMove() const

Definition RISCVSubtarget.h:184

const RISCVFrameLowering * getFrameLowering() const override

Definition RISCVSubtarget.h:137

unsigned getFLen() const

Definition RISCVSubtarget.h:231

unsigned getPrefetchDistance() const override

Definition RISCVSubtarget.h:388

bool is64Bit() const

Definition RISCVSubtarget.h:222

Wrapper class representing virtual and physical registers.

constexpr unsigned id() const

Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...

StringRef - Represent a constant reference to a string, i.e.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

static constexpr unsigned RVVBitsPerBlock

This is an optimization pass for GlobalISel generic memory operations.

This struct is a compact representation of a valid (non-zero power of two) alignment.

Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.

Definition RISCVSubtarget.h:42

uint16_t PrefetchDistance

Definition RISCVSubtarget.h:49

uint8_t PrefLoopAlignment

Definition RISCVSubtarget.h:45

const char * Name

Definition RISCVSubtarget.h:43

unsigned MaxStoresPerMemmoveOptSize

Definition RISCVSubtarget.h:65

uint16_t CacheLineSize

Definition RISCVSubtarget.h:48

unsigned MaxGluedStoresPerMemcpy

Definition RISCVSubtarget.h:61

unsigned MaxStoresPerMemmove

Definition RISCVSubtarget.h:66

unsigned MaxLoadsPerMemcmpOptSize

Definition RISCVSubtarget.h:68

uint8_t PrefFunctionAlignment

Definition RISCVSubtarget.h:44

unsigned MaxPrefetchIterationsAhead

Definition RISCVSubtarget.h:51

unsigned TailDupAggressiveThreshold

Definition RISCVSubtarget.h:56

uint16_t MinPrefetchStride

Definition RISCVSubtarget.h:50

unsigned MaxLoadsPerMemcmp

Definition RISCVSubtarget.h:69

unsigned MinimumJumpTableEntries

Definition RISCVSubtarget.h:53

unsigned MaxStoresPerMemset

Definition RISCVSubtarget.h:59

unsigned MaxStoresPerMemsetOptSize

Definition RISCVSubtarget.h:58

unsigned MaxStoresPerMemcpy

Definition RISCVSubtarget.h:63

unsigned MaxStoresPerMemcpyOptSize

Definition RISCVSubtarget.h:62

MISched::Direction PostRASchedDirection

Definition RISCVSubtarget.h:72

A region of an MBB for scheduling.