RISCVTargetParser.cpp Source File (original) (raw)

19namespace llvm {

23#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, \

24 FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID) \

25 CK_##ENUM,

26#define TUNE_PROC(ENUM, NAME) CK_##ENUM,

27#include "llvm/TargetParser/RISCVTargetParserDef.inc"

28};

31#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, \

32 FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID) \

33 { \

34 NAME, \

35 DEFAULT_MARCH, \

36 FAST_SCALAR_UNALIGN, \

37 FAST_VECTOR_UNALIGN, \

38 {MVENDORID, MARCHID, MIMPID}, \

39 },

40#include "llvm/TargetParser/RISCVTargetParserDef.inc"

41};

45 if (C.Name == CPU)

46 return &C;

47 return nullptr;

48}

52 return Info && Info->FastScalarUnalignedAccess;

53}

57 return Info && Info->FastVectorUnalignedAccess;

58}

65 return {0, 0, 0};

66 return Info->Model;

67}

70 if (!Model.isValid())

71 return "";

74 if (C.Model == Model)

75 return C.Name;

76 return "";

77}

83 return false;

84 return Info->is64Bit() == IsRV64;

85}

88 std::optional Kind =

91 #include "llvm/TargetParser/RISCVTargetParserDef.inc"

94 if (Kind.has_value())

95 return true;

98 return parseCPU(TuneCPU, IsRV64);

99}

100

104 return "";

105 return Info->DefaultMarch;

106}

107

110 if (IsRV64 == C.is64Bit())

112 }

113}

114

117 if (IsRV64 == C.is64Bit())

119 }

120#define TUNE_PROC(ENUM, NAME) Values.emplace_back(StringRef(NAME));

121#include "llvm/TargetParser/RISCVTargetParserDef.inc"

122}

123

124

127 bool NeedPlus) {

129 if (MarchFromCPU == "")

130 return;

131

132 EnabledFeatures.clear();

134 MarchFromCPU, true);

135

137 return;

138

139 std::vectorstd::string FeatStrings =

140 (*RII)->toFeatures( false);

141 for (const auto &F : FeatStrings)

142 if (NeedPlus)

144 else

145 EnabledFeatures.push_back(F.substr(1));

146}

147

148}

149

150namespace RISCVVType {

151

152

153

154

155

156

157

158

159

160

162 bool MaskAgnostic, bool AltFmt) {

164 unsigned VLMulBits = static_cast<unsigned>(VLMul);

165 unsigned VSEWBits = encodeSEW(SEW);

166 unsigned VTypeI = (VSEWBits << 3) | (VLMulBits & 0x7);

167 if (TailAgnostic)

168 VTypeI |= 0x40;

169 if (MaskAgnostic)

170 VTypeI |= 0x80;

171 if (AltFmt)

172 VTypeI |= 0x100;

173

174 return VTypeI;

175}

176

180 unsigned VSEWBits = encodeSEW(SEW);

182 unsigned VTypeI = (VSEWBits << 3) | AltFmt << 8 | TWiden << 9;

183 return VTypeI;

184}

185

187 switch (VLMul) {

188 default:

194 return std::make_pair(1 << static_cast<unsigned>(VLMul), false);

198 return std::make_pair(1 << (8 - static_cast<unsigned>(VLMul)), true);

199 }

200}

201

203 unsigned Sew = getSEW(VType);

204 OS << "e" << Sew;

205

207 if (AltFmt)

208 OS << "alt";

209

210 unsigned LMul;

211 bool Fractional;

213

214 if (Fractional)

215 OS << ", mf";

216 else

217 OS << ", m";

218 OS << LMul;

219

221 OS << ", ta";

222 else

223 OS << ", tu";

224

226 OS << ", ma";

227 else

228 OS << ", mu";

229}

230

234

236 unsigned LMul;

237 bool Fractional;

238 std::tie(LMul, Fractional) = decodeVLMUL(VLMul);

239

240

241 LMul = Fractional ? (8 / LMul) : (LMul * 8);

242

243 assert(SEW >= 8 && "Unexpected SEW value");

244 return (SEW * 8) / LMul;

245}

246

249 unsigned EMULFixedPoint = (EEW * 8) / Ratio;

250 bool Fractional = EMULFixedPoint < 8;

251 unsigned EMUL = Fractional ? 8 / EMULFixedPoint : EMULFixedPoint / 8;

253 return std::nullopt;

255}

256

257}

258

259}

static SDValue Widen(SelectionDAG *CurDAG, SDValue N)

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

Analysis containing CSE Info

#define TUNE_PROC(ENUM, NAME)

Definition RISCVTargetParser.cpp:26

This file defines the SmallVector class.

This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...

static LLVM_ABI llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseArchString(StringRef Arch, bool EnableExperimentalExtension, bool ExperimentalExtensionVersionCheck=true)

Parse RISC-V ISA info from arch string.

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

reference emplace_back(ArgTypes &&... Args)

void push_back(const T &Elt)

StringRef - Represent a constant reference to a string, i.e.

A switch()-like statement whose cases are string literals.

StringSwitch & Case(StringLiteral S, T Value)

This class implements an extremely fast bulk output stream that can only output to a stream.

#define llvm_unreachable(msg)

Marks that the current location is not supposed to be reachable.

@ C

The default llvm calling convention, compatible with C.

static bool isTailAgnostic(unsigned VType)

static VLMUL encodeLMUL(unsigned LMUL, bool Fractional)

LLVM_ABI void printXSfmmVType(unsigned VType, raw_ostream &OS)

Definition RISCVTargetParser.cpp:231

LLVM_ABI std::optional< VLMUL > getSameRatioLMUL(unsigned SEW, VLMUL VLMUL, unsigned EEW)

Definition RISCVTargetParser.cpp:247

LLVM_ABI unsigned encodeXSfmmVType(unsigned SEW, unsigned Widen, bool AltFmt)

Definition RISCVTargetParser.cpp:177

static unsigned getXSfmmWiden(unsigned VType)

static bool isValidLMUL(unsigned LMUL, bool Fractional)

static bool isMaskAgnostic(unsigned VType)

LLVM_ABI std::pair< unsigned, bool > decodeVLMUL(VLMUL VLMul)

Definition RISCVTargetParser.cpp:186

static unsigned encodeSEW(unsigned SEW)

LLVM_ABI unsigned getSEWLMULRatio(unsigned SEW, VLMUL VLMul)

Definition RISCVTargetParser.cpp:235

static bool isValidSEW(unsigned SEW)

LLVM_ABI void printVType(unsigned VType, raw_ostream &OS)

Definition RISCVTargetParser.cpp:202

static bool isAltFmt(unsigned VType)

LLVM_ABI unsigned encodeVTYPE(VLMUL VLMUL, unsigned SEW, bool TailAgnostic, bool MaskAgnostic, bool AltFmt=false)

Definition RISCVTargetParser.cpp:161

static unsigned getSEW(unsigned VType)

static VLMUL getVLMUL(unsigned VType)

LLVM_ABI bool hasFastVectorUnalignedAccess(StringRef CPU)

Definition RISCVTargetParser.cpp:55

LLVM_ABI void getFeaturesForCPU(StringRef CPU, SmallVectorImpl< std::string > &EnabledFeatures, bool NeedPlus=false)

Definition RISCVTargetParser.cpp:125

LLVM_ABI void fillValidTuneCPUArchList(SmallVectorImpl< StringRef > &Values, bool IsRV64)

Definition RISCVTargetParser.cpp:115

static const CPUInfo * getCPUInfoByName(StringRef CPU)

Definition RISCVTargetParser.cpp:43

constexpr CPUInfo RISCVCPUInfo[]

Definition RISCVTargetParser.cpp:30

LLVM_ABI CPUModel getCPUModel(StringRef CPU)

Definition RISCVTargetParser.cpp:62

LLVM_ABI StringRef getMArchFromMcpu(StringRef CPU)

Definition RISCVTargetParser.cpp:101

CPUKind

Definition RISCVTargetParser.cpp:22

LLVM_ABI bool parseCPU(StringRef CPU, bool IsRV64)

Definition RISCVTargetParser.cpp:79

LLVM_ABI bool hasFastScalarUnalignedAccess(StringRef CPU)

Definition RISCVTargetParser.cpp:50

LLVM_ABI bool hasValidCPUModel(StringRef CPU)

Definition RISCVTargetParser.cpp:60

LLVM_ABI StringRef getCPUNameFromCPUModel(const CPUModel &Model)

Definition RISCVTargetParser.cpp:69

LLVM_ABI bool parseTuneCPU(StringRef CPU, bool IsRV64)

Definition RISCVTargetParser.cpp:87

LLVM_ABI void fillValidCPUArchList(SmallVectorImpl< StringRef > &Values, bool IsRV64)

Definition RISCVTargetParser.cpp:108

This is an optimization pass for GlobalISel generic memory operations.

bool errorToBool(Error Err)

Helper for converting an Error to a bool.

unsigned Log2_32(uint32_t Value)

Return the floor log base 2 of the specified value, -1 if the value is zero.