RegisterFile.h Source File (original) (raw)

16#ifndef LLVM_MCA_HARDWAREUNITS_REGISTERFILE_H

17#define LLVM_MCA_HARDWAREUNITS_REGISTERFILE_H

26namespace llvm {

27namespace mca {

39 unsigned IID;

40 unsigned WriteBackCycle;

41 unsigned WriteResID;

45 static const unsigned INVALID_IID;

47public:

49 : IID(INVALID_IID), WriteBackCycle(), WriteResID(), RegisterID(),

50 Write() {}

73 return Write && Other.Write && Write == Other.Write;

74 }

76#ifndef NDEBUG

77 void dump() const;

78#endif

79};

93 struct RegisterMappingTracker {

98 const unsigned NumPhysRegs;

100 unsigned NumUsedPhysRegs;

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105 const unsigned MaxMoveEliminatedPerCycle;

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113 unsigned NumMoveEliminated;

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116 bool AllowZeroMoveEliminationOnly;

117

118 RegisterMappingTracker(unsigned NumPhysRegisters,

119 unsigned MaxMoveEliminated = 0U,

120 bool AllowZeroMoveElimOnly = false)

121 : NumPhysRegs(NumPhysRegisters), NumUsedPhysRegs(0),

122 MaxMoveEliminatedPerCycle(MaxMoveEliminated), NumMoveEliminated(0U),

123 AllowZeroMoveEliminationOnly(AllowZeroMoveElimOnly) {}

124 };

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144 using IndexPlusCostPairTy = std::pair<unsigned, unsigned>;

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165 struct RegisterRenamingInfo {

166 IndexPlusCostPairTy IndexPlusCost;

169 bool AllowMoveElimination;

170 RegisterRenamingInfo()

171 : IndexPlusCost(std::make_pair(0U, 1U)), RenameAs(0U), AliasRegID(0U),

172 AllowMoveElimination(false) {}

173 };

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187 using RegisterMapping = std::pair<WriteRef, RegisterRenamingInfo>;

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190 std::vector RegisterMappings;

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194 APInt ZeroRegisters;

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196 unsigned CurrentCycle;

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217 void allocatePhysRegs(const RegisterRenamingInfo &Entry,

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222 void freePhysRegs(const RegisterRenamingInfo &Entry,

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229 void initialize(const MCSchedModel &SM, unsigned NumRegs);

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231public:

233 unsigned NumRegs = 0);

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270 unsigned PRFIndex) const;

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304#ifndef NDEBUG

305 void dump() const;

306#endif

307};

308

309}

310}

311

312#endif

This file implements a class to represent arbitrary precision integral constant values and operations...

This file defines a base class for describing a simulated hardware unit.

This file defines the SmallVector class.

Class for arbitrary precision integers.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...

Generic base class for all target subtargets.

MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

An instruction propagated through the simulated instruction pipeline.

Tracks register operand latency in cycles.

void collectWrites(const MCSubtargetInfo &STI, const ReadState &RS, SmallVectorImpl< WriteRef > &Writes, SmallVectorImpl< WriteRef > &CommittedWrites) const

unsigned getElapsedCyclesFromWriteBack(const WriteRef &WR) const

void addRegisterWrite(WriteRef Write, MutableArrayRef< unsigned > UsedPhysRegs)

unsigned isAvailable(ArrayRef< MCPhysReg > Regs) const

unsigned getNumRegisterFiles() const

Definition RegisterFile.h:293

RAWHazard checkRAWHazards(const MCSubtargetInfo &STI, const ReadState &RS) const

void removeRegisterWrite(const WriteState &WS, MutableArrayRef< unsigned > FreedPhysRegs)

bool tryEliminateMoveOrSwap(MutableArrayRef< WriteState > Writes, MutableArrayRef< ReadState > Reads)

RegisterFile(const MCSchedModel &SM, const MCRegisterInfo &mri, unsigned NumRegs=0)

void addRegisterRead(ReadState &RS, const MCSubtargetInfo &STI) const

void cycleEnd()

Definition RegisterFile.h:302

bool canEliminateMove(const WriteState &WS, const ReadState &RS, unsigned PRFIndex) const

void onInstructionExecuted(Instruction *IS)

A reference to a register write.

Definition RegisterFile.h:38

bool isAvailable() const

Returns true if this register write has been executed, and the new register value is therefore availa...

Definition RegisterFile.h:70

unsigned getSourceIndex() const

Definition RegisterFile.h:53

unsigned getWriteResourceID() const

void notifyExecuted(unsigned Cycle)

WriteRef()

Definition RegisterFile.h:48

bool operator==(const WriteRef &Other) const

Definition RegisterFile.h:72

const WriteState * getWriteState() const

Definition RegisterFile.h:56

MCPhysReg getRegisterID() const

bool isValid() const

Definition RegisterFile.h:66

WriteState * getWriteState()

Definition RegisterFile.h:57

unsigned getWriteBackCycle() const

bool hasKnownWriteBackCycle() const

Tracks uses of a register definition (e.g.

This is an optimization pass for GlobalISel generic memory operations.

uint16_t MCPhysReg

An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...

A register file descriptor.

Machine model for scheduling, bundling, and heuristics.

bool hasUnknownCycles() const

Definition RegisterFile.h:245

bool isValid() const

Definition RegisterFile.h:244

int CyclesLeft

Definition RegisterFile.h:241

MCPhysReg RegisterID

Definition RegisterFile.h:240