SPIRVInstrInfo.cpp Source File (original) (raw)

21#define GET_INSTRINFO_CTOR_DTOR

22#include "SPIRVGenInstrInfo.inc"

24using namespace llvm;

30 switch (MI.getOpcode()) {

31 case SPIRV::OpConstantTrue:

32 case SPIRV::OpConstantFalse:

33 case SPIRV::OpConstantI:

34 case SPIRV::OpConstantF:

35 case SPIRV::OpConstantComposite:

36 case SPIRV::OpConstantCompositeContinuedINTEL:

37 case SPIRV::OpConstantSampler:

38 case SPIRV::OpConstantNull:

39 case SPIRV::OpSpecConstantTrue:

40 case SPIRV::OpSpecConstantFalse:

41 case SPIRV::OpSpecConstant:

42 case SPIRV::OpSpecConstantComposite:

43 case SPIRV::OpSpecConstantCompositeContinuedINTEL:

44 case SPIRV::OpSpecConstantOp:

45 case SPIRV::OpUndef:

46 case SPIRV::OpConstantFunctionPointerINTEL:

47 return true;

48 default:

49 return false;

50 }

51}

54 switch (MI.getOpcode()) {

55 case SPIRV::OpSpecConstantTrue:

56 case SPIRV::OpSpecConstantFalse:

57 case SPIRV::OpSpecConstant:

58 case SPIRV::OpSpecConstantComposite:

59 case SPIRV::OpSpecConstantCompositeContinuedINTEL:

60 case SPIRV::OpSpecConstantOp:

61 return true;

62 default:

63 return false;

64 }

65}

68 switch (MI.getOpcode()) {

69 case SPIRV::OpAsmTargetINTEL:

70 case SPIRV::OpAsmINTEL:

71 return true;

72 default:

73 return false;

74 }

75}

78 auto &MRI = MI.getMF()->getRegInfo();

79 if (MI.getNumDefs() >= 1 && MI.getOperand(0).isReg()) {

80 auto DefRegClass = MRI.getRegClassOrNull(MI.getOperand(0).getReg());

81 return DefRegClass && DefRegClass->getID() == SPIRV::TYPERegClass.getID();

82 } else {

83 return MI.getOpcode() == SPIRV::OpTypeForwardPointer ||

84 MI.getOpcode() == SPIRV::OpTypeStructContinuedINTEL;

85 }

86}

89 switch (MI.getOpcode()) {

90 case SPIRV::OpDecorate:

91 case SPIRV::OpDecorateId:

92 case SPIRV::OpDecorateString:

93 case SPIRV::OpMemberDecorate:

94 case SPIRV::OpMemberDecorateString:

95 return true;

96 default:

97 return false;

98 }

99}

100

102 switch (MI.getOpcode()) {

103 case SPIRV::OpAliasDomainDeclINTEL:

104 case SPIRV::OpAliasScopeDeclINTEL:

105 case SPIRV::OpAliasScopeListDeclINTEL:

106 return true;

107 default:

108 return false;

109 }

110}

111

113 switch (MI.getOpcode()) {

114 case SPIRV::OpCapability:

115 case SPIRV::OpExtension:

116 case SPIRV::OpExtInstImport:

117 case SPIRV::OpMemoryModel:

118 case SPIRV::OpEntryPoint:

119 case SPIRV::OpExecutionMode:

120 case SPIRV::OpExecutionModeId:

121 case SPIRV::OpString:

122 case SPIRV::OpSourceExtension:

123 case SPIRV::OpSource:

124 case SPIRV::OpSourceContinued:

125 case SPIRV::OpName:

126 case SPIRV::OpMemberName:

127 case SPIRV::OpModuleProcessed:

128 return true;

129 default:

132 }

133}

134

136 bool KHRFloatControls2) const {

137 switch (MI.getOpcode()) {

138 case SPIRV::OpFAddS:

139 case SPIRV::OpFSubS:

140 case SPIRV::OpFMulS:

141 case SPIRV::OpFDivS:

142 case SPIRV::OpFRemS:

143 case SPIRV::OpFAddV:

144 case SPIRV::OpFSubV:

145 case SPIRV::OpFMulV:

146 case SPIRV::OpFDivV:

147 case SPIRV::OpFRemV:

148 case SPIRV::OpFMod:

149 return true;

150 case SPIRV::OpFNegateV:

151 case SPIRV::OpFNegate:

152 case SPIRV::OpOrdered:

153 case SPIRV::OpUnordered:

154 case SPIRV::OpFOrdEqual:

155 case SPIRV::OpFOrdNotEqual:

156 case SPIRV::OpFOrdLessThan:

157 case SPIRV::OpFOrdLessThanEqual:

158 case SPIRV::OpFOrdGreaterThan:

159 case SPIRV::OpFOrdGreaterThanEqual:

160 case SPIRV::OpFUnordEqual:

161 case SPIRV::OpFUnordNotEqual:

162 case SPIRV::OpFUnordLessThan:

163 case SPIRV::OpFUnordLessThanEqual:

164 case SPIRV::OpFUnordGreaterThan:

165 case SPIRV::OpFUnordGreaterThanEqual:

166 case SPIRV::OpExtInst:

167 return KHRFloatControls2 ? true : false;

168 default:

169 return false;

170 }

171}

172

174 switch (MI.getOpcode()) {

175 case SPIRV::OpIAddS:

176 case SPIRV::OpIAddV:

177 case SPIRV::OpISubS:

178 case SPIRV::OpISubV:

179 case SPIRV::OpIMulS:

180 case SPIRV::OpIMulV:

181 case SPIRV::OpShiftLeftLogicalS:

182 case SPIRV::OpShiftLeftLogicalV:

183 case SPIRV::OpSNegate:

184 return true;

185 default:

186 return false;

187 }

188}

189

191 switch (MI.getOpcode()) {

192 case SPIRV::OpIAddS:

193 case SPIRV::OpIAddV:

194 case SPIRV::OpISubS:

195 case SPIRV::OpISubV:

196 case SPIRV::OpIMulS:

197 case SPIRV::OpIMulV:

198 return true;

199 default:

200 return false;

201 }

202}

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235 bool AllowModify) const {

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246 return true;

247}

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255 int * ) const {

257 if (I == MBB.end())

258 return 0;

259

260 if (I->getOpcode() == SPIRV::OpBranch) {

261 I->eraseFromParent();

262 return 1;

263 }

264 return 0;

265}

266

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285 int * ) const {

286 if ( TBB )

287 return 0;

289 return 1;

290}

291

295 Register SrcReg, bool KillSrc,

296 bool RenamableDest, bool RenamableSrc) const {

297

298

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300

301 assert(I->isCopy() && "Copy instruction is expected");

302 auto DstOp = I->getOperand(0);

303 auto SrcOp = I->getOperand(1);

305 "Register operands are expected in COPY");

306 auto &MRI = I->getMF()->getRegInfo();

308}

unsigned const MachineRegisterInfo * MRI

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL

This file declares the MachineIRBuilder class.

const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB

const SmallVectorImpl< MachineOperand > & Cond

This file defines the SmallVector class.

ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...

MachineInstrBundleIterator< MachineInstr > iterator

const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const

Representation of each machine instruction.

Wrapper class representing virtual and physical registers.

bool isConstantInstr(const MachineInstr &MI) const

Definition SPIRVInstrInfo.cpp:29

bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override

Definition SPIRVInstrInfo.cpp:231

bool isInlineAsmDefInstr(const MachineInstr &MI) const

Definition SPIRVInstrInfo.cpp:67

SPIRVInstrInfo(const SPIRVSubtarget &STI)

Definition SPIRVInstrInfo.cpp:26

bool isTypeDeclInstr(const MachineInstr &MI) const

Definition SPIRVInstrInfo.cpp:77

bool isDecorationInstr(const MachineInstr &MI) const

Definition SPIRVInstrInfo.cpp:88

unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

Definition SPIRVInstrInfo.cpp:254

bool isAliasingInstr(const MachineInstr &MI) const

Definition SPIRVInstrInfo.cpp:101

void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override

Definition SPIRVInstrInfo.cpp:292

bool canUseFastMathFlags(const MachineInstr &MI, bool KHRFloatControls2) const

Definition SPIRVInstrInfo.cpp:135

bool isHeaderInstr(const MachineInstr &MI) const

Definition SPIRVInstrInfo.cpp:112

bool canUseNUW(const MachineInstr &MI) const

Definition SPIRVInstrInfo.cpp:190

bool isSpecConstantInstr(const MachineInstr &MI) const

Definition SPIRVInstrInfo.cpp:53

bool canUseNSW(const MachineInstr &MI) const

Definition SPIRVInstrInfo.cpp:173

unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

Definition SPIRVInstrInfo.cpp:280

This class consists of common code factored out of the SmallVector class to reduce code duplication b...

This is an optimization pass for GlobalISel generic memory operations.

MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)

Builder interface. Specify how to create the initial instruction itself.

decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)