LLVM: lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp Source File (original) (raw)
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21using namespace llvm;
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23#define DEBUG_TYPE "spirv-mccodeemitter"
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25namespace {
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29
30public:
31 SPIRVMCCodeEmitter(const MCInstrInfo &mcii) : MCII(mcii) {}
32 SPIRVMCCodeEmitter(const SPIRVMCCodeEmitter &) = delete;
33 void operator=(const SPIRVMCCodeEmitter &) = delete;
34 ~SPIRVMCCodeEmitter() override = default;
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48};
49
50}
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54 return new SPIRVMCCodeEmitter(MCII);
55}
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67 return MCDesc.operands()[0].RegClass >= 0 &&
68 MCDesc.operands()[1].RegClass >= 0 &&
69 MCDesc.operands()[0].RegClass != SPIRV::TYPERegClassID &&
70 MCDesc.operands()[1].RegClass == SPIRV::TYPERegClassID;
71 }
72 return false;
73}
74
76 if (Op.isReg()) {
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81 } else if (Op.isImm()) {
84 } else {
86 }
87}
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93 unsigned NumOps = MI.getNumOperands();
96 for (unsigned i = 2; i < NumOps; ++i)
98}
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105}
106
107void SPIRVMCCodeEmitter::encodeUnknownType(const MCInst &MI,
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112 const uint64_t OpCode = MI.getOperand(1).getImm();
113 const uint32_t NumWords = MI.getNumOperands();
114 const uint32_t FirstWord = (0xFFFF & NumWords) << 16 | (0xFFFF & OpCode);
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120 for (unsigned i = 2; i < NumWords; ++i)
122}
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124void SPIRVMCCodeEmitter::encodeInstruction(const MCInst &MI,
125 SmallVectorImpl &CB,
126 SmallVectorImpl &Fixups,
127 const MCSubtargetInfo &STI) const {
128 if (MI.getOpcode() == SPIRV::UNKNOWN_type) {
129 encodeUnknownType(MI, CB, Fixups, STI);
130 return;
131 }
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134 const uint64_t OpCode = getBinaryCodeForInstr(MI, Fixups, STI);
135 const uint32_t NumWords = MI.getNumOperands() + 1;
136 const uint32_t FirstWord = (NumWords << 16) | OpCode;
138
139
142 else
144}
145
146#include "SPIRVGenMCCodeEmitter.inc"
const size_t AbstractManglingParser< Derived, Alloc >::NumOps
static void emitUntypedInstrOperands(const MCInst &MI, SmallVectorImpl< char > &CB)
Definition SPIRVMCCodeEmitter.cpp:101
static void emitOperand(const MCOperand &Op, SmallVectorImpl< char > &CB)
Definition SPIRVMCCodeEmitter.cpp:75
static void emitTypedInstrOperands(const MCInst &MI, SmallVectorImpl< char > &CB)
Definition SPIRVMCCodeEmitter.cpp:91
static bool hasType(const MCInst &MI, const MCInstrInfo &MII)
Definition SPIRVMCCodeEmitter.cpp:62
support::endian::Writer EndianWriter
Definition SPIRVMCCodeEmitter.cpp:57
MCCodeEmitter - Generic instruction encoding interface.
Context object for machine code objects.
Instances of this class represent a single low-level machine instruction.
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Instances of this class represent operands of the MCInst class.
Generic base class for all target subtargets.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getIDFromRegister(unsigned Reg)
void write(void *memory, value_type value, endianness endian)
Write a value to memory with a particular endianness.
This is an optimization pass for GlobalISel generic memory operations.
MCCodeEmitter * createSPIRVMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition SPIRVMCCodeEmitter.cpp:52
DWARFExpression::Operation Op
Adapter to write values to a stream in a particular byte order.