ScheduleDAGInstrs.h Source File (original) (raw)

14#ifndef LLVM_CODEGEN_SCHEDULEDAGINSTRS_H

15#define LLVM_CODEGEN_SCHEDULEDAGINSTRS_H

29#include

30#include

31#include

32#include

33#include

34#include

36namespace llvm {

62 return VirtReg.virtRegIndex();

63 }

64 };

86 return static_cast<unsigned>(RegUnit);

87 }

88 };

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179 mutable std::optional AAForDep;

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194 using SUList = std::list<SUnit *>;

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217 return nullptr;

218 }

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224 void reduceHugeMemNodeMaps(Value2SUsMap &stores,

225 Value2SUsMap &loads, unsigned N);

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229 void addChainDependency(SUnit *SUa, SUnit *SUb,

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234 for (SUnit *Entry : SUs)

236 }

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239 void addChainDependencies(SUnit *SU, Value2SUsMap &Val2SUsMap);

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242 void addChainDependencies(SUnit *SU, Value2SUsMap &Val2SUsMap,

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250 void addBarrierChain(Value2SUsMap &map);

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256 void insertBarrierChain(Value2SUsMap &map);

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267 std::vector<std::pair<MachineInstr *, MachineInstr *>>;

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296 return Topo.IsReachable(SU, TargetSU);

297 }

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334 unsigned regioninstrs);

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337 virtual void exitRegion();

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347 bool TrackLaneMasks = false);

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356 void addSchedBarrierDeps();

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368 void dumpNode(const SUnit &SU) const override;

369 void dump() const override;

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372 std::string getGraphNodeLabel(const SUnit *SU) const override;

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375 std::string getDAGName() const override;

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382 bool canAddEdge(SUnit *SuccSU, SUnit *PredSU);

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399 protected:

400 void initSUnits();

401 void addPhysRegDataDeps(SUnit *SU, unsigned OperIdx);

402 void addPhysRegDeps(SUnit *SU, unsigned OperIdx);

403 void addVRegDefDeps(SUnit *SU, unsigned OperIdx);

404 void addVRegUseDeps(SUnit *SU, unsigned OperIdx);

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412 };

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416#ifndef NDEBUG

418#endif

420 assert((Addr == nullptr || Addr == &SUnits[0]) &&

421 "SUnits std::vector reallocated on the fly!");

422 return &SUnits.back();

423 }

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430}

431

432#endif

assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")

static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")

This file defines the DenseMap class.

hexagon widen Hexagon Store false hexagon widen loads

A common definition of LaneBitmask for use in TableGen and CodeGen.

static void addEdge(SmallVectorImpl< LazyCallGraph::Edge > &Edges, DenseMap< LazyCallGraph::Node *, int > &EdgeIndexMap, LazyCallGraph::Node &N, LazyCallGraph::Edge::Kind EK)

This file defines the PointerIntPair class.

This file defines the SmallVector class.

This file defines the SparseMultiSet class, which adds multiset behavior to the SparseSet.

This class is a wrapper over an AAResults, and it is intended to be used only when there are no IR ch...

A set of register units used to track register liveness.

MachineInstrBundleIterator< MachineInstr > iterator

The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.

Representation of each machine instruction.

MachineOperand class - Representation of each machine instruction operand.

constexpr PointerIntPair()=default

ValueType getPointer() const

A discriminated union of two or more pointer types, with the discriminator in the low bit of the poin...

Special value supplied for machine level alias analysis.

Track the current register pressure at some position in the instruction stream, and remember the high...

Wrapper class representing virtual and physical registers.

Scheduling unit. This is a node in the scheduling DAG.

const MCSchedClassDesc * SchedClass

nullptr or resolved SchedClass.

MachineInstr * getInstr() const

Returns the representative MachineInstr for this SUnit.

LiveRegUnits LiveRegs

Set of live physical registers for updating kill flags.

Definition ScheduleDAGInstrs.h:275

DenseMap< MachineInstr *, SUnit * > MISUnitMap

After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to...

Definition ScheduleDAGInstrs.h:160

SmallVector< ClusterInfo > & getClusters()

Returns the array of the clusters.

Definition ScheduleDAGInstrs.h:392

MachineBasicBlock::iterator end() const

Returns an iterator to the bottom of the current scheduling region.

Definition ScheduleDAGInstrs.h:308

MachineBasicBlock * BB

The block in which to insert instructions.

Definition ScheduleDAGInstrs.h:147

MachineInstr * FirstDbgValue

Definition ScheduleDAGInstrs.h:272

bool CanHandleTerminators

The standard DAG builder does not normally include terminators as DAG nodes because it does not creat...

Definition ScheduleDAGInstrs.h:138

bool ScheduleSingleMIRegions

True if regions with a single MI should be scheduled.

Definition ScheduleDAGInstrs.h:131

const TargetSchedModel * getSchedModel() const

Gets the machine model for instruction scheduling.

Definition ScheduleDAGInstrs.h:285

MachineBasicBlock::iterator RegionEnd

The end of the range to be scheduled.

Definition ScheduleDAGInstrs.h:153

VReg2SUnitOperIdxMultiMap CurrentVRegUses

Tracks the last instructions in this region using each virtual register.

Definition ScheduleDAGInstrs.h:177

void addChainDependencies(SUnit *SU, SUList &SUs, unsigned Latency)

Adds dependencies as needed from all SUs in list to SU.

Definition ScheduleDAGInstrs.h:233

const MCSchedClassDesc * getSchedClass(SUnit *SU) const

Resolves and cache a resolved scheduling class for an SUnit.

Definition ScheduleDAGInstrs.h:288

~ScheduleDAGInstrs() override=default

ScheduleDAGInstrs(MachineFunction &mf, const MachineLoopInfo *mli, bool RemoveKillFlags=false)

bool shouldScheduleSingleMIRegions() const

Whether regions with a single MI should be scheduled.

Definition ScheduleDAGInstrs.h:300

DbgValueVector DbgValues

Remember instruction that precedes DBG_VALUE.

Definition ScheduleDAGInstrs.h:271

std::vector< std::pair< MachineInstr *, MachineInstr * > > DbgValueVector

Definition ScheduleDAGInstrs.h:266

SUnit * newSUnit(MachineInstr *MI)

Creates a new SUnit and return a ptr to it.

Definition ScheduleDAGInstrs.h:415

virtual void finalizeSchedule()

Allow targets to perform final scheduling actions at the level of the whole MachineFunction.

Definition ScheduleDAGInstrs.h:366

ScheduleDAGTopologicalSort Topo

Topo - A topological ordering for SUnits which permits fast IsReachable and similar queries.

Definition ScheduleDAGInstrs.h:264

DumpDirection

The direction that should be used to dump the scheduled Sequence.

Definition ScheduleDAGInstrs.h:197

@ BottomUp

Definition ScheduleDAGInstrs.h:199

@ TopDown

Definition ScheduleDAGInstrs.h:198

@ NotSet

Definition ScheduleDAGInstrs.h:201

@ Bidirectional

Definition ScheduleDAGInstrs.h:200

std::list< SUnit * > SUList

A list of SUnits, used in Value2SUsMap, during DAG construction.

Definition ScheduleDAGInstrs.h:194

SUnit * BarrierChain

Remember a generic side-effecting instruction as we proceed.

Definition ScheduleDAGInstrs.h:184

BatchAAResults * getAAForDep() const

Returns a (possibly null) pointer to the current BatchAAResults.

Definition ScheduleDAGInstrs.h:214

bool TrackLaneMasks

Whether lane masks should get tracked.

Definition ScheduleDAGInstrs.h:141

ClusterInfo * getCluster(unsigned Idx)

Get the specific cluster, return nullptr for InvalidClusterId.

Definition ScheduleDAGInstrs.h:395

bool IsReachable(SUnit *SU, SUnit *TargetSU)

IsReachable - Checks if SU is reachable from TargetSU.

Definition ScheduleDAGInstrs.h:295

RegUnit2SUnitsMap Defs

Defs, Uses - Remember where defs and uses of each register are as we iterate upward through the instr...

Definition ScheduleDAGInstrs.h:169

UndefValue * UnknownValue

For an unanalyzable memory access, this Value is used in maps.

Definition ScheduleDAGInstrs.h:259

VReg2SUnitMultiMap CurrentVRegDefs

Tracks the last instruction(s) in this region defining each virtual register.

Definition ScheduleDAGInstrs.h:175

DumpDirection DumpDir

Definition ScheduleDAGInstrs.h:207

MachineBasicBlock::iterator begin() const

Returns an iterator to the top of the current scheduling region.

Definition ScheduleDAGInstrs.h:305

SUnit * getSUnit(MachineInstr *MI) const

Returns an existing SUnit for this MI, or nullptr.

Definition ScheduleDAGInstrs.h:426

TargetSchedModel SchedModel

TargetSchedModel provides an interface to the machine model.

Definition ScheduleDAGInstrs.h:124

RegUnit2SUnitsMap Uses

Definition ScheduleDAGInstrs.h:170

virtual void schedule()=0

Orders nodes according to selected style.

const MachineLoopInfo * MLI

Definition ScheduleDAGInstrs.h:120

bool RemoveKillFlags

True if the DAG builder should remove kill flags (in preparation for rescheduling).

Definition ScheduleDAGInstrs.h:128

std::optional< BatchAAResults > AAForDep

Definition ScheduleDAGInstrs.h:179

MachineBasicBlock::iterator RegionBegin

The beginning of the range to be scheduled.

Definition ScheduleDAGInstrs.h:150

void addChainDependency(SUnit *SUa, SUnit *SUb, unsigned Latency=0)

Adds a chain edge between SUa and SUb, but only if both AAResults and Target fail to deny the depende...

unsigned NumRegionInstrs

Instructions in this region (distance(RegionBegin, RegionEnd)).

Definition ScheduleDAGInstrs.h:156

const MachineFrameInfo & MFI

Definition ScheduleDAGInstrs.h:121

SmallVector< ClusterInfo > Clusters

Definition ScheduleDAGInstrs.h:186

virtual bool doMBBSchedRegionsTopDown() const

If this method returns true, handling of the scheduling regions themselves (in case of a scheduling b...

Definition ScheduleDAGInstrs.h:319

void setDumpDirection(DumpDirection D)

Definition ScheduleDAGInstrs.h:204

This class can compute a topological ordering for SUnits and provides methods for dynamically updatin...

std::vector< SUnit > SUnits

The scheduling units.

ScheduleDAG(const ScheduleDAG &)=delete

This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.

Fast multiset implementation for objects that can be identified by small unsigned keys.

Provide an instruction scheduling machine model to CodeGen passes.

'undef' values are things that do not have specified contents.

LLVM Value Representation.

Abstract Attribute helper functions.

This is an optimization pass for GlobalISel generic memory operations.

SparseMultiSet< VReg2SUnitOperIdx, Register, VirtReg2IndexFunctor > VReg2SUnitOperIdxMultiMap

Definition ScheduleDAGInstrs.h:102

void dump(const SparseBitVector< ElementSize > &LHS, raw_ostream &out)

SparseMultiSet< VReg2SUnit, Register, VirtReg2IndexFunctor > VReg2SUnitMultiMap

Track local uses of virtual registers.

Definition ScheduleDAGInstrs.h:99

constexpr unsigned InvalidClusterId

SmallVector< UnderlyingObject, 4 > UnderlyingObjectsVector

Definition ScheduleDAGInstrs.h:115

SmallPtrSet< SUnit *, 8 > ClusterInfo

Keep record of which SUnit are in the same cluster group.

PointerUnion< const Value *, const PseudoSourceValue * > ValueType

Definition ScheduleDAGInstrs.h:105

SparseMultiSet< PhysRegSUOper, MCRegUnit, MCRegUnitToIndex, uint16_t > RegUnit2SUnitsMap

Use a SparseMultiSet to track physical registers.

Definition ScheduleDAGInstrs.h:93

Summarize the scheduling resources required for an instruction of a particular scheduling class.

int OpIdx

Definition ScheduleDAGInstrs.h:79

SUnit * SU

Definition ScheduleDAGInstrs.h:78

MCRegUnit RegUnit

Definition ScheduleDAGInstrs.h:80

unsigned getSparseSetIndex() const

Definition ScheduleDAGInstrs.h:85

PhysRegSUOper(SUnit *su, int op, MCRegUnit R)

Definition ScheduleDAGInstrs.h:82

bool mayAlias() const

Definition ScheduleDAGInstrs.h:112

UnderlyingObject(ValueType V, bool MayAlias)

Definition ScheduleDAGInstrs.h:108

ValueType getValue() const

Definition ScheduleDAGInstrs.h:111

VReg2SUnitOperIdx(Register VReg, LaneBitmask LaneMask, unsigned OperandIndex, SUnit *SU)

Definition ScheduleDAGInstrs.h:70

unsigned OperandIndex

Definition ScheduleDAGInstrs.h:68

LaneBitmask LaneMask

Definition ScheduleDAGInstrs.h:55

VReg2SUnit(Register VReg, LaneBitmask LaneMask, SUnit *SU)

Definition ScheduleDAGInstrs.h:58

SUnit * SU

Definition ScheduleDAGInstrs.h:56

unsigned getSparseSetIndex() const

Definition ScheduleDAGInstrs.h:61

Definition ScheduleDAGInstrs.h:54