LLVM: llvm::ScheduleDAGInstrs Class Reference (original) (raw)

A ScheduleDAG for scheduling lists of MachineInstr. More...

#include "[llvm/CodeGen/ScheduleDAGInstrs.h](ScheduleDAGInstrs%5F8h%5Fsource.html)"

Public Types
enum DumpDirection { TopDown, BottomUp, Bidirectional, NotSet }
The direction that should be used to dump the scheduled Sequence. More...
using SUList = std::list<SUnit *>
A list of SUnits, used in Value2SUsMap, during DAG construction.
Public Member Functions
void setDumpDirection (DumpDirection D)
ScheduleDAGInstrs (MachineFunction &mf, const MachineLoopInfo *mli, bool RemoveKillFlags=false)
~ScheduleDAGInstrs () override=default
const TargetSchedModel * getSchedModel () const
Gets the machine model for instruction scheduling.
const MCSchedClassDesc * getSchedClass (SUnit *SU) const
Resolves and cache a resolved scheduling class for an SUnit.
bool IsReachable (SUnit *SU, SUnit *TargetSU)
IsReachable - Checks if SU is reachable from TargetSU.
bool shouldScheduleSingleMIRegions () const
Whether regions with a single MI should be scheduled.
MachineBasicBlock::iterator begin () const
Returns an iterator to the top of the current scheduling region.
MachineBasicBlock::iterator end () const
Returns an iterator to the bottom of the current scheduling region.
SUnit * newSUnit (MachineInstr *MI)
Creates a new SUnit and return a ptr to it.
SUnit * getSUnit (MachineInstr *MI) const
Returns an existing SUnit for this MI, or nullptr.
virtual bool doMBBSchedRegionsTopDown () const
If this method returns true, handling of the scheduling regions themselves (in case of a scheduling boundary in MBB) will be done beginning with the topmost region of MBB.
virtual void startBlock (MachineBasicBlock *BB)
Prepares to perform scheduling in the given block.
virtual void finishBlock ()
Cleans up after scheduling in the given block.
virtual void enterRegion (MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs)
Initialize the DAG and common scheduler state for a new scheduling region.
virtual void exitRegion ()
Called when the scheduler has finished scheduling the current region.
void buildSchedGraph (AAResults *AA, RegPressureTracker *RPTracker=nullptr, PressureDiffs *PDiffs=nullptr, LiveIntervals *LIS=nullptr, bool TrackLaneMasks=false)
Builds SUnits for the current region.
void addSchedBarrierDeps ()
Adds dependencies from instructions in the current list of instructions being scheduled to scheduling barrier.
virtual void schedule ()=0
Orders nodes according to selected style.
virtual void finalizeSchedule ()
Allow targets to perform final scheduling actions at the level of the whole MachineFunction.
void dumpNode (const SUnit &SU) const override
void dump () const override
std::string getGraphNodeLabel (const SUnit *SU) const override
Returns a label for a DAG node that points to an instruction.
std::string getDAGName () const override
Returns a label for the region of code covered by the DAG.
void fixupKills (MachineBasicBlock &MBB)
Fixes register kill flags that scheduling has made invalid.
bool canAddEdge (SUnit *SuccSU, SUnit *PredSU)
True if an edge can be added from PredSU to SuccSU without creating a cycle.
bool addEdge (SUnit *SuccSU, const SDep &PredDep)
Add a DAG edge to the given SU with the given predecessor dependence data.
SmallVector< ClusterInfo > & getClusters ()
Returns the array of the clusters.
ClusterInfo * getCluster (unsigned Idx)
Get the specific cluster, return nullptr for InvalidClusterId.
Public Member Functions inherited from llvm::ScheduleDAG
ScheduleDAG (const ScheduleDAG &)=delete
ScheduleDAG & operator= (const ScheduleDAG &)=delete
ScheduleDAG (MachineFunction &mf)
virtual ~ScheduleDAG ()
void clearDAG ()
Clears the DAG state (between regions).
const MCInstrDesc * getInstrDesc (const SUnit *SU) const
Returns the MCInstrDesc of this SUnit.
virtual void viewGraph (const Twine &Name, const Twine &Title)
Pops up a GraphViz/gv window with the ScheduleDAG rendered using 'dot'.
virtual void viewGraph ()
Out-of-line implementation with no arguments is handy for gdb.
void dumpNodeName (const SUnit &SU) const
virtual void addCustomGraphFeatures (GraphWriter< ScheduleDAG * > &) const
Adds custom features for a visualization of the ScheduleDAG.
unsigned VerifyScheduledDAG (bool isBottomUp)
Verifies that all SUnits were scheduled and that their state is consistent.
Protected Types
using DbgValueVector
Protected Member Functions
BatchAAResults * getAAForDep () const
Returns a (possibly null) pointer to the current BatchAAResults.
void reduceHugeMemNodeMaps (Value2SUsMap &stores, Value2SUsMap &loads, unsigned N)
Reduces maps in FIFO order, by N SUs.
void addChainDependency (SUnit *SUa, SUnit *SUb, unsigned Latency=0)
Adds a chain edge between SUa and SUb, but only if both AAResults and Target fail to deny the dependency.
void addChainDependencies (SUnit *SU, SUList &SUs, unsigned Latency)
Adds dependencies as needed from all SUs in list to SU.
void addChainDependencies (SUnit *SU, Value2SUsMap &Val2SUsMap)
Adds dependencies as needed from all SUs in map, to SU.
void addChainDependencies (SUnit *SU, Value2SUsMap &Val2SUsMap, ValueType V)
Adds dependencies as needed to SU, from all SUs mapped to V.
void addBarrierChain (Value2SUsMap &map)
Adds barrier chain edges from all SUs in map, and then clear the map.
void insertBarrierChain (Value2SUsMap &map)
Inserts a barrier chain in a huge region, far below current SU.
void initSUnits ()
Creates an SUnit for each real instruction, numbered in top-down topological order.
void addPhysRegDataDeps (SUnit *SU, unsigned OperIdx)
MO is an operand of SU's instruction that defines a physical register.
void addPhysRegDeps (SUnit *SU, unsigned OperIdx)
Adds register dependencies (data, anti, and output) from this SUnit to following instructions in the same scheduling region that depend the physical register referenced at OperIdx.
void addVRegDefDeps (SUnit *SU, unsigned OperIdx)
Adds register output and data dependencies from this SUnit to instructions that occur later in the same scheduling region if they read from or write to the virtual register defined at OperIdx.
void addVRegUseDeps (SUnit *SU, unsigned OperIdx)
Adds a register data dependency if the instruction that defines the virtual register used at OperIdx is mapped to an SUnit.
LaneBitmask getLaneMaskForMO (const MachineOperand &MO) const
Returns a mask for which lanes get read/written by the given (register) machine operand.
bool deadDefHasNoUse (const MachineOperand &MO)
Returns true if the def register in MO has no uses.
Protected Member Functions inherited from llvm::ScheduleDAG
void dumpNodeAll (const SUnit &SU) const
Protected Attributes
const MachineLoopInfo * MLI = nullptr
const MachineFrameInfo & MFI
TargetSchedModel SchedModel
TargetSchedModel provides an interface to the machine model.
bool RemoveKillFlags
True if the DAG builder should remove kill flags (in preparation for rescheduling).
bool ScheduleSingleMIRegions = false
True if regions with a single MI should be scheduled.
bool CanHandleTerminators = false
The standard DAG builder does not normally include terminators as DAG nodes because it does not create the necessary dependencies to prevent reordering.
bool TrackLaneMasks = false
Whether lane masks should get tracked.
MachineBasicBlock * BB = nullptr
The block in which to insert instructions.
MachineBasicBlock::iterator RegionBegin
The beginning of the range to be scheduled.
MachineBasicBlock::iterator RegionEnd
The end of the range to be scheduled.
unsigned NumRegionInstrs = 0
Instructions in this region (distance(RegionBegin, RegionEnd)).
DenseMap< MachineInstr *, SUnit * > MISUnitMap
After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to an SUnit.
RegUnit2SUnitsMap Defs
Defs, Uses - Remember where defs and uses of each register are as we iterate upward through the instructions.
RegUnit2SUnitsMap Uses
VReg2SUnitMultiMap CurrentVRegDefs
Tracks the last instruction(s) in this region defining each virtual register.
VReg2SUnitOperIdxMultiMap CurrentVRegUses
Tracks the last instructions in this region using each virtual register.
std::optional< BatchAAResults > AAForDep
SUnit * BarrierChain = nullptr
Remember a generic side-effecting instruction as we proceed.
SmallVector< ClusterInfo > Clusters
DumpDirection DumpDir = NotSet
UndefValue * UnknownValue
For an unanalyzable memory access, this Value is used in maps.
ScheduleDAGTopologicalSort Topo
Topo - A topological ordering for SUnits which permits fast IsReachable and similar queries.
DbgValueVector DbgValues
Remember instruction that precedes DBG_VALUE.
MachineInstr * FirstDbgValue = nullptr
LiveRegUnits LiveRegs
Set of live physical registers for updating kill flags.
Additional Inherited Members
Public Attributes inherited from llvm::ScheduleDAG
const TargetMachine & TM
Target processor.
const TargetInstrInfo * TII
Target instruction information.
const TargetRegisterInfo * TRI
Target processor register info.
MachineFunction & MF
Machine function.
MachineRegisterInfo & MRI
Virtual/real register map.
std::vector< SUnit > SUnits
The scheduling units.
SUnit EntrySU
Special node for the region entry.
SUnit ExitSU
Special node for the region exit.
bool StressSched

A ScheduleDAG for scheduling lists of MachineInstr.

Definition at line 118 of file ScheduleDAGInstrs.h.

◆ DbgValueVector

Initial value:

std::vector<std::pair<MachineInstr *, MachineInstr *>>

Definition at line 266 of file ScheduleDAGInstrs.h.

◆ SUList

A list of SUnits, used in Value2SUsMap, during DAG construction.

Note: to gain speed it might be worth investigating an optimized implementation of this data structure, such as a singly linked list with a memory pool (SmallVector was tried but slow and SparseSet is not applicable).

Definition at line 194 of file ScheduleDAGInstrs.h.

◆ DumpDirection

The direction that should be used to dump the scheduled Sequence.

Enumerator
TopDown
BottomUp
Bidirectional
NotSet

Definition at line 197 of file ScheduleDAGInstrs.h.

Definition at line 122 of file ScheduleDAGInstrs.cpp.

References DbgValues, EnableSchedItins, EnableSchedModel, llvm::ScheduleDAG::ExitSU, llvm::get(), getFunction(), llvm::MachineFunction::getSubtarget(), MFI, MLI, RemoveKillFlags, SchedModel, llvm::ScheduleDAG::ScheduleDAG(), llvm::ScheduleDAG::SUnits, Topo, and UnknownValue.

Referenced by llvm::SwingSchedulerDAG::classof(), llvm::DefaultVLIWScheduler::DefaultVLIWScheduler(), llvm::ScheduleDAGMI::ScheduleDAGMI(), and llvm::SwingSchedulerDAG::SwingSchedulerDAG().

◆ ~ScheduleDAGInstrs()

llvm::ScheduleDAGInstrs::~ScheduleDAGInstrs ( ) overridedefault

◆ addBarrierChain()

void ScheduleDAGInstrs::addBarrierChain ( Value2SUsMap & map) protected

◆ addChainDependencies() [1/3]

void llvm::ScheduleDAGInstrs::addChainDependencies ( SUnit * SU, SUList & SUs, unsigned Latency ) inlineprotected

◆ addChainDependencies() [2/3]

void ScheduleDAGInstrs::addChainDependencies ( SUnit * SU, Value2SUsMap & Val2SUsMap ) protected

◆ addChainDependencies() [3/3]

Adds dependencies as needed to SU, from all SUs mapped to V.

Definition at line 702 of file ScheduleDAGInstrs.cpp.

References addChainDependencies(), llvm::MapVector< KeyT, ValueT, MapType, VectorType >::end(), llvm::MapVector< KeyT, ValueT, MapType, VectorType >::find(), and llvm::ScheduleDAGInstrs::Value2SUsMap::getTrueMemOrderLatency().

◆ addChainDependency()

void ScheduleDAGInstrs::addChainDependency ( SUnit * SUa, SUnit * SUb, unsigned Latency = 0 ) protected

◆ addEdge()

◆ addPhysRegDataDeps()

void ScheduleDAGInstrs::addPhysRegDataDeps ( SUnit * SU, unsigned OperIdx ) protected

MO is an operand of SU's instruction that defines a physical register.

Adds data dependencies from SU to any uses of the physical register.

Definition at line 259 of file ScheduleDAGInstrs.cpp.

References llvm::SUnit::addPred(), llvm::SDep::Artificial, assert(), llvm::SDep::Data, llvm::MachineInstr::getDesc(), llvm::SUnit::getInstr(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MCInstrDesc::hasImplicitDefOfPhysReg(), llvm::MCInstrDesc::hasImplicitUseOfPhysReg(), llvm::SUnit::hasPhysRegDefs, I, llvm::MachineOperand::isDef(), llvm::ScheduleDAG::MF, SchedModel, llvm::SDep::setLatency(), llvm::ScheduleDAG::TRI, UseReg(), and Uses.

Referenced by addPhysRegDeps().

◆ addPhysRegDeps()

void ScheduleDAGInstrs::addPhysRegDeps ( SUnit * SU, unsigned OperIdx ) protected

Adds register dependencies (data, anti, and output) from this SUnit to following instructions in the same scheduling region that depend the physical register referenced at OperIdx.

Definition at line 315 of file ScheduleDAGInstrs.cpp.

References addPhysRegDataDeps(), llvm::SUnit::addPred(), llvm::SDep::Anti, B(), Defs, llvm::ScheduleDAG::ExitSU, llvm::SUnit::getInstr(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::SUnit::hasPhysRegUses, I, llvm::SUnit::isCall, llvm::MachineOperand::isDead(), llvm::MachineOperand::isUse(), llvm::ScheduleDAG::MF, MI, llvm::ScheduleDAG::MRI, llvm::SDep::Output, P, RemoveKillFlags, SchedModel, llvm::MachineOperand::setIsKill(), llvm::SDep::setLatency(), llvm::ScheduleDAG::TRI, and Uses.

Referenced by buildSchedGraph().

◆ addSchedBarrierDeps()

void ScheduleDAGInstrs::addSchedBarrierDeps ( )

Adds dependencies from instructions in the current list of instructions being scheduled to scheduling barrier.

We want to make sure instructions which define registers that are either used by the terminator or are live-out are properly scheduled. This is especially important when the definition latency of the return value(s) are too high to be hidden by the branch or when the liveout registers used by instructions in the fallthrough block.

Definition at line 212 of file ScheduleDAGInstrs.cpp.

References addVRegUseDeps(), llvm::MachineInstr::all_uses(), BB, llvm::ScheduleDAG::ExitSU, llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumOperands(), llvm::MCInstrDesc::hasImplicitUseOfPhysReg(), llvm::MachineInstr::isBarrier(), llvm::MachineInstr::isCall(), llvm::MCRegUnitMaskIterator::isValid(), OpIdx, RegionBegin, RegionEnd, llvm::skipDebugInstructionsBackward(), llvm::ScheduleDAG::TRI, and Uses.

Referenced by buildSchedGraph().

◆ addVRegDefDeps()

void ScheduleDAGInstrs::addVRegDefDeps ( SUnit * SU, unsigned OperIdx ) protected

Adds register output and data dependencies from this SUnit to instructions that occur later in the same scheduling region if they read from or write to the virtual register defined at OperIdx.

TODO: Hoist loop induction variable increments. This has to be reevaluated. Generally, IV scheduling should be done before coalescing.

Definition at line 425 of file ScheduleDAGInstrs.cpp.

References llvm::SUnit::addPred(), llvm::LaneBitmask::any(), assert(), CurrentVRegDefs, CurrentVRegUses, llvm::SDep::Data, deadDefHasNoUse(), llvm::drop_begin(), llvm::LaneBitmask::getAll(), llvm::SUnit::getInstr(), getLaneMaskForMO(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), I, llvm::MachineOperand::isDead(), llvm::MachineOperand::isUndef(), llvm::make_range(), llvm::ScheduleDAG::MF, MI, llvm::ScheduleDAG::MRI, none, llvm::SDep::Output, SchedModel, llvm::MachineOperand::setIsUndef(), llvm::SDep::setLatency(), and TrackLaneMasks.

Referenced by buildSchedGraph().

◆ addVRegUseDeps()

void ScheduleDAGInstrs::addVRegUseDeps ( SUnit * SU, unsigned OperIdx ) protected

Adds a register data dependency if the instruction that defines the virtual register used at OperIdx is mapped to an SUnit.

Add a register antidependency from this SUnit to instructions that occur later in the same scheduling region if they write the virtual register.

TODO: Handle ExitSU "uses" properly.

Definition at line 545 of file ScheduleDAGInstrs.cpp.

References llvm::SDep::Anti, assert(), CurrentVRegDefs, CurrentVRegUses, llvm::LaneBitmask::getAll(), llvm::SUnit::getInstr(), getLaneMaskForMO(), llvm::MachineOperand::getReg(), llvm::make_range(), MI, none, and TrackLaneMasks.

Referenced by addSchedBarrierDeps(), and buildSchedGraph().

◆ begin()

◆ buildSchedGraph()

Builds SUnits for the current region.

If RPTracker is non-null, compute register pressure as a side effect. The DAG builder is an efficient place to do it because it already visits operands.

Definition at line 755 of file ScheduleDAGInstrs.cpp.

References AAForDep, addBarrierChain(), addChainDependencies(), llvm::PressureDiffs::addInstruction(), addPhysRegDeps(), addSchedBarrierDeps(), addVRegDefDeps(), addVRegUseDeps(), llvm::RegisterOperands::adjustLaneLiveness(), llvm::SDep::Artificial, assert(), BarrierChain, CanHandleTerminators, llvm::ScheduleDAG::clearDAG(), llvm::RegisterOperands::collect(), CurrentVRegDefs, CurrentVRegUses, llvm::dbgs(), DbgValues, Defs, EnableAASchedMI, llvm::ScheduleDAG::ExitSU, FirstDbgValue, llvm::LiveIntervals::getInstructionIndex(), llvm::RegPressureTracker::getPos(), getReductionSize(), llvm::MachineOperand::getReg(), getUnderlyingObjectsForInstr(), HugeRegion, llvm::PressureDiffs::init(), initSUnits(), llvm::ScheduleDAGInstrs::Value2SUsMap::insert(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUse(), llvm::SUnit::Latency, LLVM_DEBUG, llvm::ScheduleDAG::MF, MFI, MI, MISUnitMap, llvm::ScheduleDAG::MRI, llvm::SUnit::NodeNum, llvm::SUnit::NumSuccs, llvm::MachineOperand::readsReg(), llvm::RegPressureTracker::recede(), llvm::RegPressureTracker::recedeSkipDebugValues(), reduceHugeMemNodeMaps(), RegionBegin, RegionEnd, llvm::SDep::setLatency(), llvm::ScheduleDAGInstrs::Value2SUsMap::size(), llvm::ScheduleDAG::SUnits, llvm::ScheduleDAG::TII, Topo, TrackLaneMasks, llvm::ScheduleDAG::TRI, UnknownValue, UseAA, and Uses.

Referenced by llvm::ScheduleDAGMILive::buildDAGWithRegPressure(), llvm::DefaultVLIWScheduler::schedule(), llvm::ScheduleDAGMI::schedule(), and llvm::SwingSchedulerDAG::schedule().

◆ canAddEdge()

◆ deadDefHasNoUse()

◆ doMBBSchedRegionsTopDown()

virtual bool llvm::ScheduleDAGInstrs::doMBBSchedRegionsTopDown ( ) const inlinevirtual

If this method returns true, handling of the scheduling regions themselves (in case of a scheduling boundary in MBB) will be done beginning with the topmost region of MBB.

Reimplemented in llvm::ScheduleDAGMI.

Definition at line 319 of file ScheduleDAGInstrs.h.

◆ dump()

void ScheduleDAGInstrs::dump ( ) const overridevirtual

◆ dumpNode()

void ScheduleDAGInstrs::dumpNode ( const SUnit & SU) const overridevirtual

◆ end()

◆ enterRegion()

◆ exitRegion()

void ScheduleDAGInstrs::exitRegion ( ) virtual

Called when the scheduler has finished scheduling the current region.

Definition at line 208 of file ScheduleDAGInstrs.cpp.

◆ finalizeSchedule()

virtual void llvm::ScheduleDAGInstrs::finalizeSchedule ( ) inlinevirtual

◆ finishBlock()

void ScheduleDAGInstrs::finishBlock ( ) virtual

◆ fixupKills()

Fixes register kill flags that scheduling has made invalid.

Definition at line 1144 of file ScheduleDAGInstrs.cpp.

References llvm::dbgs(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getRegMask(), I, llvm::MachineOperand::isDef(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), LiveRegs, LLVM_DEBUG, MBB, MI, llvm::ScheduleDAG::MRI, llvm::printMBBReference(), llvm::reverse(), toggleKills(), and llvm::ScheduleDAG::TRI.

◆ getAAForDep()

BatchAAResults * llvm::ScheduleDAGInstrs::getAAForDep ( ) const inlineprotected

◆ getCluster()

◆ getClusters()

◆ getDAGName()

std::string ScheduleDAGInstrs::getDAGName ( ) const overridevirtual

◆ getGraphNodeLabel()

std::string ScheduleDAGInstrs::getGraphNodeLabel ( const SUnit * SU) const overridevirtual

◆ getLaneMaskForMO()

◆ getSchedClass()

◆ getSchedModel()

◆ getSUnit()

◆ initSUnits()

void ScheduleDAGInstrs::initSUnits ( ) protected

Creates an SUnit for each real instruction, numbered in top-down topological order.

The instruction order A < B, implies that no edge exists from B to A.

Map each real instruction to its SUnit.

After initSUnits, the SUnits vector cannot be resized and the scheduler may hang onto SUnit pointers. We may relax this in the future by using SUnit IDs instead of pointers.

MachineScheduler relies on initSUnits numbering the nodes by their order in the original instruction list.

Definition at line 593 of file ScheduleDAGInstrs.cpp.

References llvm::SUnit::getInstr(), getSchedClass(), llvm::SUnit::hasReservedResource, llvm::SUnit::isCall, llvm::SUnit::isCommutable, llvm::SUnit::isUnbuffered, llvm::SUnit::Latency, llvm::make_range(), MI, MISUnitMap, newSUnit(), NumRegionInstrs, RegionBegin, RegionEnd, SchedModel, and llvm::ScheduleDAG::SUnits.

Referenced by buildSchedGraph().

◆ insertBarrierChain()

void ScheduleDAGInstrs::insertBarrierChain ( Value2SUsMap & map) protected

Inserts a barrier chain in a huge region, far below current SU.

Adds barrier chain edges from all SUs in map with higher NodeNums than this new BarrierChain, and remove them from map. It is assumed BarrierChain has been set before calling this.

Definition at line 722 of file ScheduleDAGInstrs.cpp.

References assert(), BarrierChain, llvm::MapVector< KeyT, ValueT, MapType, VectorType >::begin(), llvm::MapVector< KeyT, ValueT, MapType, VectorType >::end(), I, llvm::ScheduleDAGInstrs::Value2SUsMap::reComputeSize(), and llvm::MapVector< KeyT, ValueT, MapType, VectorType >::remove_if().

Referenced by reduceHugeMemNodeMaps().

◆ IsReachable()

bool llvm::ScheduleDAGInstrs::IsReachable ( SUnit * SU, SUnit * TargetSU ) inline

◆ newSUnit()

◆ reduceHugeMemNodeMaps()

Reduces maps in FIFO order, by N SUs.

This is better than turning every Nth memory SU into BarrierChain in buildSchedGraph(), since it avoids unnecessary edges between seen SUs above the new BarrierChain, and those below it.

Definition at line 1075 of file ScheduleDAGInstrs.cpp.

References assert(), BarrierChain, llvm::dbgs(), insertBarrierChain(), LLVM_DEBUG, loads, N, llvm::SUnit::NodeNum, llvm::sort(), stores, and llvm::ScheduleDAG::SUnits.

Referenced by buildSchedGraph().

◆ schedule()

virtual void llvm::ScheduleDAGInstrs::schedule ( ) pure virtual

◆ setDumpDirection()

void llvm::ScheduleDAGInstrs::setDumpDirection ( DumpDirection D) inline

◆ shouldScheduleSingleMIRegions()

bool llvm::ScheduleDAGInstrs::shouldScheduleSingleMIRegions ( ) const inline

◆ startBlock()

◆ AAForDep

◆ BarrierChain

SUnit* llvm::ScheduleDAGInstrs::BarrierChain = nullptr protected

◆ BB

The block in which to insert instructions.

Definition at line 147 of file ScheduleDAGInstrs.h.

Referenced by addSchedBarrierDeps(), llvm::GCNIterativeScheduler::BuildDAG::BuildDAG(), llvm::ScheduleDAGMILive::buildDAGWithRegPressure(), llvm::ScheduleDAGMILive::computeCyclicCriticalPath(), llvm::ScheduleDAGMI::dumpScheduleTraceBottomUp(), llvm::ScheduleDAGMI::dumpScheduleTraceTopDown(), llvm::GCNIterativeScheduler::enterRegion(), enterRegion(), finishBlock(), llvm::SIScheduleDAGMI::getBB(), llvm::VLIWMachineScheduler::getBBSize(), getDAGName(), llvm::ScheduleDAGMILive::initRegPressure(), llvm::SIScheduleDAGMI::initRPTracker(), llvm::SwingSchedulerDAG::mayOverlapInLaterIter(), llvm::ScheduleDAGMI::moveInstruction(), llvm::GCNIterativeScheduler::OverrideLegacyStrategy::OverrideLegacyStrategy(), llvm::ScheduleDAGMI::placeDebugValues(), llvm::VLIWMachineScheduler::schedule(), llvm::GCNIterativeScheduler::scheduleRegion(), startBlock(), and llvm::ScheduleDAGMILive::updatePressureDiffs().

◆ CanHandleTerminators

bool llvm::ScheduleDAGInstrs::CanHandleTerminators = false protected

◆ Clusters

◆ CurrentVRegDefs

◆ CurrentVRegUses

◆ DbgValues

DbgValueVector llvm::ScheduleDAGInstrs::DbgValues protected

◆ Defs

Defs, Uses - Remember where defs and uses of each register are as we iterate upward through the instructions.

This is allocated here instead of inside BuildSchedGraph to avoid the need for it to be initialized and destructed for each block.

Definition at line 169 of file ScheduleDAGInstrs.h.

Referenced by addPhysRegDeps(), and buildSchedGraph().

◆ DumpDir

DumpDirection llvm::ScheduleDAGInstrs::DumpDir = NotSet protected

◆ FirstDbgValue

MachineInstr* llvm::ScheduleDAGInstrs::FirstDbgValue = nullptr protected

◆ LiveRegs

◆ MFI

◆ MISUnitMap

◆ MLI

◆ NumRegionInstrs

unsigned llvm::ScheduleDAGInstrs::NumRegionInstrs = 0 protected

◆ RegionBegin

The beginning of the range to be scheduled.

Definition at line 150 of file ScheduleDAGInstrs.h.

Referenced by addSchedBarrierDeps(), begin(), buildSchedGraph(), enterRegion(), llvm::ScheduleDAGMI::initQueues(), llvm::ScheduleDAGMILive::initQueues(), llvm::ScheduleDAGMILive::initRegPressure(), llvm::SIScheduleDAGMI::initRPTracker(), initSUnits(), llvm::ScheduleDAGMI::moveInstruction(), llvm::ScheduleDAGMI::placeDebugValues(), llvm::GCNIterativeScheduler::schedule(), llvm::GCNScheduleDAGMILive::schedule(), llvm::SIScheduleDAGMI::schedule(), and llvm::GCNIterativeScheduler::scheduleRegion().

◆ RegionEnd

The end of the range to be scheduled.

Definition at line 153 of file ScheduleDAGInstrs.h.

Referenced by addSchedBarrierDeps(), llvm::ScheduleDAGMILive::buildDAGWithRegPressure(), buildSchedGraph(), end(), enterRegion(), llvm::ScheduleDAGMILive::enterRegion(), llvm::ScheduleDAGMI::initQueues(), llvm::ScheduleDAGMILive::initRegPressure(), initSUnits(), llvm::ScheduleDAGMI::placeDebugValues(), llvm::GCNIterativeScheduler::schedule(), llvm::GCNScheduleDAGMILive::schedule(), and llvm::GCNIterativeScheduler::scheduleRegion().

◆ RemoveKillFlags

bool llvm::ScheduleDAGInstrs::RemoveKillFlags protected

◆ SchedModel

◆ ScheduleSingleMIRegions

bool llvm::ScheduleDAGInstrs::ScheduleSingleMIRegions = false protected

◆ Topo

◆ TrackLaneMasks

bool llvm::ScheduleDAGInstrs::TrackLaneMasks = false protected

◆ UnknownValue

◆ Uses

The documentation for this class was generated from the following files: